JPH0666324B2 - Bipolar transistor manufacturing method - Google Patents
Bipolar transistor manufacturing methodInfo
- Publication number
- JPH0666324B2 JPH0666324B2 JP62283422A JP28342287A JPH0666324B2 JP H0666324 B2 JPH0666324 B2 JP H0666324B2 JP 62283422 A JP62283422 A JP 62283422A JP 28342287 A JP28342287 A JP 28342287A JP H0666324 B2 JPH0666324 B2 JP H0666324B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- collector
- base
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000012212 insulator Substances 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000000605 extraction Methods 0.000 description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 4
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 4
- 229910001634 calcium fluoride Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 229910004261 CaF 2 Inorganic materials 0.000 description 1
- 238000003877 atomic layer epitaxy Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバイポーラトランジスタの製造方法に関するも
のである。TECHNICAL FIELD The present invention relates to a method for manufacturing a bipolar transistor.
近年，半導体装置の高速化，高集積化に向けて，活発な
研究開発が進められている。特に化合物半導体等のヘテ
ロ接合を利用したバイポーラトランジスタ（以下，ＨＢ
Ｔと称す）は，ベースを高ドーピングしてもエミッタ注
入効率を高く保てるため，高利得で高速性能を有するデ
バイスとして注目されている。このＨＢＴは分子線エピ
タキシャル成長法，有機金属気相成長法，イオン注入技
術等の化合物半導体および単結晶絶縁体の薄膜多層プロ
セス技術の進展に伴い，その実現が可能となった。In recent years, active research and development have been underway toward higher speed and higher integration of semiconductor devices. In particular, bipolar transistors using heterojunctions of compound semiconductors (hereinafter referred to as HB
(Referred to as “T”) is attracting attention as a device having high gain and high speed performance because the emitter injection efficiency can be kept high even if the base is heavily doped. This HBT can be realized with the progress of thin film multi-layer process technology of compound semiconductors and single crystal insulators such as molecular beam epitaxial growth method, metalorganic vapor phase epitaxy method, and ion implantation technology.
ＨＢＴにおいて高速高周波特性を表わす一つの指標であ
る最大発振周波数maxは次式で示される。In the HBT, the maximum oscillation frequency max, which is one index showing the high speed and high frequency characteristics, is expressed by the following equation.
ここで，Tは電流利得遮断周波数，RBはベース抵抗，C
BCはトランジスタの真性領域におけるベース・コレクタ
容量，Cbcはトランジスタの外部領域のベース・コレク
タ寄生接合容量である。 Where T is the current gain cutoff frequency, R B is the base resistance, and C
BC is the base-collector capacitance in the intrinsic region of the transistor, and Cbc is the base-collector parasitic junction capacitance in the external region of the transistor.
又、Tは次式で与えられる。Also, T is given by the following equation.
ここで、CBEはトランジスタの真性領域におけるベース
・エミッタ容量、Cbeは外部領域のベース・エミッタ容
量、gmは相互コンダクタンスである。 Here, C BE is the base-emitter capacitance in the intrinsic region of the transistor, C be is the base-emitter capacitance in the external region, and gm is the transconductance.
(1)，(2)式から明らかなように，ＨＢＴの高速動作を実
現するために，Cbc又はCbeを極力小さくする必要があ
る。これを実現するために従来は，トランジスタが構成
される基板に対し基板の表面側から外部領域に選択的に
高エネルギーで，酸素イオン，水素イオンなどを注入
し，前述の寄生接合部を半絶縁化することにより，その
容量を低減していた。As is clear from Eqs. (1) and (2), it is necessary to minimize C bc or C be in order to realize high-speed operation of the HBT. In order to realize this, conventionally, oxygen ions, hydrogen ions, etc. are selectively injected into the external region from the surface side of the substrate with high energy to the substrate on which the transistor is formed, and the parasitic junction is semi-insulated. However, the capacity has been reduced.
第３図は従来構造のＨＢＴの一例のチップ断面図を示し
たものである。同図においては，半絶縁性GaAs基板１上
にｎ−GaAsからなるコレクタ層２，ｐ−GaAsからなるベ
ース層３，ｎ−AlGaAsからなるエミッタ層４が順次形成
されている。６はトランジスタの真性領域で，実際のト
ランジスタ動作をする場所である。この真性領域の外部
の領域におけるベース・コレクタ寄生接合容量を低減す
るために，外部領域に選択的にイオンを注入して半絶縁
体層５を設けている。なお、エミッタ層４とコレクタ層
２を入れかえた構成にしてCbeを低減させてもよい。FIG. 3 shows a chip cross-sectional view of an example of a conventional HBT. In the figure, a collector layer 2 made of n-GaAs 2, a base layer 3 made of p-GaAs 3, and an emitter layer 4 made of n-AlGaAs are sequentially formed on a semi-insulating GaAs substrate 1. Reference numeral 6 is an intrinsic region of the transistor, which is a place where the transistor actually operates. In order to reduce the base-collector parasitic junction capacitance in the region outside this intrinsic region, the semi-insulating layer 5 is provided by selectively implanting ions into the external region. The emitter layer 4 and the collector layer 2 may be replaced with each other to reduce C be .
このような従来のＨＢＴにおいて，トランジスタの外部
領域におけるベース層とコレクタ層（又はエミッタ層）
とが対向しているため，前述のイオン注入を行なっても
寄生容量は高々３０％から４０％しか低減されない。
又，前述の注入によってベース電極直下のベース層の結
晶構成には欠陥が生ずる。この欠陥は熱処理の後にも一
部残っており，ベース層のキャリヤの一部はトラップさ
れ，その結果RBが大幅に増大する。In such a conventional HBT, the base layer and collector layer (or emitter layer) in the external region of the transistor
Therefore, even if the above-mentioned ion implantation is performed, the parasitic capacitance can be reduced by at most 30% to 40%.
Further, the above-mentioned implantation causes defects in the crystal structure of the base layer immediately below the base electrode. Some of these defects remain after the heat treatment, and some of the carriers in the base layer are trapped, resulting in a large increase in R B.
以上述べたように，Cbc又はCbeが若干低減されてもRBが
大きくなるため，(1)，(2)式から分かるように，このよ
うな従来のＨＢＴから優れた高速高周波特性は期待でき
ないという欠点があった。As described above, since R B increases even if C bc or C be is slightly reduced, as can be seen from Eqs. (1) and (2), excellent high-speed and high-frequency characteristics from such a conventional HBT are There was a drawback that I could not expect.
本発明の目的は，ベース・コレクタ（又はベース・エミ
ッタ）寄生容量が全然なく，かつベース抵抗の小さいバ
イポーラトランジスタの製造方法を提供することにあ
る。An object of the present invention is to provide a method for manufacturing a bipolar transistor having no base-collector (or base-emitter) parasitic capacitance and a small base resistance.
本発明バイポーラトランジスタの製造方法は、半絶縁性
基板上に第１（又は第３）の半導体材料からなるコレク
タ（又はエミッタ）層を成長する工程と，所定のパター
ンを有する第１のマスクを用いて前記コレクタ（又はエ
ミッタ）層を前記半絶縁性基板に達するまで選択的にエ
ッチングする工程と，前記半絶縁性基板の露出部分には
所定の格子常数を有する単結晶絶縁体からなる所定の厚
さの絶縁体層をエピタキシャル成長する工程と，少なく
とも，前記絶縁体層とコレクタ（又はエミッタ）層との
境界を含む領域を露出させた第２のマスクを形成する工
程と，第２の半導体材料からなるベース層を選択的に成
長する工程と，その後に第３（又は第１）の半導体材料
からなるエミッタ（又はコレクタ）層を前記ベース層上
に成長する工程とを含む構成を有している。The method for manufacturing a bipolar transistor of the present invention uses a step of growing a collector (or emitter) layer made of a first (or third) semiconductor material on a semi-insulating substrate, and a first mask having a predetermined pattern. Selectively etching the collector (or emitter) layer until it reaches the semi-insulating substrate, and the exposed portion of the semi-insulating substrate has a predetermined thickness of a single crystal insulator having a predetermined lattice constant. Epitaxially growing the insulator layer, and forming a second mask exposing at least a region including a boundary between the insulator layer and the collector (or emitter) layer, and using a second semiconductor material. Selectively growing a base layer consisting of: and subsequently growing an emitter (or collector) layer of a third (or first) semiconductor material on said base layer. It has a configuration that includes.
本発明の製造方法にて製造されたバイポーラトランジス
タにおいては，ベース層の引出し電極形成用領域は半絶
縁性基板上の絶縁体層に形成されているので、外部ベー
ス層とコレクタ層（又はエミッタ層）とが接触しないた
め，ベース・コレクタ（又はベース・エミッタ）寄生接
合を完全に除去できる。In the bipolar transistor manufactured by the manufacturing method of the present invention, since the extraction electrode forming region of the base layer is formed in the insulator layer on the semi-insulating substrate, the external base layer and the collector layer (or the emitter layer) are formed. ), The base-collector (or base-emitter) parasitic junction can be completely removed.
又、本発明バイポーラトランジスタの製造方法において
は、コレクタ層（又はエミッタ層）を選択エッチングし
てそのあとに絶縁体層をエピタキャル成長させてその上
からベース層を形成するので、欠陥のない良質のベース
層が得られる。Further, in the method for manufacturing a bipolar transistor of the present invention, the collector layer (or the emitter layer) is selectively etched, and then the insulator layer is epitaxially grown and the base layer is formed on the insulator layer. A base layer is obtained.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の製造方法にて製造されたバイポーラト
ランジスタの一実施例を示すＨＢＴチップの断面図であ
る。この実施例は半絶縁性GaAs基板１上にｎ−GaAsから
なるコレクタ層２，ｐ−GaAsからなるベース層３，ｎ−
AlGaAsからなるエミッタ層４を順次に形成したエミッタ
トップＨＢＴである。このＨＢＴにおいて，ベース引出
し電極３３直下のベース層がGaAsの格子定数α＝5.6533
Å（２５℃）に近い格子定数α＝5.4629Å（２５℃）を
有するフッ化カルシウムCaF2からなる単結晶絶縁体層８
上に設けられている。FIG. 1 is a sectional view of an HBT chip showing an embodiment of a bipolar transistor manufactured by the manufacturing method of the present invention. In this embodiment, a semi-insulating GaAs substrate 1 is provided with a collector layer 2 made of n-GaAs, a base layer 3 made of p-GaAs, and n-.
This is an emitter top HBT in which an emitter layer 4 made of AlGaAs is sequentially formed. In this HBT, the base layer immediately below the base extraction electrode 33 has a GaAs lattice constant α = 5.6533.
Single crystal insulator layer 8 made of calcium fluoride CaF 2 having a lattice constant α = 5.4629Å (25 ° C) close to Å (25 ° C)
It is provided above.
第２図は本発明バイポーラトランジスタの製造方法の一
実施例を説明するための工程順に示した半導体チップの
断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip showing steps in order to explain one embodiment of a method for manufacturing a bipolar transistor of the present invention.
まず、第２図(a)に示すように、半絶縁性GaAs基板１上
に厚さ５００nm程度のｎ−GaAs半導体層を成長してコレ
クタ層２を形成する。First, as shown in FIG. 2A, an n-GaAs semiconductor layer having a thickness of about 500 nm is grown on a semi-insulating GaAs substrate 1 to form a collector layer 2.
次に、第２図(b)に示すように、コレクタ層２を部分的
にエッチングによって除去したあとにGaAsと格子整合し
ているフッ化カルシウムを厚さ0.5μｍ程度埋め込むこ
とによって絶縁体層８を形成する。温度５００〜600℃
において、分子線エピタキシャル（ＭＢＥ）法や原子層
エピタキシャル（ＡＬＥ）法を使用すればよいのであ
る。Next, as shown in FIG. 2 (b), the insulator layer 8 is formed by partially removing the collector layer 2 by etching and then burying calcium fluoride lattice-matched with GaAs to a thickness of about 0.5 μm. To form. Temperature 500-600 ℃
In the above, the molecular beam epitaxial (MBE) method or the atomic layer epitaxial (ALE) method may be used.
次に、第２図(c)に示すように、厚さ0.1μｍ程度のSiO2
層12を形成したあとに少なくとも，フッ化カルシウム層
とコレクタ層の境界を含む領域を露出させたマスクを利
用してｐ−GaAs半導体を0.1μｍ程度、温度５００〜600
℃でアトミック・レイヤーエピタキシ（ＡＬＥ）法によ
り埋め込むことによってベース層３を形成する。Next, as shown in FIG. 2 (c), SiO 2 with a thickness of about 0.1 μm is used.
After forming the layer 12, at least a region including the boundary between the calcium fluoride layer and the collector layer is exposed by using a mask, and the p-GaAs semiconductor is about 0.1 μm at a temperature of 500 to 600.
The base layer 3 is formed by embedding it by the atomic layer epitaxy (ALE) method at a temperature of ° C.
次に、第２図(d)に示すように、厚さ２００nm程度のｎ
−AlGaAs半導体層を成長してエミッタ層４を形成する。
最後に，周知の方法でエミッタ電極を形成したあとに所
定のパターンを有するマスクを用いてベース層およびコ
レクタ層を部分的に露出しそれぞれベース電極およびコ
レクタ電極を設ける。その結果，第１図に示したＨＢＴ
が得られる。Next, as shown in FIG. 2 (d), n with a thickness of about 200 nm is used.
-The AlGaAs semiconductor layer is grown to form the emitter layer 4.
Finally, after forming the emitter electrode by a known method, the base layer and the collector layer are partially exposed by using a mask having a predetermined pattern to provide the base electrode and the collector electrode, respectively. As a result, the HBT shown in FIG.
Is obtained.
なお，以上の実施例において、コレクタ層とエミッタ層
を入れかえてもよいことは改めて詳述するまでもなく明
らかなことである。It is obvious that the collector layer and the emitter layer may be replaced with each other in the above embodiments, without needing to reiterate.
以上説明したように本発明の製造方法にて製造されたバ
イポーラトランジスタは，ベース層の引出し電極形成用
領域が半絶縁性基板上の単結晶でかつ基板と格子整合し
ている絶縁体層上に形成されているのでコレクタ層（又
はエミッタ層）と接触しないためベース・コレクタ（又
はエミッタ）寄生接合容量を完全に除去でき、又、ベー
ス抵抗も低く、ＨＢＴの動作周波数を今まで不可能だっ
た200GHZ帯以上に大きく向上できる効果がある。As described above, in the bipolar transistor manufactured by the manufacturing method of the present invention, the extraction electrode forming region of the base layer is a single crystal on the semi-insulating substrate and is on the insulator layer lattice-matched with the substrate. Since it does not contact the collector layer (or emitter layer) because it is formed, the base-collector (or emitter) parasitic junction capacitance can be completely removed, and the base resistance is low, so that the operating frequency of the HBT has been impossible until now. There is an effect that it can be greatly improved above the 200GHZ band.
又、本発明バイポーラトランジスタの製造方法は、ベー
ス層を通してのイオン注入工程を使用せず、エピタキシ
ャル成長法を用いて良質のベース層を形成でき寄生抵
抗、容量の小さなバイポーラトランジスタを提供できる
効果がある。In addition, the bipolar transistor manufacturing method of the present invention has an effect that a high quality base layer can be formed by an epitaxial growth method without using an ion implantation step through the base layer, and a bipolar transistor having a small parasitic resistance and capacitance can be provided.
第１図は本発明の製造方法にて製造されたバイポーラト
ランジスタの一実施例を示すＨＢＴチップの断面図，第
２図(a)〜(d)は本発明バイポーラトランジスタの製造方
法の一実施例を示す工程順に配置した半導体チップの断
面図，第３図は従来のＨＢＴの一例のチップ断面図であ
る。 １……半絶縁性GaAs基板、２……ｎ−GaAsコレクタ層、
３……ｐ−GaAsベース層、４……ｎ−AlGaAsエミッタ
層、５……半絶縁体層、６……トランジスタの真性領
域、８……フッ化カルシウム単結晶絶縁体層、１２……
SiO2層、２２……コレクタ引出電極、３３……ベース引
出電極、４４……エミッタ引出電極。FIG. 1 is a sectional view of an HBT chip showing an embodiment of a bipolar transistor manufactured by the manufacturing method of the present invention, and FIGS. 2 (a) to (d) are an embodiment of the manufacturing method of the bipolar transistor of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip arranged in the order of steps, and FIG. 3 is a cross-sectional view of an example of a conventional HBT. 1 ... Semi-insulating GaAs substrate, 2 ... n-GaAs collector layer,
3 ... p-GaAs base layer, 4 ... n-AlGaAs emitter layer, 5 ... semi-insulating layer, 6 ... intrinsic region of transistor, 8 ... calcium fluoride single crystal insulating layer, 12 ...
SiO 2 layer, 22 ... Collector extraction electrode, 33 ... Base extraction electrode, 44 ... Emitter extraction electrode.
Claims (1)
体材料からなるコレクタ（又はエミッタ）層を成長する
工程と、所定のパターンを有する第１のマスクを用いて
前記コレクタ（又はエミッタ）層を前記半絶縁性基板に
達するまで選択的にエッチングする工程と、前記半絶縁
性基板の露出部分に所定の格子常数を有する単結晶絶縁
体からなる所定の厚さの絶縁体層をエピタキシャル成長
する工程と、少なくとも、前記絶縁体層とコレクタ（又
はエミッタ）層との境界を含む領域を露出させた第２の
マスクを形成する工程と、第２の半導体材料からなるベ
ース層を選択的に成長する工程と、その後に第３（又は
第１）の半導体材料からなるエミッタ（又はコレクタ）
層を前記ベース層上に成長する工程とを含むことを特徴
とするバイポーラトランジスタの製造方法。1. A step of growing a collector (or emitter) layer made of a first (or third) semiconductor material on a semi-insulating substrate, and the collector (or emitter) layer using a first mask having a predetermined pattern. Or an emitter layer is selectively etched until it reaches the semi-insulating substrate, and an insulator layer having a predetermined thickness and made of a single crystal insulator having a predetermined lattice constant in the exposed portion of the semi-insulating substrate. Epitaxial growth, forming a second mask exposing at least a region including a boundary between the insulator layer and the collector (or emitter) layer, and selecting a base layer made of a second semiconductor material. Growth step followed by an emitter (or collector) made of a third (or first) semiconductor material
A step of growing a layer on the base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62283422A JPH0666324B2 (en) | 1987-11-09 | 1987-11-09 | Bipolar transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62283422A JPH0666324B2 (en) | 1987-11-09 | 1987-11-09 | Bipolar transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01124256A JPH01124256A (en) | 1989-05-17 |
| JPH0666324B2 true JPH0666324B2 (en) | 1994-08-24 |
Family
ID=17665327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62283422A Expired - Lifetime JPH0666324B2 (en) | 1987-11-09 | 1987-11-09 | Bipolar transistor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666324B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168049A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Heterojunction bipolar transistor and manufacture thereof |
-
1987
- 1987-11-09 JP JP62283422A patent/JPH0666324B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01124256A (en) | 1989-05-17 |
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