JPH0666331B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to the manufacture of a semiconductor device having an improved silicidation of a source / drain region and a gate electrode. Regarding the method.

(Prior Art) As is well known, a method of siliciding the source / drain region and the gate electrode has been adopted for the purpose of reducing the resistance of the source / drain region and the gate electrode of the MOS transistor. Here, as a silicidation method, a refractory metal layer or the like is selectively deposited on a silicon substrate to be silicidized (first method), or a refractory metal layer or the like is deposited on the entire surface of the substrate. After that, a method (second method) of reacting Si with the refractory metal layer by heat treatment to silicidize only the source / drain regions and the gate electrode is mentioned.

FIG. 4 shows the first method.

First, the field oxide film 2 is formed on the surface of the P-type silicon substrate 1. Subsequently, a gate electrode 4 made of polycrystalline silicon is formed on the element region surrounded by the field oxide film 2 with the gate oxide film 3 interposed therebetween. Then, using the gate electrode 4 as a mask, n-type impurities are introduced into the element region to form N ⁺ -type source / drain regions 5 and 6 (shown in FIG. 4 (a)). Furthermore, the SiO ₂ film 7 is formed on the entire surface.
Are deposited by the CVD method (shown in FIG. 4 (b)). Then, the SiO ₂ film 7 is subjected to reactive ion etching (R
Etching is performed by IE) to leave only the side wall of the gate electrode 4. Here, the remaining SiO ₂ film is used as a spacer 7a (shown in FIG. 4 (c)). The spacer 7a is necessary to insulate the gate electrode 4 from the source / drain regions 5 and 6.

Subsequently, after depositing a tungsten (W) layer on the source / drain regions 5 and 6 and the gate electrode 4, 40
The W layer is silicified by heat treatment at 0 to 600 ° C. to form the silicide layer 8 (shown in FIG. 4 (d)).
Although not shown, a MOS transistor is manufactured by forming an interlayer insulating film, a contact hole, and a lead wire, which are not shown.

FIG. 5 shows the second method.

First, similarly to the first method, after forming the field oxide film 2 on the surface of the silicon substrate 1, the gate electrode 4 is formed on the element region through the gate oxide film 3 and the N ⁺ source. The drain regions 5 and 6 and the spacer 7a are formed. Subsequently, the W layer 11 is formed on the entire surface (illustrated in FIG. 5A). Next, heat treatment is performed to form the silicide layer 12 on the source / drain regions 5 and 6 and the gate electrode 4, and the W layer 11 in other portions is removed by etching (FIG. 5 (c) (illustration). Although not shown, an MO layer is formed by forming an interlayer insulating film, a contact hole and a lead wire.
An S-type transistor is manufactured.

However, according to the conventional manufacturing method, the spacer 7a is required on the side wall of the gate electrode 4 to insulate the source / drain regions 5, 6 from the gate electrode 4. For this reason,
During silicidation, the lower part of the spacer 7a is not silicidized. Therefore, the resistance is high in the non-silicided region, and the drain current is reduced. Further, in the case of the first method, since the selection ratio of Si and SiO ₂ at the time of tungsten deposition is not infinite, a tungsten layer is slightly formed on the field oxide film 2 and the insulation between elements is deteriorated.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the resistance of a source / drain region and thereby increasing the drain current. And

[Structure of the Invention] (Means for Solving Problems) The present invention relates to a step of forming an element isolation region on a surface of a semiconductor substrate, and a gate oxide film in the element region of the substrate surrounded by the element isolation region. A step of forming a gate electrode through the element, a step of ion-implanting a refractory metal or a compound thereof into an element isolation region including the element region and its vicinity, and a second conductivity for forming a source / drain region in the element region. Type impurities, and a step of subjecting the high melting point metal or compound thereof to ion implantation of the high melting point metal or compound thereof to silicidation, and including the high melting point metal or compound thereof in an element region and its vicinity before or after ion implantation in the device isolation region, the ion implantation of Si ⁺ in the isolation region of the device region near to conduct even silicidation in the element isolation region And gist a method for manufacturing a semiconductor device according to symptoms.

(Operation) According to the present invention, after forming the gate electrode, a refractory metal or its compound is ion-implanted into the element region of the semiconductor substrate to form a silicide layer. As a result, almost the entire surface of the source and drain regions is silicidized, a silicide layer can be formed in a wider area in the source / drain regions than in the conventional case, and the drain current can be increased.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG. 1 (reference example 1), FIG. 2 (reference example 2) and FIG. 3 (example).

Reference Example 1 First, a field oxide film is formed on the surface of a P-type silicon substrate 21.
22 formed. Subsequently, a gate electrode 24 made of polycrystalline silicon was formed in the element region surrounded by the field oxide film 22 via a gate oxide film 23 (shown in FIG. 1 (a)). Then, for example, WF ₆ ⁺ is applied with an acceleration voltage of 240 Ke
Ions are implanted into the gate electrode 24 and the source / drain region formation planned portion of the element region under the conditions of V and a dose amount of 1 × 10 ¹⁵ cm ^-2 to form a tungsten (W) layer 25 (first).
Figure (b) illustration). Here, the accelerating voltage was set so that when the thickness of the gate oxide film 23 was, for example, 20 nm, the peak of the concentration of tungsten after ion implantation was at a position deeper than the interface between the gate oxide film 22 and the substrate 21. Further, for example, arsenic is ion-implanted into the element region to form an N ⁺ -type source.
Drain regions 26 and 27 were formed (shown in FIG. 1 (c)).

Next, heat treatment is performed at 400 to 600 ° C. for 30 minutes to silicify the W layer 25, and the source / drain regions 26,
A silicide layer 25 a was formed on the surface of 27 and a silicide layer 25 b was formed on the surface of the gate electrode 24. On this occasion,
Since tungsten does not react with SiO ₂ even if heat treatment is performed, the surface of the field oxide film 22 is not silicidized, and good insulation between elements is maintained. Subsequently, after removing the W layer 25 which is not silicided, an interlayer insulating film 28 is formed on the entire surface. Then, the silicide layers 25a, 25
The interlayer insulating film 28 on b was selectively removed to form a contact hole 29. Further, extraction wirings 30 were formed in these contact holes 29 to manufacture a MOS type transistor (shown in FIG. 1 (d)).

According to the first reference example, after forming the gate electrode 24, a spacer is not provided on the side wall of the gate electrode as in the conventional case, and the WF is previously formed in the element region where the source / drain regions 26 and 27 are to be formed.
_After ion-implanting ₆ ⁺ to form the W layer 25, the source / drain regions 26 and 27 are formed in the element region, and the silicide layer is further formed. Therefore, the tungsten layer 25a is formed on the entire surface of the source / drain regions 26 and 27. Is formed. Therefore, the source
The drain regions 26 and 27 can be made low in resistance to increase the drain current.

Further, since tungsten does not react with SiO ₂ even if heat treatment is performed, the surface of the field oxide film 22 is not silicified, and good insulation between elements can be maintained.

When WF ₆ ⁺ is ion-implanted at a high dose amount of 1 × 10 ¹⁶ cm ⁻² or more in Reference Example 1, there is a concern that insulation between elements may be deteriorated. In such cases, WF ₆ ⁺
After the ion implantation, the surface of the field oxide film 22 is etched by, for example, 50 nm with an aqueous NH ₄ F solution to improve the insulation between the elements.

Further, the work function of the gate electrode 24 can be controlled within the range of 4.9 to 4.5 eV by changing the dose amount of WF ₆ ⁺ .

Reference Example 2 First, similarly to Reference Example 1, after forming the field oxide film 22 on the surface of the P-type silicon substrate 21, the gate electrode 24 was formed on the element region with the gate oxide film 23 interposed therebetween. Continuing,
After forming the source / drain regions 26 and 27, the gate oxide film 24 was selectively etched using the gate electrode 24 as a mask. Next, oxidation is performed. As a result, a thin oxide film 31a having a thickness of 10 to 20 nm is formed on the surfaces of the source / drain regions 26 and 27, and a thickness of about 50 nm is formed around the gate electrode 24.
A thick oxide film 31b was formed (shown in FIG. 2 (a)).
Further, WF ₆ ⁺ was ion-implanted into the source / drain regions 26 and 27 and the gate electrode 24 from above the oxide films 31a and 31b at the same acceleration voltage and dose as in Reference Example 1. Then, heat treatment is performed to form the silicide layer 25a on the surface of the source / drain regions 26 and 27 and the silicide layer 25 on the surface of the gate electrode 24.
b was formed.

Thereafter, similarly to Reference Example 1, after forming the interlayer insulating film 28, the contact hole 29 and the take-out wiring 30 were formed to manufacture a MOS transistor (shown in FIG. 2B).

According to the second reference example, similarly to the first reference example, the resistance of the source / drain regions 26 and 27 can be reduced to increase the drain current, and the insulation between the elements can be improved. Even if the gate electrode 24 is covered with the oxide film 31 as shown in FIG. 2A, silicidation can be achieved by ion implantation of WF ₆ ⁺ and heat treatment.

Example First, a field oxide film 22 is formed on the surface of a P-type silicon substrate 21.
Then, a gate electrode 24 was formed in the element region surrounded by the field oxide film 22 with a gate oxide film 23 interposed therebetween. Subsequently, oxidation was performed to form a thin oxide film 31a in the source / drain region forming planned portion and a thick oxide film 31b around the gate electrode 24 (shown in FIG. 3 (a)). Then
A resist film 41 was formed on the field oxide film 22 except the element region and its periphery. Further, using this resist film 41 as a mask, WF ₆ ⁺ was ion-implanted on the element region and the field oxide film 22 under the same conditions as in Reference Example 1 to form a W layer 42 (shown in FIG. 3B). Further, the resist film
Using 41 as it was as a mask, Si ⁺ was ion-implanted into the element region and the field oxide film 22 (shown in FIG. 3B). This Si ⁺ ion implantation is for silicidizing the surface of the field oxide film 22 not covered with the resist film 41.

Next, the resist film 41 was peeled off (shown in FIG. 3 (C)). Subsequently, after using the gate electrode 24 as a mask to introduce an n-type impurity into the device region, heat treatment was performed.
As a result, N ⁺ type source / drain regions 2 are formed in the element region.
6 and 27 are formed, and source / drain region 2
Silicide layers 42a, 42a extending from the respective surfaces of 6, 27 to the field oxide surface are formed and the gate electrode 24
A silicide layer 42b was formed on the surface of the. Thereafter, after forming the interlayer insulating film 28 by a conventional method, the contact hole 29 and the take-out wiring 30 are formed to manufacture a MOS type transistor (shown in FIG. 3 (d)).

According to the embodiment, similarly to the first embodiment, the resistance of the source / drain regions 26 and 27 can be reduced to increase the drain current. Further, in Reference Example 2 described above, WF ₆ ⁺ is ion-implanted also on the surface of the field oxide film 22 around the element region using the resist film 41 as a mask, and then Si ⁺ is ion-implanted using the resist film 41 again as it is. . As a result, during silicidation, silicide layers 42a and 42a electrically connected to the source / drain regions 26 and 27, respectively, are also formed on the surface of the field oxide film 22 around the element region. Therefore, the source
The contact holes 29, 29 for the drain regions 26, 27 can be formed on the silicide layers 42a, 42a on the surface of the field oxide film 22, and the device can be highly integrated. Further, for the same reason as above, the source / drain regions 26 and 27 and the substrate 21 are
The junction area with and decreases, and the junction capacitance decreases. Therefore,
The speed of the device can be increased.

In addition, although the case where WF ₆ ⁺ is ion-implanted has been described in the above embodiment, the present invention is not limited to this. For example W ⁺ , M
It may be o ⁺ , or a compound ion thereof.

Further, in the embodiment, the NMOS has been described as an example, but the present invention is not limited to this.

[Effects of the Invention] As described in detail above, according to the present invention, the source
It is possible to provide a method for manufacturing a semiconductor device that can reduce the resistance of the drain region and thus increase the drain current.

[Brief description of drawings]

1 (a) to 1 (d) are MOSs according to Reference Example 1 of the present invention.
Sectional view showing a method of manufacturing a transistor
FIGS. 3A and 3B are cross-sectional views showing a method of manufacturing a MOS transistor according to a second embodiment of the present invention in the order of steps, and FIGS. 3A to 3D are MOS according to an embodiment of the present invention. 4A to 4D are cross-sectional views showing a method of manufacturing a MOS transistor in the order of steps, FIGS. 4A to 4D are cross-sectional views showing a method of manufacturing a conventional MOS transistor in the order of steps, and FIGS. 5A and 5B are conventional. FIG. 8 is a cross-sectional view showing the method of manufacturing the other MOS transistor in the order of steps. 21 …… P-type silicon substrate, 22 …… Field oxide film,
23 ... Gate oxide film, 24 ... Gate electrode, 25, 42 ... Tungsten layer (W layer), 25a, 25b, 42a, 42b ... Silicide layer, 26 ... N ⁺ type source region, 27 ... N ⁺ type drain region, 28 ... Interlayer insulating film, 29 ... Contact hole, 30 ... Extraction wiring, 31a, 31b ... Oxide film, 41
…… Resist.

Claims (2)

[Claims] 1. A step of forming an element isolation region on a surface of a semiconductor substrate, a step of forming a gate electrode in an element region of the substrate surrounded by the element isolation region through a gate oxide film, and the element region. And a step of ion-implanting a refractory metal or a compound thereof into an element isolation region including the vicinity thereof, a step of introducing a second conductivity type impurity for forming source / drain regions into the element region, and a heat treatment A step of siliciding a region where a refractory metal or a compound thereof is ion-implanted, before or after ion-implanting the refractory metal or a compound thereof into a device isolation region including a device region and its vicinity, Si
^A method of manufacturing a semiconductor device, wherein ⁺ is ion-implanted into an element isolation region near the element region, and silicidation is also performed in the element isolation region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an oxidation step is performed after forming the gate oxide film and before ion-implanting a refractory metal or a compound thereof. .