JPH0666420B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention provides a base layer of a differential negative resistance element and a channel layer of a field effect transistor element in integrating a differential negative resistance element and a field effect transistor element. By using the same epitaxially grown layer, monolithic integration of both devices can be reasonably and easily made possible.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which a differential negative resistance element and a field effect transistor element are monolithically integrated, and a manufacturing method thereof.

Recently, a lot of research has been done to realize a semiconductor device having a new function by using a heterojunction of a compound semiconductor, particularly a resonant tunneling barrier structure. Among them, a differential negative resistance element is a next-generation device having a function as described below. It is expected that a circuit utilizing this will be realized as a device of.

[Conventional technology]

A film side sectional view of a resonant tunneling hot electron transistor (RHET), which is an example of a differential negative resistance element, is shown in FIG.
Shown in Figure 2A. This RHET is a semi-insulating GaAs substrate 21, semiconductor layers 22 to 26 as shown in the following examples, an emitter electrode 27, a base electrode 28,
And a collector electrode 28.

This RHET has a resonance tunneling barrier structure in which the barrier layer 25 between the emitter and the base is a quantum well structure, and the GaAs well layer 25b is sandwiched between two AlGaAs barrier layers 25a and 25c. Is a discrete value called the resonance level.

As shown in the energy band diagram in FIG. 2B, the differential negative resistance element RHET operates by applying a positive potential to the emitter 26 to the base 24 and the collector 22, but the energy level of the electrons in the emitter is changed. Is equal to the resonance level E ₁ of the electron in the quantum well, that is, the emitter 26-base 24
When the base voltage (peak voltage) between them is V _BE ≈2E ₁ / q (q is the charge of an electron), an electron (hot electron) is injected from the emitter to the base 24 by the resonant tunneling effect, and this electron flows through the base. It passes at a very high speed, crosses the collector barrier 23, and reaches the collector 22.

If the base voltage V _BE is smaller or larger than 2E ₁ / q, the condition of resonance tunneling is not satisfied, and the electron injection amount into the base 24,
That is, the collector current is reduced. Therefore, as shown in the example of the grounded-emitter collector current measured at a temperature of 77K shown in Fig. 3, the collector current is a value (V _BE ) _{RESO of the} base voltage V _BE.
Shows the maximum value.

Therefore, the inverter gate using this RHET is
The output shows a decrease in output (V _BE ), a minimum value at _RESO , and an increase again in response to an increase in V _BE , which shows a differential negative resistance characteristic. For example, if composed of transistors, 7 to 8 elements are required. 2-input exclusive-NOR (EXCLUSIVE-NOR)
As shown in FIG. 4, the gate can be composed of one RHET and three resistance elements.

A B C 1 1 1 1 0 0 1 1 0 1 0 1 0 0 In addition to the above-mentioned RHET, the differential negative resistance element is, for example, a resonant tunneling bipolar transistor having an npn bipolar transistor structure in which the base layer is p-type. (RBT) and so on. Since such a differential negative resistance element is effective in reducing the number of elements in the logic circuit and shortening the delay time, it is different from the transistor element having the normal switching function when the required logic circuit is constructed. It is strongly desired to integrate the negative resistance element.

[Problems to be Solved by the Invention]

However, the differential negative resistance element and the field effect transistor element differ in the multilayer structure of the semiconductor layer, and an appropriate multilayer structure of the semiconductor layer and a manufacturing method become a problem in advancing monolithic integration.

[Means for Solving the Problems]

The problem is that the differential negative resistance element and the field effect transistor element are formed on the same semiconductor substrate, and the base layer of the differential negative resistance element and the channel layer of the field effect transistor element are the same epitaxial growth layer. This is solved by a semiconductor integrated circuit device according to the present invention.

Further, this semiconductor integrated circuit device has a differential semiconductor that epitaxially grows a required semiconductor layer on a semiconductor substrate to selectively remove a part of the semiconductor layer and makes ohmic contact with the semiconductor layer in a region where the selective removal is not performed. The emitter electrode of the negative resistance element and the gate electrode of the field effect transistor element that makes Schottky contact with the semiconductor layer exposed by the selective removal are formed of the same metal layer, and ohmic contacts are formed on the same semiconductor layer. This is easily realized by the method for manufacturing a semiconductor integrated circuit device according to the present invention, in which the base electrode of the differential negative resistance element and the source and drain electrodes of the field effect transistor element that are in contact are formed of the same metal layer.

[Action]

In the semiconductor integrated circuit device according to the present invention, the base layer in the semiconductor layer necessary for the differential negative resistance element epitaxially grown on the semiconductor substrate is also used as the channel layer of the field effect transistor element.

In this embodiment, the uppermost layer of the epitaxial growth layer has a composition and impurity concentration suitable for ohmic contact, and a part of these semiconductor layers is selectively removed until a semiconductor layer suitable for Schottky contact is exposed, The emitter electrode of the differential negative resistance element and the Schottky gate electrode of the field effect transistor element are formed of the same metal layer.

Further, the base electrode of the differential negative resistance element and the source and drain electrodes of the field effect transistor element are disposed in the same metal layer in direct or indirect ohmic contact with the base layer.

According to the present invention, it is possible to monolithically integrate a differential negative resistance element and a Schottky barrier field effect transistor element rationally and easily as in the above-described example, and a high performance and high integration semiconductor integrated circuit is obtained. The device is realized.

〔Example〕

 The present invention will be specifically described below with reference to examples.

Embodiment 1 FIG. 1 is a schematic sectional view of a semiconductor device comprising an RHET and a Schottky barrier type FET which is an embodiment of the present invention, and FIGS. 5A to 5E are schematic sectional views of the semiconductor device during the manufacturing process. It is a figure.

See FIG. 5A: The following semiconductor layers are sequentially grown on the semi-insulating GaAs substrate 1 by, for example, the molecular beam epitaxial growth method.

The emitter layer 6 has a three-layer structure, and is thin Al
The GaAs layer 6b functions as an etching stop layer in the etching process described later, and is formed according to the thickness of the lower emitter layer 6a.
The FET can be an enhancement type or an enhancement type, resulting in a thin enhancement type.

“A” indicates a region for forming RHET, and “B” indicates a region for forming a Schottky barrier field effect transistor (MES FET) device.

See FIG. 5B: An element isolation region 8 is formed in this semiconductor substrate by selective ion implantation of boron (B), oxygen (O) or the like.
Element isolation can also be achieved by forming a V (or U) trench insulator or employing mesa etching.

The RHET formation region A is covered with a mask 16 of SiO ₂ or the like,
For example, a reactive ion etching method using CCl ₂ F ₂ was used to etch AlGaAs layer 6b as a stop layer,
ET n-type InGaAs of element formation region B and element isolation region 8
The contact layer 7 and the n-type GaAs emitter layer 6c are selectively removed.

See FIG. 5C: For example, by patterning a conductor layer formed by sputtering WSi to a thickness of about 400 nm, the emitter electrode 11 of the RHET and the emitter electrode 11 are formed.
The gate electrode 14 of the MES FET element is formed. In this case, the emitter electrode on the n-InGaAs contact layer 7 becomes an ohmic contact and the gate electrode 14 on the n-AlGaAs layer 6b becomes a Schottky contact.

See FIG. 5D: A mask (not shown) having an opening formed in the RHET formation region A is provided, and the RHET emitter electrode 11 is formed by, for example, a reactive ion etching method using CCl ₂ F _2.
The n-type InGaAs contact layer 7 in the RHET formation region A and the n-type InGaAs contact layer 7 are formed by etching using the AlGaAs layer 6b as a stop layer with the mask as a mask.
The GaAs emitter layer 6c is removed to define the emitter region.

Then, for example, gold germanium / gold (AuGe / Au) is used to form the base electrode 12 of the differential negative resistance element and the source / drain electrode 15 of the MES FET element by the normal lift-off method.

See FIG. 5E: Outside the base electrode 12, etching is performed until the n-type GaAs collector layer 2 is exposed, and a collector electrode 13 of AuGe / Au or the like is formed here.

Then, for example, heat treatment is performed at a temperature of 450 ° C. for about 30 seconds to perform AuG
e and the semiconductor substrate are alloyed to form alloyed regions 12A, 13A and
15A is formed, but the alloyed area 12A of the base electrode 12 of the differential negative resistance element and the alloyed area 15A of the source / drain electrode 15 of the MES FET element reach the n-type GaAs base layer 4 and reach the n-type GaAs. The depth does not reach the collector layer 2.

In the present embodiment, the RHET and MES FET elements show the same good characteristics as when they are formed independently, and the intended operation is sufficiently achieved by forming a logic circuit with these elements.

Example 2 FIG. 6 shows the RHET and Schottky barrier type of Example 1.
It is a schematic sectional drawing of the semiconductor device similar to the semiconductor device which consists of FET. This semiconductor device is the same as the semiconductor device of Example 1 except that (a) there is no base electrode of RHET and (b) the V-groove insulator isolation is adopted for element isolation. Therefore, the same reference numerals in FIG. 6 as those in FIG. 1 represent the same components. In this case, since the n-GaAs layer 4 which is the base layer of RHET is also the channel layer of FET, the base of RHET and the source of FET are directly connected. Therefore, the circuit of the semiconductor device of the second embodiment is as shown in FIG. 7, and in the semiconductor device of the first embodiment, the base electrode 12 and the source electrode 15 are connected by wiring (not shown). It will constitute a circuit.

The manufacturing process of this semiconductor device is the same as the manufacturing process of the first embodiment except for the following two points.

(A) After the predetermined semiconductor layers 2 to 7 are formed, V grooves are formed by anisotropic etching instead of ion implantation for element isolation, and the V grooves are formed by SiO ₂ , polycrystalline silicon, or the like. Fill with insulator 17 of.

(B) Instead of forming the three electrodes of the base electrode, the source electrode and the drain electrode in Example 1, the drain electrode
Only 15 is formed by AuGe / Au by the lift-off method.

FIG. 8 shows an energy band diagram of RHET in the non-biased state in the semiconductor devices of Examples 1 and 2 (note that the energy band diagram in the biased state is almost the same as that in FIG. 1B). Also, the energy band diagram of the Schottky barrier type FET is shown in Fig. 9A (non-biased state) and
FIG. 9B (bias state in which a negative voltage V _G is applied to the gate electrode 4) is shown. Since the RHET collector barrier layer (i-AlGaAs layer) 3 is below the FET channel layer 4, the Vth of the FET is improved. That is, as shown in FIG. 9A, the carriers consisting of the electrons existing in the channel layer 4 in the gate non-bias state are pushed out by the application of the gate bias V _G, and the boundary between the ON and OFF states of the transistor is generated. It will be clear.

Embodiment 3 In the semiconductor devices of Embodiments 1 and 2, the field effect transistor is a Schottky barrier type FET, but instead, a heterojunction type FET that generates and uses a two-dimensional electron gas (2DEG) is formed. You can
In this case, the layer structure of the semiconductor layer epitaxially grown on the semi-insulating GaAs substrate is substantially the same as that of the first embodiment, but the RHET collector / barrier layer 3 is formed of n-AlGaAs (i- AlGaAs) as an electron supply layer,
Then, the base layer 4 of the RHET is formed of i-GaAs (n in the first embodiment,
-GaAs) to generate a two-dimensional electron gas here. Therefore, the semiconductor layers sequentially grown on the semi-insulating GaAs substrate are as follows.

Semiconductor layer composition 2: collector n-GaAs 3: collector barrier n-AlGaAs 4: base i-GaAs 5: base barrier 5a i-AlGaAs 5b i-GaAs 5c i-AlGaAs 6: emitter 6a n-GaAs 6b i- AlGaAs 6c n-GaAs 7: Contact A semiconductor device including n-InGaAs RHET and a heterojunction type FET is manufactured in the same manner as in the manufacturing process of the first or second embodiment.

The energy band diagram of this RHET in the non-biased state is shown in FIG. 10A. The two-dimensional electron gas (2DE) near the collector barrier layer (n-AlGaAs) 3 of the base layer (i-GaAs) 4
G) occurs. Energy band diagrams of the heterojunction type FET are shown in FIG. 10B (non-biased state) and FIG. 10C (biased state, a negative voltage V _G is applied to the gate). This heterojunction type FET is a normally-on (depletion) type FET, and the channel layer 4 (that is, the base layer: i-GaAs layer) is depleted in the bias state and the OF
It becomes F state. In addition, n-Ga which is a contact layer in FET
A normally-off (enhancement) type may be used depending on the thickness of the As layer 6. The FET operates at a high speed by the two-dimensional electron gas, and the RHET maintains a low base resistance and has a thin base layer, so that the gain can be improved and the speed can be increased.

Example 4 A semiconductor device can be manufactured by combining a differential negative resistance element with a Schottky barrier FET as a resonance base transistor (RBT) replacing RHET.

As shown in FIG. 11A, the following semiconductor layers are sequentially formed on the semi-insulating GaAs substrate 31 by the molecular beam epitaxial growth method.

Semiconductor layer composition 32: collector n-GaAs 34: base p-GaAs 35: emitter barrier 35a i-AlGaAs 35b i-GaAs 35c i-AlGaAs 36: emitter n-AlGaAs 37: contact n-InGaAs "C" is RBT A formation region, "B", indicates a region where a Schottky barrier type FET is formed. Element separation (not shown)
Is achieved by the ion-implanted region in Example 1 or the V-groove insulator in Example 2.

S that is a little larger than the emitter electrode in the RBT region C
Cover the contact layer 37 with a mask (not shown) such as iO ₂
The contact layer 37, the emitter layer 36, and the emitter / barrier layer 35 are selectively removed by a dry etching method,
The base layer 34 is exposed as shown in FIG. During this etching, the upper portion of the base layer 34 is also etched.
After removing the mask 16, a resist pattern (not shown) having openings for the emitter electrode and the gate electrode is formed on the exposed surface, WSi is deposited by sputtering, and the resist pattern is removed to form a contact. An emitter electrode 41 on layer 37 and a gate electrode 44 on base layer 34 are formed simultaneously. In order to form the collector electrode, a resist pattern is formed on the exposed surface, and the upper portions of the base layer 34 and the collector layer 32 are selectively removed by a dry etching method. Next, a resist pattern having openings for electrodes is formed on the entire surface, gold germanium / gold (AuGe / Au) is deposited by vapor deposition, and the resist pattern is removed to remove the resist pattern on the base (p-GaAs) layer 34. A base electrode 42, a source electrode 45s and a drain electrode 45d of the FET, and a collector electrode 43 are simultaneously formed on the collector (n-GaAs) layer 32. In this way, RBT and Schottky barrier type F
A semiconductor device composed of ET is obtained.

The energy band diagram of this RBT in the non-biased state is shown in FIG. 12A. The energy band diagrams of the Schottky barrier type FET are shown in Figure 12B (non-biased state) and 1
Shown in Figure 2C (biased state). This Schottky barrier type FET has a P channel in which carriers are holes. In this embodiment, since it is a normally-on type FET, when no voltage is applied to the gate electrode (when there is no bias), the channel layer (that is, p-Ga) is formed in the channel.
A hole is generated in the As base layer (34) and the FET is turned on. When a positive voltage is applied to the gate electrode + V _G, the channel layer is turned off depleted. At this time, n-GaAs
Since the collector layer 32 is below the channel layer 34 of the FET and acts as a barrier, the Vth characteristic of the FET is improved.

〔The invention's effect〕

As described above, according to the present invention, monolithic integration of a differential negative resistance element and a field effect transistor element can be reasonably and easily performed, and both elements can be arbitrarily selected when forming a logic circuit or the like. Therefore, the number of elements can be significantly reduced and the delay time can be shortened.

[Brief description of drawings]

Figure 1 shows the RHET and Schottky barrier type according to the present invention.
2A is a schematic perspective view of a semiconductor device including a FET, FIG. 2A is a schematic cross-sectional view of RHET (differential negative resistance element), and FIG. 2B is a peak voltage (V _BE ) applied to RHET of FIG. FIG. 3 is an energy band diagram of the above, FIG. 3 is a graph showing the voltage-current characteristics of the RHET of FIG. 1, FIG. 4 is a circuit diagram of the EXCLUSIVE-NOR gate, and FIGS. 5A to 5E. FIG. 6 is a schematic cross-sectional view of the semiconductor device illustrating the manufacturing process of the semiconductor device of FIG. 1, and FIG. 6 is a schematic cross-sectional view of a semiconductor device including an RHET and a Schottky barrier type FET according to another embodiment of the present invention. FIG. 7 is a circuit diagram of the semiconductor device of FIG. 6, FIG. 8 is an energy band diagram of RHET of the semiconductor device according to the present invention in a non-biased state, and FIGS. 9A and 9B. The figure shows a non-biased Schottky barrier type FET of a semiconductor device according to the present invention. FIG. 10A is an energy band diagram of a RHET of a semiconductor device according to the present invention in which a two-dimensional electron gas is generated, and FIG. 10B and FIG. FIGS. 11A and 11B are energy band diagrams of a heterojunction type FET of a semiconductor device according to the present invention in which a two-dimensional electron gas is generated, in a non-biased state and a biased state. FIGS. 11A and 11B are composed of RBT and Schottky barrier type FET. FIG. 12A is a schematic cross-sectional view of a semiconductor device illustrating a manufacturing process of a semiconductor device according to the present invention, FIG. 12A is an energy band diagram of RBT in a non-biased state, and FIGS. 12B and 12C are RBT and one embodiment. FIG. 3 is an energy band diagram in a non-bias state and a bias state of the Schottky barrier type FET manufactured in FIG. A: RHET formation region, B: Field effect transistor formation region, C: RBT formation region, 1 ... Semi-insulating GaAs substrate, 2 ... Collector layer, 3 ... Collector barrier layer, 4 ... Base layer , 5 ... Emitter barrier layer (quantum well structure), 5a, 5b ... AlGaAs barrier layer, 5b ... GaAs well layer, 6 ... Emitter layer, 6a, 6c ... GaAs layer, 6b ... AlGaAs layer 7 ... … Contact layer, 11 …… RHET emitter electrode, 12 …… RHET base electrode, 13 …… RHET collector electrode, 14 …… FET gate electrode, 15s …… FET source electrode, 15d …… FET drain Electrodes, 12A, 13A, 15A ... Alloyed areas.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/73 8427-4M H01L 29/72

Claims (8)

[Claims] 1. A differential negative resistance element and a field effect transistor element are formed on the same semiconductor substrate, and a base layer of the differential negative resistance element and a channel layer of the field effect transistor element are the same epitaxial growth layer. And a semiconductor integrated circuit device. 2. A differential negative resistance element is a resonant tunneling hot electron transistor (RHET) and a field effect transistor element (FET) is a Schottky barrier type field effect transistor. The device according to the item. 3. A device according to claim 1, wherein the differential negative resistance element is a resonant tunneling hot electron transistor (RHET), and the field effect transistor element is a heterojunction type field effect transistor. . 4. The device according to claim 1, wherein the differential negative resistance element is a resonant tunneling bipolar transistor (RBT), and the field effect transistor element is a Schottky barrier type field effect transistor. . 5. A differential negative resistance element and a field effect transistor element formed on one semiconductor substrate, wherein a base layer of the differential negative resistance element and a channel layer of the field effect transistor element are the same. A method of manufacturing a semiconductor integrated circuit device, which is an epitaxial growth layer, comprises epitaxially growing a required semiconductor layer on a semiconductor substrate to selectively remove a part of the semiconductor layer, and to remove a portion of the region where the selective removal is not performed. The emitter electrode of the differential negative resistance element that makes ohmic contact with the semiconductor layer and the gate electrode of the field effect transistor element that makes Schottky contact with the semiconductor layer exposed by the selective removal are simultaneously formed in the same conductor layer, and A base electrode of the differential negative resistance element that makes ohmic contact with the same semiconductor layer, and the field effect transistor. The method of manufacturing a semiconductor integrated circuit device characterized by comprising the step of simultaneously forming the source of the element, and a drain electrode of the same conductive layer. 6. A semi-insulating GaAs substrate is used as the semiconductor substrate, and an n-GaAs layer of a collector layer and an i-type of a collector barrier layer for the differential negative resistance element as the semiconductor layer.
AlGaAs layer, n-GaAs layer of base layer, i-AlGaAs / i- of emitter barrier layer having a resonant tunneling barrier structure
A GaAs / i-AlGaAs multilayer, an emitter layer n-GaAs layer and an emitter contact layer n-InGaAs layer are sequentially epitaxially grown, and for the field effect transistor, the emitter contact layer n-AlGaAs layer and the emitter layer. 6. The method according to claim 5, wherein a part of the n-GaAs layer of the above is selectively etched away, and the gate electrode is formed on the remaining n-GaAs layer of the emitter layer. 7. A semi-insulating GaAs substrate is used as the semiconductor substrate, and an n-GaAs layer of a collector layer and an n-type of a collector barrier layer are used for the differential negative resistance element as the semiconductor layer.
AlGaAs layer, i-GaAs layer of base layer, i-AlGaAs / i- of emitter barrier layer having resonance tunneling barrier structure
A GaAs / i-AlGaAs multilayer, an emitter layer n-GaAs layer and an emitter contact layer n-InGaAs layer are sequentially epitaxially grown, and for the field effect transistor, the emitter contact layer n-AlGaAs layer and the emitter layer. 6. The method according to claim 5, wherein a part of the n-GaAs layer of the above is selectively etched away, and the gate electrode is formed on the remaining n-GaAs layer of the emitter layer. 8. A semi-insulating GaAs substrate is used as the semiconductor substrate, and for the differential negative resistance element as the semiconductor layer, an n-GaAs layer of a collector layer, a p-GaAs layer of a base layer,
I-AlGaAs / i-GaAs / i-AlGaAs multilayer of emitter barrier layer having resonance tunneling barrier structure, n-AlGaAs layer of emitter layer and n-InGa of emitter contact layer
An As layer is sequentially epitaxially grown, and for the field effect transistor, an n-InGaAs layer of the emitter contact layer, an n-AlGaAs layer of the emitter layer, and an i-AlGaAs / i-GaAs / of the emitter barrier layer. i-AlGa
As multi-layer is selectively etched, and p-
The method of claim 5 wherein the gate electrode is formed on a GaAs layer.