JPH0666439B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the structure of a memory device using an insulated gate field effect transistor.

[Conventional technology]

For a storage device mounted on the surface of a semiconductor substrate such as a silicon single crystal, the information storage part is composed of one insulated gate field effect transistor and one capacitance part for the highest density and the highest capacity. Considered suitable. In such a situation, in order to increase the capacity to 1 megabit or more, a method of forming a capacitor portion having a large occupied plane area of a semiconductor memory device on a side wall of a groove extending in a semiconductor substrate is disclosed in Japanese Patent Publication No. Sho 58-.
It is disclosed in Japanese Patent No. 12739.

[Problems to be solved by the invention]

In the above-described conventional information storage capacitor section using the groove surface, as shown in FIG. 4 or FIG. 5, the information charges contact the insulator formed on the groove surface as the dielectric film 401. Of the dielectric film 401 shown in FIG. 4 and the silicon substrate, that is, the capacitance portion composed of the insulator capacitance formed by the capacitance electrode 402 and the depletion layer capacitance formed on the silicon substrate surface 403 on the side wall of the groove. Accumulates at the interface. Therefore, when the density is increased and the distance between the information storage portions becomes narrow, electrical interference between the information storage portions becomes remarkable and normal information storage becomes impossible. This is because the depletion layer on the surface 403 of the silicon substrate spreads due to the potential of the information storage. This is because punch-through is likely to occur, and the stored information charges are transferred to another adjacent information storage capacitor section. Furthermore, since this depletion layer increases the soak current,
The accumulated charges are likely to disappear. Furthermore, soft errors frequently occur due to the transmission of α particles.

For this reason, the conventional method has a fatal drawback for increasing the density of the semiconductor memory device.

[Means for solving problems]

According to the present invention, the capacitance portion of the information storage portion including one MOS transistor and one capacitance portion is dug along the inside of the semiconductor substrate and includes a high-concentration impurity. A film, further covering this dielectric film, a first capacitance electrode, further covering this capacitance electrode with a second dielectric film and further this second dielectric film, and electrically connecting to the semiconductor substrate. The second capacitance electrode is formed, and the information charges are accumulated in the first capacitance electrode.

In the present invention, unlike the prior art, information charges are not accumulated on the semiconductor substrate side, and only serve as the counter electrode of the first capacitance electrode, like the second capacitance electrode.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view of an embodiment of the present invention, FIG. 2 is a plan view of two information storage units, and FIG. 3 is an equivalent circuit diagram. Furthermore, FIGS. 6 to 13 are sectional structural views showing the manufacturing process of the present invention.

P with a specific resistance of 0.001 to 0.02 Ω-cm Type on silicon substrate 101
With a specific resistance of 0.1-10 Ω-cm and a film thickness of 0.5-5 μm
A film thickness is formed on the silicon semiconductor surface on which the thin film layer 102 is formed.
It was composed of 0.2-1.0 μm insulating film such as silicon oxide film.
Element isolation region 103 is formed with channel stopper region 104
To do. From the surface of such a silicon thin film layer, P Type silico
A groove having a depth of 2 to 10 μm is formed on the substrate 101,
First, such as a silicon oxide film or a silicon nitride film on the groove surface of
The dielectric film 105 is formed. Further cover this dielectric film 105
Then, polysilicon or silicide containing N-type impurities
The first capacitor electrode 106 composed of is formed.

Furthermore, the MOS transistor for taking in and out information has a gate electrode 1
07, gate insulating film 108, N which becomes a source or drain region
⁺ Region 109. Here, one side of the N ⁺ region 109 is electrically connected to the first capacitance electrode 106 so that the information charge is stored in the first capacitance electrode 106.

Furthermore, a second dielectric film 110 is formed on the surface of the first capacitor electrode 106.
Is formed of a silicon oxide film or a silicon nitride film,
By covering the second dielectric film 110, the second capacitor electrode 111 is
With P-type polysilicon or silicide containing concentration impurities
Form. Here, the second capacitor electrode 111 and P Type silicon
The substrate 101 is electrically connected.

Thus, the electrode wiring 113 is formed on the interlayer insulating film 112, and the information storage unit of the present invention is completed. Here, the gate electrode 107 becomes the wort line of the semiconductor memory device, and the electrode wiring 113 becomes the bit line.

FIG. 2 is a plan view when the information storage unit of the present invention is applied to a memory cell array. Where word line 201 bit line 2
02 are arranged vertically and horizontally, and the capacitive portion is the first dielectric film 203,
The first capacitance electrode 204, the second dielectric film 205, and the second capacitance electrode 206 are included. Here, the contact hole 207 is for connecting the bit line 202 and the N ⁺ region 109 of FIG. As shown in FIG. 3, the present invention does not have the depletion layer capacitance as in the prior art shown in FIGS. 4 and 5.
A first capacitor made of the first dielectric film and a second capacitor made of the second dielectric film are present in parallel. For this reason, the planar density of the capacitance is increased and the depletion layer is scarcely present, eliminating the problems that occurred in the case of the conventional technique.

Next, referring to FIGS. 6 to 13, the manufacturing method of the present invention will be described.
Will be described in detail. As shown in Fig. 6, the specific resistance is 0.001 to 0.02.
Ω-cm P -Type silicon substrate 601 has a specific resistance of 0.1-10
Ω-cm, P-type silicon thin film layer 602 with a thickness of 0.5-5 μm
After depositing by epitaxial growth or CVD method
Device that selectively converts the thin film layer 602 to silicon oxide
The channel stopper region 604 is formed while forming the isolation region 603.
Also forms. Then patterned as shown in FIG.
Insulating film with mask material 605 for etching silicon substrate
Reactive silicon thin film layer 602 and silicon substrate 601
Ion etching is performed to form the capacitance groove 606, which is shown in FIG.
As shown in the figure covering the side wall of the capacitor groove, the film thickness is 40 to 400Å
Forming a thin silicon oxide film or silicon nitride film
A dielectric film 607 is formed.

After that, as shown in FIG. 9, when the entire surface is covered and a polysilicon or silicide film 608 containing N-type impurities is deposited and then heat treatment is performed, the N-type impurities are thermally diffused and the P-type silicon thin film layer 602 part is formed. An N ⁺ -type region 609 is formed at. Next, when the polysilicon or silicide film 608 is subjected to reactive ion etching, as shown in FIG. 10, the film remains only on the side wall and the other part is removed to form the first capacitor electrode 610.

Next, as shown in Fig. 11, thin silicon with a film thickness of 100 to 400 Å
After forming the insulating film 611 such as an oxide film or a silicon nitride film
Perform reactive ion etching. The same as above
Similarly, the insulating film 611 remains only on the side wall and the other part is removed.
It Thus, as shown in FIG. 12, the second dielectric film 612 is
P-type polysilicon formed and further containing high-concentration impurities
Alternatively, the second capacitor electrode 613 is formed with a silicide film.
It Here, this second capacitance electrode 613 and P Type silicon base
It is electrically connected to the plate 601. Next, as shown in FIG.
The interlayer insulating film 614 is formed by thermal oxidation, and the mask material 605 is also removed.
It Thus, the capacity part of the information storage part of the present invention is formed.
It After that, if the MOS transistor is formed by a known method,
The information storage unit of the present invention shown in FIG. 1 is completed.

As can be seen from these examples, in the present invention, information charges are accumulated on the first capacitance electrode side above the groove capacitance portion through the insulated gate field effect transistor. Furthermore, the use of the semiconductor substrate having a high concentration of impurities plays a role of suppressing the inversion of the silicon surface on the side wall of the trench and preventing the capacitance value from decreasing. Therefore, it should be noted that, as an alternative to the use of the semiconductor substrate having a high concentration of impurities, a method of using a substrate having a normal concentration and introducing the high concentration impurities only into the sidewall of the groove by thermal diffusion or the like has the same effect.

Furthermore, the present invention is further developed to provide a third dielectric film, a third dielectric film, and a third dielectric film.
It is also noted that it is possible to sequentially form the fourth capacitor electrode and increase the planar density of the capacitor.

〔The invention's effect〕

As described above, according to the present invention, a groove is formed in a semiconductor substrate and a plurality of dielectric films and a plurality of capacitor electrodes are formed on the side wall of the groove. By doing so, the planar density of the capacitance is increased, and as described above, the electric interference between the information storage units is eliminated, and the information storage unit intervals can be narrowed. Furthermore, since the information charges are stored in the capacitor electrode formed on the dielectric film that is an insulator, the leak current is significantly reduced, and the information retention time is lengthened. Further, the present invention has an effect that the soft error due to α particles is sharply reduced.

Furthermore, in the present invention, the counter electrode potential of the capacity electrode for storing the information charge can be taken by the semiconductor substrate, so that the layout is very simple.

[Brief description of drawings]

 FIG. 1 is a vertical sectional view showing an embodiment of the present invention.
1 is a plan view of FIG. 1, and FIG. 3 is an equivalent circuit diagram of FIG.
It FIG. 4 is a sectional view of a conventional information storage capacity section,
FIG. 5 is an equivalent circuit diagram of FIG. Figures 6 to 13
FIG. 4 is a sectional structural view showing a manufacturing process of an embodiment of the present invention.
It 101 …… P Silicon substrate, 102 ... Silicon thin film layer, 10
3 ... Element isolation area, 104 ... Channel stopper area, 10
5 ... First dielectric film, 106 ... First capacitance electrode, 107 ...
… Gate electrode, 108 …… Gate insulating film, 109 …… N⁺region,
110: second dielectric film, 111: second capacitance electrode, 112
...... Interlayer insulating film, 113 ...... Electrode wiring, 201 ...... Word line,
202 ... bit line, 203 ... first dielectric film, 204 ... first
1 ... Capacitive electrode, 205 ... second dielectric film, 206 ... second
Capacitance electrode, 401 ... Dielectric film, 402 ... Capacitance electrode, 403 ...
… Silicon substrate surface, 601 …… P Silicon substrate, 602 ...
… Silicon thin film layer, 603 …… Element isolation region, 604 …… Cha
Flannel stopper area, 605 ... mask material, 606 ... capacity groove,
607 ... first dielectric film, 608 ... polysilicon or silicon
Membrane, 609 …… N⁺Mold region, 610 ... first capacitance electrode, 611
...... Insulating film, 612 ...... Second dielectric film, 613 ...... Second volume
Quantity electrode, 614 ... Interlayer insulation film.

Claims (4)

[Claims] 1. An information storage unit includes one MOS transistor and one.
In a semiconductor memory device including a plurality of capacitance sections, a first dielectric film is formed on a sidewall of a groove formed by the capacitance section extending inside a semiconductor substrate. To form a first capacitance electrode, form a second dielectric film on the first capacitance electrode, and form a second capacitance electrode by covering the second dielectric film. And a first capacitance electrode electrically connected to a source or drain region of a MOS transistor, and a second capacitance electrode electrically connected to a semiconductor substrate. . 2. The semiconductor according to claim 1, wherein the side wall of the groove formed extending inside the semiconductor substrate contains an effective impurity in an impurity concentration of 10 ¹⁸ to 10 ²¹ atoms / cm ^3. Storage device. 3. The semiconductor substrate has an impurity concentration of 10 ¹⁸ -10.
Film thickness 1-5μ on a semiconductor wafer with ²¹ atoms / cm ³
m, containing impurities concentration of 10 ¹⁴ to 10 ¹⁷ atoms / cm ³ of the semiconductor memory device that the claims paragraph 1, wherein the semiconductor epitaxial layer is formed. 4. The semiconductor memory device according to claim 1, wherein the second capacitor electrode contains impurities of the same conductivity type as that of the semiconductor substrate in the range of 10 ¹⁸ to 10 ²¹ atoms / cm ^3. .