JPH0666590B2 - Field effect transistor frequency multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a field effect transistor frequency multiplier circuit, an attenuator is inserted between the output side of a field effect transistor and a fundamental wave trap circuit, and the reflection coefficient of this transistor viewed from the gate side. Is set to be smaller than 1 so that the multiplication operation can be stably performed.

[Industrial application field]

The present invention relates to an improvement of a field effect transistor frequency multiplier circuit.

Generally, when a wave with high stability and high frequency is required, the output of an oscillator with low frequency but high stability is multiplied by a frequency multiplication circuit (hereinafter abbreviated as a multiplication circuit) to obtain a wave with a desired frequency. It has gained.

Conventionally, a microwave diode such as a variable capacitance diode or a step recovery diode was used as a multiplication circuit, but recently, a gallium arsenide field effect transistor (hereinafter abbreviated as FET) has been used instead of this. .

The advantages of using FETs are that they can be expected to have a multiplication gain, have good input / output isolation, and can be used in a wide band. However, they require stable operation as a multiplication circuit.

[Conventional technology]

 FIG. 5 shows a circuit diagram of a conventional example.

The operation of FIG. 5 will be described below by taking the double operation as an example.
In the figure, the fundamental wave of frequency fo (hereinafter abbreviated as fo) input from the terminal IN passes through the matching circuit 1 composed of the open stub 11 of the microstrip line and the source S.
It is added to the gate G of FET2 which is grounded. Since the gate bias voltage of FET2 is pinch off or near 0V,
An output wave containing a relatively large number of doubled (abbreviated as 2fo below) components can be taken out from the drain D, but the fo component of the output wave is totally reflected to the FET side by the fundamental wave trap circuit 3
Non-linear characteristic between drain D and source S of
The o component is extracted and the fo component output to the load is suppressed.

On the other hand, the 2fo component is efficiently taken out through the matching circuit 4 having a function of flattening the frequency characteristic of the 2fo band composed of the fundamental wave trap circuit 3, the open stub, etc., and brought to a predetermined level by the resistance attenuator 5. It is adjusted and output to the load.

The fundamental wave trap circuit 3 is composed of an open stub having a length of λg / 4 (λg represents a wavelength) so as to be totally reflected with respect to fo, and is placed before or after the matching circuit 4. The resistance attenuator 5 also has a role of alleviating the effect of impedance mismatch with the circuit connected to the next stage.

[Problems to be solved by the invention]

As described above, the fo component output from the drain of FET2 is totally reflected by the fundamental wave trap circuit 3, so when the stability factor K of the FET used is smaller than 1 with respect to the fo component, There is a problem that the reflection coefficient when viewed from the FET side becomes larger than 1 and the multiplier circuit may become unstable or oscillate. The stability coefficient K can be obtained from the S parameter described in the FET catalog. When K> 1, it does not oscillate even if any impedance is connected to the input / output side of the FET and it is stable. In the case of K <1, it is unstable when a specific impedance on the input / output side of the FET is connected.

[Means for solving problems]

According to the present invention, the above problem is caused by the function of receiving the output from the field effect transistor (2) for multiplying the fundamental frequency fo as the input wave and flattening the frequency characteristic in the desired multiplied wave band as shown in FIG. Matching circuit (4)
And a fundamental wave trap circuit (3) that totally reflects the fundamental frequency fo component to the field effect transistor side, an attenuator showing good impedance characteristics for the fundamental frequency fo component and its harmonic components is connected, The attenuation of the attenuator is solved by a field effect transistor frequency multiplier circuit, characterized in that the stability factor K of the field effect transistor is selected to be greater than 1 with respect to the fundamental frequency fo component.

[Action]

The present invention inserts an attenuator 5 between the fundamental wave trap circuit 3 and the FET 2 that exhibits an impedance characteristic effective for the fundamental frequency fo component and its harmonics, and returns the fo component reflected by the drain of the FET to the power source. Attenuated to prevent the multiplication circuit from becoming unstable.

That is, the fo component of the FET output wave is the fundamental wave trap circuit 3
It is totally reflected by and returns to the output side of FET2 again, but in this process it passes through the attenuator 5 twice, so by determining the attenuation amount so that the reflection coefficient when looking at the FET side from the gate becomes smaller than 1. , Instability of FET frequency multiplier and possibility of oscillation are improved.

It should be noted that this attenuator also has the functions of improving the impedance mismatch with the circuit connected to the next stage and adjusting the output level of the desired multiplied wave, as described above, so these must be satisfied. .

〔Example〕

FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a mounting diagram of FIG. In all the drawings, the same symbols indicate the same objects, and the DC supply circuit is omitted. The operation of the circuit shown in FIG. 2 will be described below by taking the double operation as an example as in the conventional example.

In the figure, the 2fo component output from the drain of the FET 2 is efficiently output to the load at a predetermined level by the matching circuit 4 and the attenuator (eg, resistance attenuator) 5.

That is, in the matching circuit 4, the frequency characteristic of the 2fo component is flattened, and the attenuator exhibits an impedance characteristic effective for the fundamental frequency fo component and its harmonics.

Here, the fundamental wave trap circuit 3 has λ for the 2fo component.
Since the open stub is g / 2, the impedance when the open stub is viewed from the point a becomes infinite and is not affected by this trap circuit.

However, the fo component is reflected back to the drain here,
Since there is the attenuator 5 in between, it is attenuated by twice the amount of attenuation in the round trip and returns to the drain. At this time, from the gate
If the reflection coefficient on the FET side is smaller than 1, the instability of this FET frequency multiplier and the possibility of oscillation are improved.

FIG. 3 shows the circuit of FIG. 2 constructed by a microstrip line on a dielectric substrate. Numbers with "" correspond to the parts without "" of FIG. Further, 6 is a DC blocking capacitor, 7 is a dielectric substrate, and 8 is a through hole.

FIG. 4 is a mounting view of another embodiment of the present invention, and FIG. 2 is a diagram in which the portion of the fundamental wave trap circuit 3 is replaced with a band pass filter 8'having a center frequency of 2fo. In this case as well, the fo component is reflected by the filter 8'and returned to the drain of the FET, so the same operation as above is performed, but harmonic components other than 2fo are removed here, so the output of the FET frequency multiplier circuit The ratio of the 2fo component to other unnecessary components in is extremely improved.

〔The invention's effect〕

As described in detail above, according to the present invention, there is an effect that the instability of the FET frequency multiplier circuit and the possibility of oscillation are improved.

[Brief description of drawings]

 FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a mounting diagram of FIG. 2, and FIG. 4 is a mounting diagram of another embodiment of the present invention. FIG. 5 shows a circuit diagram of a conventional example. In the figure, 2 is a field effect transistor, 3 is a fundamental wave trap circuit, 4 is a matching circuit, and 5 is an attenuator.

Claims (1)

[Claims] 1. A matching circuit (4) to which an output from a field effect transistor (2) for multiplying a fundamental frequency fo as an input wave is inputted and which has a function of flattening frequency characteristics of a desired multiplied wave band. , Attenuator that exhibits good impedance characteristics to the fundamental frequency fo component and its harmonic components is connected between the fundamental frequency trap component (3) that totally reflects the fundamental frequency fo component to the field effect transistor side, and attenuates A field effect transistor frequency multiplier circuit characterized in that the attenuation amount of the container is selected so that the stability coefficient K of the field effect transistor is larger than 1 with respect to the fundamental frequency fo component.