JPH0666649B2 - Hysteresis comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is a hysteresis comparator circuit, comprising:
And supplying a signal between the pair of input terminals using the second differential circuit and outputting the signal from between the pair of output terminals,
Prevents malfunction due to the effect of fluctuations in the ground level.

[Industrial application field]

The present invention relates to a hysteresis comparator circuit, and more particularly to a comparator circuit having a hysteresis characteristic.

Conventionally, a comparator having a hysteresis characteristic has been used for the purpose of preventing chattering. Thus, it is desired that even those having hysteresis characteristics are not affected by noise.

[Conventional technology]

FIG. 4 shows a circuit configuration diagram of an example of a conventional hysteresis comparator. In the figure, a reference voltage is supplied to the inverting input terminal of the operational amplifier 10, and the output of the operational amplifier 10 is fed back. Further, the signal from the signal source 12 is supplied to the non-inverting input terminal via the input terminal 11, and the signal obtained by comparing the signal with the reference voltage is output from the output terminal 13.

[Problems to be solved by the invention]

In the above-mentioned conventional circuit, a signal from the signal source 12 whose reference is the ground level is input to the input terminal 11, and the output signal of the output terminal 13 is output with the ground level as the reference.

Here, when the output signal rises to H level and falls to L level, the impedance of the ground changes,
In addition to this, the ground level fluctuates due to the mixing of external noise. Therefore, there is a problem that the noise source 14 is equivalently inserted between the signal source 12 and the ground, noise is superimposed on the signal, and the comparator malfunctions.

The present invention has been made in view of the above points, and an object of the present invention is to provide a hysteresis comparator in which there is no risk of malfunction due to fluctuations in the ground level.

[Means for solving problems]

The pair of first and second transistors (Q ₁ and Q ₂ ) receives signals coming between the pair of input terminals (20a, 20b), respectively, differentially amplifies the signals, and the second transistor side A first differential circuit for outputting between the first output terminal (22a) and the second output terminal (22b) on the side of the first transistor, and the first and second differential circuits of the first differential circuit. The pair of third and fourth transistors (Q ₄ , Q ₃ ) respectively receive the signal output between the two output terminals to perform switching, and the fourth transistor (Q ₃ ) obtained by this switching. The terminal (Vc ₃ ) that outputs the signal on the side is connected to the connection point of the series-connected resistors (R ₂ , R ₄ ) that supply power to the first output terminal (22a) of the first differential circuit. and the difference between the first terminal (Vc ₄₎ for outputting a signal of said third transistor (Q ₄₎ side obtained in switching Second series connected resistors for supplying power to the output terminal (22b) of the circuit (R _1,
A second differential circuit connected to the connection point of R ₃ ).

[Action]

In the present invention, reverse-phase positive phase of the second differential circuit for switching operation (Q _3, Q _4), reverse phase respectively of the signal first differential circuit (Q _1, Q _2), positive phase The signal is output between the pair of input terminals (20a, 20b) and the signal is output from the pair of output terminals (22a, 22b).

Therefore, the ground level of the fluctuation of the potential of the pair of input terminals be varied due to external noise or the like (20a, 20b) are in phase, it is removed by the first differential circuit (Q _1, Q _2).
Therefore, there is no risk of malfunction.

〔Example〕

FIG. 1 shows a circuit diagram of a first embodiment of a hysteresis comparator of the present invention.

In the figure, a signal comes in between the terminals 20a and 20b. Terminals 20a, 20b
Each of them is connected to the base of each of the transistors Q ₁ and Q ₂ which form the first differential circuit. The collector of the transistor Q ₁ is connected to the line of the power supply voltage V _CC through the resistors R ₃ and R _1, and the collector of the transistor Q ₂ is connected to the line of the power supply voltage V _CC through the resistors R ₄ and R _2. These emitters are commonly connected and connected to a constant current source 21 that flows a current I ₁ .

The collectors of the transistors Q ₁ and Q ₂ are connected to the terminals 22b and 22a, respectively, and are also connected to the bases of the transistors Q ₃ and Q ₄ that form the second differential circuit. The collector of the transistor Q ₃ is connected to the connection point between the resistors R ₂ and R ₄ , the collector of the transistor Q ₄ is connected to the connection point between the resistors R ₁ and R ₃ , and the emitters of the transistors Q ₃ and Q ₄ are connected. Are connected in common and are connected to a constant current source 23 that flows a current I ₂ . That is, the second differential circuit is supplied with the positive-phase and negative-phase signals output from the first differential circuit, and the positive-phase signal obtained by the second differential circuit is supplied to the first differential circuit. Is fed back to the output side of the opposite phase of
The negative phase signal is fed back to the positive phase output side of the first differential circuit.

Gain of the transistor Q _1, Q ₂ is sufficiently large with respect to the transistors Q _3, Q _4, the the transistor Q _3, Q ₄ performs a switching operation.

Here, when the terminal 20a, the voltage V _I between 20b of the positive collector current I ₄ of the transistor Q ₂ collector current I ₃ of the transistor Q ₁ is large is small, so that transistor Q _1, Q ₂ each of The collector potentials V _C1 and V _C2 become L level and H level, respectively, so that the transistor Q ₄ is turned on and the transistor Q ₃ is turned off. Therefore, a current (I ₃ + I ₂ ) flows through the resistor R _1, and the collector potentials V _C3 and V _C4 of the transistors Q ₃ and Q ₄ are V _C4 <V.
_{Due to} the relationship of _C3 , the voltage V ₀ between the terminals 22a and 22b is positive.

Even if the voltage V _I changes from positive to zero and the currents I ₃ and I ₄ become I ₃ = I ₄ , the current I ₂ continues to flow through the resistor R ₁ so that V _C1 <V _C2
And the voltage V ₀ remains positive while transistor Q ₄ remains conductive.

Further, when the voltage V _I becomes negative, the currents I ₃ and I ₄ become I ₃ <I ₄ .
Then, when the equation (1) described later is satisfied, the transistors Q ₃ , Q
₄ switches to turn on transistor Q ₃ and turn off transistor Q ₄ . Therefore, the current I ₂ flows through the resistor R ₂ ,
The voltage V ₀ suddenly switches from positive to negative. Voltage V at this point
_{I, that} is, the first threshold voltage V _TH1 is expressed by the equation (6) described later.

Next, when V _I changes from negative to positive, similarly to the above,
When the voltage V _I is zero, the voltage V ₀ remains negative and the voltage V _0
The voltage V ₀ becomes positive only when I exceeds a predetermined threshold voltage V _TH2 .

Analysis of the circuit shown in FIG. 1 shows that the transistor Q ₃ is cut off and the transistor Q ₄ is turned on (V ₀ > 0) to the voltage V ₀
Is inverted, that is, V ₀ = 0, and the following equation holds.

I ₃ (R ₁ + R ₃ ) + I ₂ R ₁ = I ₄ (R ₂ + R ₄ ) ... (1) Further, the following formula is always established.

I ₁ = I ₃ + I ₄ (2) Here, _assuming that the base-emitter voltages of the transistors Q ₁ and Q ₂ are V _BE1 and V _BE2 , the following equation is obtained.

V _BE1 = V _BE2 + V _I (3) Base-emitter voltage V _BE of the transistor is V _BE = V _T l _n (I _C / I _S ) (4) V _T = kT / q However, I _C is Collector current, I _S is saturation current, k is Boltzmann's constant, T is absolute temperature, q is charge, and V _T is a constant.

From the above equations (3) and (4), the following equation is established.

V _I = V _T l _n (I ₃ / I ₄ ) Here, if R ₁ = R ₂ = R ₃ = R _{4 then the} following formulas are obtained from the formulas (1) and (2).

I ₃ = (2I ₁ −I ₂ ) / 4 I ₄ = (2I ₁ −I ₂ ) / 4 (5) From equations (4) and (5) The voltage V _I that satisfies the equation (6) is the threshold voltage V _TH1 .

Similarly, the voltage V _I when the voltage V ₀ becomes V ₀ <0 to V ₀ = 0, that is, the threshold voltage V _TH2 is expressed by the following equation.

Therefore, the hysteresis width V _TH is expressed by the following equation.

Although R _{1 to} R ₄ have been described as being equal, when they are similarly calculated even when the values of R _{1 to} R ₄ are different, they are expressed as shown in equation (8).

Thus, the hysteresis characteristic of the circuit of FIG. 1 is represented as shown in FIG.

Thus, the signal comes between terminals 20a and 20b, and
It is output from between a and 22b, and neither input nor output is referenced to the ground level. Therefore, if the external noise fluctuates the level of the ground mixed, fluctuations in terminal 22a, 22b respectively of the potential for ground level are in phase, the differential circuit of transistors Q _1, Q ₂ is no affected There is no malfunction.

FIG. 3 shows a circuit diagram of a second embodiment of the circuit of the present invention.

The circuit composed of the transistors Q ₁ and Q _{2 in} FIG. ₁ is composed of a two-stage differential circuit of the transistors Q ₁ A and Q ₂ A and Q ₁ B and Q ₂ B in FIG. The bases of the transistors Q ₁ A and Q ₂ A are respectively connected to the terminals 20 a and 20 b similarly to the transistors Q ₁ and Q ₂ . Resistors R _3, R ₄ each is connected transistors Q ₁ A, the transistors Q _5, Q ₆ each based is connected to the collector of the s Q ₂ A husband, transistors Q _5, Q ₆ each emitter level shift element The constant current sources 30 and 31 are connected via E ₁ and E ₂ , respectively. The level shift amounts of the level shift elements E ₁ and E ₂ and the current values of the constant current sources 30 and 31 are the same. The collector potentials of the transistors Q ₅ and Q ₆ and the transistors Q ₁ A and Q ₂ A, which are level-shifted by the level shift elements E ₁ and E ₂ , are supplied to the bases of the transistors Q ₁ B and Q ₂ B, respectively.

The emitters of the transistors Q ₁ B and Q ₂ B are commonly connected to the constant current source 32, and the collectors of the transistors Q ₁ B and Q ₂ B are commonly connected to the level shift element E ₃ via resistors R ₅ and R ₆ having the same resistance value. The output signals of the differential circuits of the transistors Q ₁ A and Q ₂ A are further differentially amplified. This is to stabilize the circuit operation by sufficiently increasing the gain of the transistors Q ₃ and Q ₄ with respect to the second differential circuit. In order to match the levels of the differential circuits of the transistors Q ₁ A and Q ₂ A and the differential circuits of the transistors Q ₁ B and Q ₂ B, the transistors Q ₅ and Q ₆ and the level shift element E
_{1 to} E ₃ are provided.

The collectors of the transistors Q ₁ B and Q ₂ B are connected to the terminals 22 b and 22 a, respectively, and also to the bases of the transistors Q ₃ and Q ₄ .

Transistors Q ₁ A, Q ₂ A and Q ₁ B, Q ₂ B are transistors Q ₁ , Q ₂
Since the first differential circuit similar to the above is constructed, the circuit of FIG. 3 performs the same operation as the circuit of FIG. 1, and the description thereof will be omitted.

The terminals 22a and 22b may be connected to the non-inverting input terminal and the inverting input terminal of the differential amplifier to improve the output characteristics.

〔The invention's effect〕

As described above, according to the hysteresis comparator of the present invention, even if the ground level fluctuates due to external noise or the like, it is not affected at all and there is no possibility of causing a malfunction, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the circuit of the present invention, FIG. 2 is a diagram for explaining hysteresis characteristics, FIG. 3 is a circuit diagram of a second embodiment of the circuit of the present invention, and FIG. It is a circuit block diagram of an example of a circuit. In FIG., 20a, 20b, 22a, 22b are terminals, 21,23,30～32 constant current _{source, Q 1 ~Q 4, Q 1} A, Q 1 B, Q 2 A, Q 2 B is the transistor, R _{1 to} R ₅ are resistors, and E _{1 to} E ₃ are level shift elements.

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-52-12554 (JP, A) JP-A-54-128656 (JP, A) JP-A-56-42426 (JP, A) Actual publication 43- 15719 (JP, Y1)

Claims (1)

[Claims] 1. A pair of first and second transistors (Q ₁ , Q ₂ ) receives a signal coming between a pair of input terminals (20a, 20b), respectively, and differentially amplifies the signal, A first differential circuit for outputting between the first output terminal (22a) on the second transistor side and the second output terminal (22b) on the first transistor side; and performs switching by receiving respectively the signals output between said first and second output terminals in the pair of third and fourth transistors (Q _4, Q _3), obtained the fourth in the switching A resistor (R ₂ , R ₄ ) connected in series for supplying power to the terminal (Vc ₃ ) for outputting a signal on the transistor (Q ₃ ) side to the first output terminal (22a) of the first differential circuit. of and connected to the connection point, and outputs a signal of the third transistor (Q ₄₎ side obtained in the switching terminal (Vc ₄₎ Supplying power to the second output terminal of the differential circuit of said 1 (22b) in series connected resistors (R _1,
R ₃ ), and a second differential circuit connected to the connection point, and the pair of the first and second output terminals (22a, 22b) at the time of rising and falling of the signal output Input terminal (20
a, 20b) Hysteresis comparator characterized in that the threshold voltage for signals coming between them is made different.