JPH0666759B2 - Data failure detection circuit - Google Patents

Description

The present invention relates to a data failure detection circuit using parity information.

[Conventional technology]

FIG. 2 is a block diagram of a conventional example of a data failure detection circuit using this type of parity information.

In the parity generation circuit 21 (or 22, the same applies hereinafter), the n-bit (n ≧ 1) data line 11 (12) is pulled in, and the n-bit data is specified according to the odd parity rule designation from the parity rule designation information line 71 (72). , And outputs it to the parity information line 31 (32). Memory circuit 41 (42)
Data line 11 (12) and parity information line 31 (32) are pulled in to store data and parity information.
Output to 11 (12) and parity information line 31 (32). The parity check circuit 51 (52) checks whether the parity information from the memory circuit 41 (42) is an odd parity with respect to the data from the memory circuit 41 (42), and only if there is an error, the check result is obtained. The fault information is output to the output information line 61 (62). That is, when the memory circuit 41 (42) is normal, no fault information appears on the check result output information line 61 (62), and when the memory circuit 41 (42) becomes a fault such as a bit stack, the check result output information line is displayed. Since the failure information is output to 61 (62), the memory circuit 41 located between the parity generation circuit 21 (22) and the parity check circuit 51 (52).
This means checking the normality of (42).

Furthermore, it is necessary to check whether the parity generation circuit 21 (22) and the parity check circuit 51 (52) are operating normally. For this, the Parity rule designation information line
By changing the parity rule designation from 71 (72) from the normal odd parity rule to the even parity rule, the parity information on the parity information line 31 (32) becomes an even parity for n-bit data. Due to the odd parity check in the check circuit 51 (52), the failure information is output to the check result output information line 61 (62). The failure information when this even parity rule is specified is the parity generation circuit 21.
(22) and the parity check circuit 51 (52) indicate normality of operation, and conversely, if no failure information is output, there is a failure.

Parity check circuit 21 (22) to Parity check circuit 51
The section up to (52) is called the parity section, and in Figure 2 it is 2
It shows two parity sections.

[Problems to be solved by the invention]

The conventional data failure detection circuit using the parity information described above requires m parity rule specifying information lines and m check result output information lines when m (m ≧ 2) parity sections exist. Therefore, it is necessary to install a flip-flop for holding the parity rule designation information determined corresponding to each parity section in the preceding stage of each parity rule designation information line, and the check result output information line. In the subsequent stage, m answer circuits for the maintenance scan reading order by the online program are required.

The smallest maintenance unit that a device detects a fault and replaces with a maintenance item is typically a package. Due to the high integration technology of LSI, a plurality of circuits that realize a plurality of different functions are mounted in one package that is a physical maintenance unit, and therefore, a plurality of parity sections are included in one package. Therefore, the conventional data failure detection circuit requires frequent maintenance due to an increase in cost due to an increase in flip-flops that hold parity rule instruction information and an answer circuit for maintenance scanning, and an increase in failure display points. There is a drawback that

[Means for solving problems]

In the data failure detection circuit of the present invention, each parity rule specifying information line for sharing the parity rule specifying information is commonly connected, and the check result of m (m: 2 or more in the parity section) parity check circuits is obtained. When at least one of the output information indicates a fault, the first gate circuit which outputs a predetermined logical value signal, and the check result information of the m parity check circuits all indicate a fault. A second gate circuit that outputs a predetermined logical value signal and the parity rule designating information of the parity rule designating information line are used as input selection signals to select the output of the first gate circuit or the output of the second gate circuit, It is characterized by having a 2-1 selector for outputting as failure information.

That is, according to the present invention, since only one parity rule specifying information line and one check result output information line are required, the number of flip-flops holding the parity rule specifying information and the number of maintenance scanning answer circuits are each one.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data failure detection circuit according to the present invention. This embodiment is similar to the conventional example shown in FIG.
Parity generating circuit 21 to Parity check circuit 51 and Parity check circuit 22 to Parity check circuit
It shows two Parichii sections up to 52. In FIG. 1, the same parts as those of the conventional example shown in FIG. 2 are designated by the same reference numerals, and the duplicate description will be omitted.

The parity generation circuits 21 and 22 are commonly connected to a parity rule designation information line 70. The logical sum circuit 8a and the logical product circuit 8b take the logical sum and the logical product of the fault information of the check result output information lines 61 and 62 of the parity check circuits 51 and 52, respectively. 2-
The 1-selector 9 outputs the output of the logical sum circuit 8a when the information on the parity rule designating information line 70 specifies the odd parity rule, and outputs it to the output check result output information 60 of the logical product circuit 8b when the even parity rule is specified.

Next, the operation of this embodiment will be described.

(1) Normally, the instruction from the parity rule designation information line 70 is an odd parity rule, and the 2-1 selector 9 selects the OR circuit 8a. At this time, the memory circuit 41 or
When at least one of 42 has a fault, the output of the OR circuit 8a becomes logic 1, and fault information is output to the check result output information line 60 of the 2-1 selector 9.

(2) Next, in order to check the operation normality of the parity generation circuits 21 and 22 and the parity check circuits 51 and 52, the information from the parity rule designation information line 70 is changed to the even parity rule. As a result, the 2-1 selector 9 selects the AND circuit 8b. And check result output information line
Only when the fault information is output to both 61 and 62, the output of the logical product circuit 8b becomes the logical "1", and the parity generation circuits 21 and 22 and the parity generation circuits 21 and 22 are connected to the check result output information line 60 of the 2-1 selector 9. Fault information indicating that the normality of the check circuits 51 and 52 has been confirmed is output.

A NOR circuit may be used instead of the OR circuit 8a, and a NAND circuit may be used instead of the AND circuit 8b.

〔The invention's effect〕

As described above, according to the present invention, the parity rule designation information is shared by m parity generation circuits, and
Input the output of the gate circuit that takes the OR or NOR of the failure information of the m parity check circuits corresponding to the number of parity generation circuits to one, and the output of the gate circuit that ANDs or NANDs the failure information to the other. 2-1 connected as
By providing a selector and making the selection designation of this selector the same as the parity rule designation information, it is possible to reduce the hardware amount of the flip-flop that holds the parity rule designation information and the maintenance scan answer circuit, and to reduce the number of fault display points. This has the effect of simplifying maintenance.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a data failure detection circuit using parity information according to the present invention, and FIG. 2 is a block diagram of a conventional example of a data failure detection circuit using parity information. 11,12 …… Data line, 21,22 …… Parity generation circuit, 31,32 …… Parity information line, 41,42 …… Memory circuit, 51,52 …… Parity check circuit, 60,61,62… … Check result output information line, 70 …… Parity rule designation information line, 8a …… OR circuit, 8b …… AND circuit, 9 …… 2-1 selector.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Koji Kogure 3-9-11 Midoricho, Musashino-shi, Tokyo Inside Nippon Telegraph and Telephone Corporation Musashino Electro-Communications Research Laboratory (72) Inventor Kiyohiko Kuroda Ueda, Nakahara-ku, Kawasaki-shi, Kanagawa Address 1015 within Fujitsu Limited

Claims (1)

[Claims] 1. A parity generation circuit for generating parity information for n-bit (n ≧ 1) data, and a parity check circuit for pulling in the parity information and the n-bit data to check normality. In the data failure detection circuit having m (m ≧ 2) parity sections, in which a parity rule specifying information line for specifying the parity rule of the generated parity information is drawn in the parity generating circuit, the parity rule specifying information is stored. The respective parity rule specifying information lines are commonly connected for common use, and a predetermined logical value signal is output when at least one of the check result output information of the m parity check circuits indicates a failure. And a predetermined logic value signal when all the check result information of the m parity check circuits indicates that there is a failure. A second gate circuit for outputting and the parity rule designating information of the parity rule designating information line as an input selection signal, and the output of the first gate circuit or the output of the second gate circuit is selected as fault information. A data failure detection circuit comprising a 2-1 selector for outputting.