JPH0666766B2 - Frame aligner circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frame aligner circuit for performing frame alignment necessary for preprocessing such as a line editing function and a switching function in digital transmission.

[Conventional technology]

In recent years, digital transmission has been introduced into communication networks, and digital networks are being built. In various signal processing, functions such as line editing and switching are essential. The frame aligner circuit aligns the frame phase of the signal sent via the digital transmission line with the reference frame phase in the station building or equipment as a pre-processing of the switching function in the digital exchange / line concentrator. It is a thing.

The frame phase of the signal sent via the digital transmission path is independent, and the frame phase of the digital signal sent from each path to the receiving side is uncorrelated. Further, the frame phase of the signal that has passed through the digital transmission line changes with the passage of time due to the environment such as temperature and humidity on the transmission line and the operation fluctuation due to the power supply fluctuation in the device and the aging fluctuation of the element. It is an important role of the frame aligner circuit to absorb the fixed phase difference and the time fluctuation of the signals sent from the respective routes as described above, and to align the frame phases to interface with the switching circuit.

FIG. 3 and FIG. 4 show time charts for explaining the operation of the frame aligner circuit and the circuit used conventionally. In FIG. 3, 1 is a write counter that controls writing to the memory, 2 is a read counter that controls reading from the memory, and 3 is a comparison of the phases indicated by the phase information c and g of the write counter 1 and the read counter 2. Phase comparison circuit for slip control of memory
Is an address selection circuit for selecting the output signal b of the write counter 1 and the output signal f of the read counter 2 and supplying an address to the memory. Reference numerals 5 and 6 have a capacity of the delay insertion / removal bit number n of data when a slip occurs. A memory, 7 is an output selection circuit that alternately selects the output data of the memories 5 and 6, 8 is a data input terminal, and 9 is a data output terminal.

Next, the operation of the conventional circuit will be described with reference to FIGS. FIG. 4 shows a case where the read speed is faster than the write speed and slip occurs. Signals a to e shown in FIGS. 4 (a) to 4 (e) are signals on the writing side, and signals f to i shown in FIGS. 4 (f) to 4 (i) are signals on the reading side.

First, the writing side will be described. One frame of the input data a of FIG. 4 (a) supplied to the input terminal 8 is composed of n bits and is numbered from the first frame to the first frame, the second frame, ... . Fig. 4 (b)
The output signal b of the write counter 1 shown in FIG.
It operates in synchronism with, and has one cycle with n bits. The window signal c of FIG. 4 (c) showing the phase information of the write counter 1 is supplied to the phase comparison circuit 3. Output data d and e of the address selection circuit 4 shown in FIGS. 4 (d) and 4 (e) are data written in the memories 5 and 6, and as shown in FIG. 4 (e), data of the first frame. Is written in the memory 6, and the data of the second frame is written in the memory 5, as shown in FIG. In this way, the memory 5
And 6 are written.

Next, the read side will be described. The cycle of the output signal f of the read counter 2 shown in FIG. 4 (f) is n bits like the write counter 1, but the phase is completely independent of the write counter 1. The phase information g of the read counter 2 shown in FIG. 4 (g) is supplied to the phase comparison circuit 3.
Signal h in FIG. 4 (h) showing the selection mode of the output selection circuit 7.
Is a signal for alternately selecting the output data of the memories 5 and 6, and as shown in FIGS. 4 (g) and 4 (h), the phase information g
The output data of the memory 5 is selected immediately after the marker. The output data i appearing at the output terminal 9 is sequentially output as the first frame, the second frame, ....

Next, the operation at the time of slip will be described. FIG. 4 shows a case where the reading speed is faster than the writing speed, and at time t1, the marker g1 of the phase information g is very close to the marker c1 of the phase information c, just before the phase approach, that is, the overlapping. The phase comparison circuit 3 that has detected the duplication of the two markers c2 and g2 of the phase information c and g at the time t2 is controlled by the signal h so as to invert the selection mode of the output selection circuit 7 after the time t3. The output data of No. 5 is continuously selected twice. As a result, the slip control is performed by reading the fourth frame information twice consecutively, and the output data i returns to the normal state.
Since the position of the marker g3 of the phase information g is also controlled when the slip occurs, the marker of the phase information g after the time t3 is shifted by n bits.

[Problems to be solved by the invention]

The above-described conventional frame aligner circuit employs a method of alternately writing the input data a into the two memories 5 and 6, and requires two memories 5 and 6. Therefore, the number of bits of one frame in the frame structure is increased. However, if the amount of delay is increased and the amount of delay insertion / removal at the time of slip occurrence must be increased, there is a drawback that the memory capacity increases and the hardware scale increases.

[Means for solving problems]

In order to eliminate such a drawback, the present invention has a delay insertion / removal bit number n of data at the time of slip occurrence that is the same as the number of bits constituting one frame, and has a capacity twice as large as this bit number n. A memory, a write counter that operates to control writing to the memory by operating every 2n bits, and a read counter that controls reading from the memory that operates per every 2n bits to write The phase approach is detected by comparing the phases of the output signals of the counter and the read counter, and when the phase approach is detected, the phase of the read counter fluctuates by n bits according to the end of reading of the frame currently being read. Control the phase comparator circuit, and select the output signals of the write counter and read counter to supply the address to the memory. It is obtained as provided with less selection circuit.

[Action]

In the present invention, the write counter and the read counter operate so that one cycle has 2n bits, and when the phases of the output signals of the write counter and the read counter approach each other, the phase of the output signal of the read counter changes by n bits. .

〔Example〕

A first embodiment of a frame aligner circuit according to the present invention
Shown in the figure. In FIG. 1, reference numeral 10 is a memory having a capacity of 2n bits. In FIG. 1, the same or corresponding parts as those in FIG. 3 are designated by the same reference numerals. In this circuit, both the write counter 1 and the read counter 2 operate with 2n bits as one cycle, and the control signal j of the phase comparison circuit 3 is input to the same counter 2 to control the read counter 2. These points are different from the conventional circuit.

Next, the operation of this circuit will be described with reference to FIGS.
Similar to FIG. 4 showing the operation of the conventional circuit, FIG. 2 shows a case where the reading speed is faster than the writing speed. Fig. 2
Signals a to c shown in (a) to (c) are signals on the writing side,
Signals d to f shown in FIGS. 2 (d) to (f) are signals on the read side.

First, the writing side will be described. The input data a shown in FIG. 2 (a) is numbered from the first frame to the first frame, the second frame, ... As in the case of FIG. The output signal b of the write counter 1 shown in FIG. 2 (b) is 2n bits and has one cycle. The window signal c shown in FIG. 2 (c) is input to the phase comparison circuit 3 as in the case of FIG.

Next, the read side will be described. The output signal f of the read counter 2 shown in FIG.
It is a 2n-bit cycle similar to, but is completely independent of the write counter 1. Phase information g shown in FIG. 2 (e)
Is the same as the phase information g in FIG. 4 and is input to the phase comparison circuit 3. The data i shown in FIG. 2 (f) is output data appearing at the output terminal 9, and includes the first frame, the second frame,
... is output in order.

Next, the slip operation will be described with reference to FIGS. 1 and 2. The time t1 is the state immediately before the occurrence of the slip as in FIG. 4, and the marker g1 of the phase information g is very close to the marker c1 of the phase information c. Time t2
When the phase comparison circuit 3 detects the duplication of the marker c2 having the phase information c and the marker g2 having the phase information g, that is, the phase approach, the read counter 2 is forcibly set to "1" at time t3. The output signal f of No. 2 has a phase shifted by n bits from that before time t3. As a result, the fourth frame is continuously output twice, so that the slip control is executed and the output data i returns to the normal state. At this time, the marker g of the phase information g
The position of 3 is also slip controlled, and the marker of the phase information g after the time t3 is shifted by one frame.

Although the memory has a capacity of 2n bits, it is necessary to completely store one frame as a frame to be read out after the slip when performing slip control to the frame before or the frame next to the frame currently being written. In order to realize this, the minimum memory capacity is 2 frames, that is, 2n bits. Further, since the memory capacity is set to 2n bits for the slip bit amount of n bits, the output signal control of the read counter at the time of slip control can be realized by setting a predetermined value or inverting control of only the highest address,
Even a circuit for slip control can be realized with small-scale hardware.

In the frame aligner circuit, when synchronous multiplexing is applied to a higher-order group in the future and a frame structure having a large number of bits in one frame is adopted, it is necessary to inevitably increase the delay insertion / removal amount during slip control. Even in such a case, this circuit does not need to use the two memories in parallel, so that it is possible to prevent an increase in the scale of hardware.

〔The invention's effect〕

As described above, according to the present invention, the capacity of the memory is set to 2n bits, the operation cycle of the write counter and the read counter is set to 2n bits, and the phases of the output signals of the write counter and the read counter are compared to detect the approach of the phases. However, since the phase of the output signal of the read counter is changed by n bits when the phases are close to each other, even if a frame configuration having a large number of bits in one frame is adopted, the delay at the slip control is caused by only one surface of the memory. Since the amount of insertion / removal can be increased, there is an effect that the hardware becomes smaller than the conventional circuit, and the order of the frames to be sent is secured, which facilitates various processing operations in the subsequent stages. In addition, slip control is performed while maintaining the frame phase, so loss of information is suppressed, and the multiplexing level in the subsequent stage is reduced. It can hold the kick frame phase to become.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a frame aligner circuit according to the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a system diagram showing a conventional frame aligner circuit, and FIG. The figure is a time chart for explaining the operation. 1 ... write counter, 2 ... read counter, 3
...... Phase comparison circuit, 4 ... Address selection circuit, 8 ... Input terminal, 9 ... Output terminal, 10 ... Memory.

Claims (1)

[Claims] 1. A memory in which the number of delay insertion / removal bits n of data when a slip occurs is the same as the number of bits constituting one frame, and has a capacity which is twice the number n of bits.
A write counter that operates so as to be 1 cycle for 2n bits and controls writing to the memory, a read counter that operates so as to be 1 cycle for 2n bits and controls reading from the memory, and the write The phase approach is detected by comparing the phases of the output signals of the counter and the read counter, and when the phase approach is detected, the phase of the read counter fluctuates by n bits according to the end of reading of the frame currently being read. A frame aligner circuit, comprising: a phase comparison circuit that controls so as to control the output of the write counter and a read counter; and an address selection circuit that supplies an address to the memory.