JPH0667017B2 - Circuit switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a circuit switching system, in particular, a circuit switching for exchanging time slots in units of 64 kb / s (kilobits per second) and circuit switching in units of lines in digital switching. Regarding the scheme.

[Prior Art] In the conventional digital exchange, line-by-line circuit exchange is performed by a space division switch, and a signal having a bit rate of 64 kb / s, which is an exchange unit in one frame, is octet-multiplexed into a plurality of signals. It was not possible to do so in a circuit switching system that swaps time slots in units of 64 kb / s. This is because the first synchronous system input signal to the circuit switching system that performs time slot replacement in units of 64 kb / s and the second synchronous system input signal to the line circuit switching system (space division switch) are data. This is because the same processing cannot be performed because the configurations are different (the former has a frame configuration while the latter does not have a frame configuration).

[Problems to be Solved by the Invention] In the above-described conventional circuit switching system, when the circuit switching in units of 64 kb / s and the circuit switching in units of lines coexist, it is necessary to have both a time switch and a space switch. However, there is a problem that the scale of hardware becomes large and control becomes complicated.

An object of the present invention is to solve such a problem of the conventional one, and in the case where the circuit switching in a predetermined bit rate unit and the line unit switching coexist, a circuit switching in which a space switch and a switching control conventionally required are deleted. To provide a method.

[Means for Solving Problems] According to the present invention, each frame has a frame structure,
A frame synchronization pattern is inserted, and a plurality of first synchronization system input signals in which signals of a predetermined bit rate are N-multiplexed are respectively received on a plurality of lines, and frame synchronization of the plurality of first synchronization system input signals is performed. Is established by detecting the frame synchronization pattern, and the N-multiplexed signal of a predetermined bit rate is multiplexed with the in-apparatus frame in a state where the frame synchronization pattern is removed,
In a circuit switching system for exchanging time slots of the predetermined bit rate by a time-division switch, a second synchronous system input to each of the plurality of lines, which is data to be circuit-switched without taking the frame structure. When a signal is input, these second synchronous system input signals are divided into N units, multiplexed into the in-apparatus frame, and exchanged in line units by the time slot exchange operation in the predetermined bit rate unit by the time division switch. A circuit switching system characterized by performing

Further, according to one aspect of the invention, a frame configuration is provided,
A frame synchronization pattern is inserted in each frame, and a plurality of first synchronization system input signals in which 64 kb / s signals are octet-multiplexed are respectively received on a plurality of lines, and the plurality of first synchronization system input signals are received. In the state where the frame synchronization of is established by detecting the frame synchronization pattern, and the frame synchronization pattern is removed,
In a circuit switching system that multiplexes an octet-multiplexed signal of 64 kb / s into an internal frame and replaces time slots in units of 64 kb / s with a time division switch,
When a second synchronous system input signal, which is all data (full data) to be circuit-switched without the frame structure, is input to each of the plurality of lines, the second synchronous system input signal is octeted. When the full data is divided into units and cannot be divided without corresponding to a multiple of the frame period, a surplus bit is added to multiplex the frame in the device,
The time-division switch switches the time slots in units of 64 kb / s to perform line-by-line replacement (first
Circuit division according to the multiplexing rule of the synchronous input signal of
A circuit switching system characterized by the above is obtained.

EXAMPLES Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The data input is a synchronous bipolar signal (first synchronous input signal) from the transmission line. If the signal received from the transmission line is a bipolar signal (three-valued signal), it needs to be converted into a unipolar signal. Therefore, this data is converted into a unipolar signal by the bipolar / unipolar exchange circuit 1, and the tank circuit (from the data to the clock To extract the clock from the data. 64 kb / s in synchronization with this clock
For data to be exchanged on a line basis, the frame synchronization circuit 3 establishes frame synchronization, controls writing of data to the elastic store 6 via the selector 5, and based on the read control signal 7, the elastic store is executed. 6
The read control is performed to multiplex the frame in the device. The elastic store 6 is a 2-port memory that performs sequential write and sequential read. The time-division switch 8 replaces this data with time slots and lines in units of 64 kb / s.

When the full data is input (in the case of the second synchronous input signal), the free-run counter 4 divides the frame into octet units without being aware of the frame, and the data is sent to the elastic store 6 via the selector 5. Write control is performed and multiplexing is performed on the frame in the device. By only exchanging this data in lines of 64 kb / s by the time division switch 8, the same operation as the line exchange in lines of the space switch is realized.

The second synchronous system input signal extracts a clock signal in the tank circuit 2, and the free-run counter 4 for counting the same period as the frame period of the first synchronous system input signal forcibly creates the frame head position, By inputting it to the elastic store 6, the subsequent processing becomes the same as the processing of the second synchronous system input signal.

The selector 5 selects the output of the frame synchronization circuit 3 in the case of processing the first synchronous system input signal, and selects the output of the free-run counter 4 in the case of processing the second synchronous system input signal.

Since a plurality of 64 kb / s signals are multiplexed on one line, it is clear that quantitatively 1 line unit> 64 kb / s.

The data exchanged with the circuit is again stored in Elastic Store 9
Then, under the control of the frame pulse generator 10 that generates a frame synchronization pulse (pattern) indicating the beginning position of the frame, the frame is multiplexed into the transmission path frame,
It is converted into a bipolar signal and output to the transmission line.

[Effects of the Invention] As described above, according to the present invention, the circuit switching system of a predetermined b / s unit can also coexist with the circuit switching of each line, so that the space conventionally required when both circuit switching systems coexist. This has the effect of reducing switches and switching control.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 1 ... Bipolar / unipolar conversion circuit, 2 ... Tank circuit, 3 ... Frame synchronization circuit, 4 ... Free run counter, 5 ... Selector, 6 ... Elastic store, 7 ... Read control signal, 8 ...... Time division switch,
9 ... Elastic store, 10 ... Frame pulse generator, 11 ... Bipolar / unipolar conversion circuit

Claims (1)

[Claims] 1. A frame synchronization structure, wherein a frame synchronization pattern is inserted in each frame, and a plurality of first synchronization system input signals in which signals of a predetermined bit rate are N-multiplexed are respectively received in a plurality of lines. , The frame synchronization of the plurality of first synchronization system input signals is established by detecting the frame synchronization pattern, and the N-multiplexed signal of a predetermined bit rate in the state where the frame synchronization pattern is removed. In a circuit switching system that multiplexes a plurality of lines into a device frame and replaces time slots in units of a predetermined bit rate by a time division switch, all of the plurality of lines should be circuit switched without the frame structure. When the second synchronous input signal which is data is input, these second synchronous input signals are divided into N units and Multiplexes the frame, the line exchange system and performs interchanging time slots replacement operation by the line units of the time division switch according to the predetermined bit rate units.