JPH0667250B2 - Phase control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit, and more particularly to a novel phase control circuit that shortens the pull-in time of a phase control system.

2. Description of the Related Art There are a wide range of applications for controlling the speed and phase of a controlled object to constant values, but here, a two-head helical scan type magnetic recording / reproducing device (hereinafter referred to as VTR) will be described as an example. .

In VTR, in order to make the recording wavelength of the video signal recorded on the magnetic tape a feasible value, it is necessary to rotate the rotating cylinder containing the video head at high speed. The rotation speed of the rotary cylinder is controlled by the speed control circuit to be a substantially constant rotation speed, and the rotation phase is controlled so that the phase difference from the reference phase signal becomes a constant value.

FIG. 15 shows a part of the speed and phase control circuit in the conventional VTR. In the figure, a terminal 1501 inputs a signal from a frequency generator (FG) that generates a signal having a frequency proportional to the rotation speed of the rotating cylinder. The period of the FG signal is measured by the speed error signal generation circuit 1502,
The amount of difference between the signal period and the reference period is output as a speed error signal. The circuits 1503 and 1508 are pulse width modulation circuits (PWM circuits), and are a kind of D / A converter that outputs a signal having a pulse width according to the input digital signal value. Therefore, the speed error signal is output to the terminal 1504 as a PWM signal.

The reference signal is input to the terminal 1505, and the head switching signal (H.SW) is input to the terminal 1506. Here, the reference signal is
When a video signal is recorded, it is a signal obtained by separating and extracting the vertical synchronizing signal contained in the video signal, and is a 60 Hz pulse signal in an NTSC VTR. The H.SW signal is a signal that indicates the rotation phase of the rotating cylinder.
In the VTR of the method, it is a square wave signal of 30Hz. Reference signal is 1
The phase difference between the signal divided by ½ and the H.SW signal is taken out by the phase error signal creating circuit 1507, and the taken out phase error signal is D / A converted by the PWM circuit 1508 and is output to the terminal 1509. Is output.

The PWM signals output to the terminals 1504 and 1509 are smoothed by the resistor R ₁ and the capacitors C ₁ and R ₂ and C ₂ , respectively, and converted into analog signals. The velocity error signal and the phase error signal are combined by the resistor R ₃ . Depending on the value of resistor R ₃ ,
The ratio (mix ratio) of combining the phase error signal with the speed error signal changes. This mix ratio is usually selected from a fraction to a few tens in order to secure the stability of the phase control system. The combined value of the speed and phase error signals obtained at the terminal 1510 is supplied to the drive circuit of the motor that drives the rotating cylinder, and controls the rotating speed and the rotating phase of the rotating cylinder.

FIG. 16 shows a more detailed block diagram of a conventional phase comparison circuit, and FIG. 14 shows the waveforms of the respective parts of FIG. In both figures, the same symbols indicate the same signals. The reference signal (vertical synchronization signal) (14a) input from the terminal 1601 is frequency-divided by the 1/2 frequency dividing circuit 1602 and becomes a signal (14b). The circuit 1603 is a preset circuit, and sets a predetermined preset value in the counter circuit 1604 at the timing of the rising edge of the signal (14b).

The counter circuit 1604 starts counting from a preset value, and when the counter overflows, starts counting again from the preset value. Therefore, the output value of the counter circuit 1604 repeats the change shown in FIG. 14 (14c). By changing the preset value, Fig. 14
Since the cycle indicated by 01 can be changed, the stable position of the phase of the controlled signal can be adjusted by changing the preset value.

The circuits 1607 and 1608 are circuits that apparently limit the upper limit value and the lower limit value of the output value of the counter circuit 1604, and the upper limit value limiting circuit 1607 starts counting the counter output (14c) from the rising edge of the signal (14b). The number of overflows is counted, and when this number is equal to or greater than a certain value, the value of the latch circuit 1605 is held at the maximum value indicated by 1402. The lower limit limiting circuit 1608 holds the value of the latch circuit 1605 at the minimum value indicated by 1403 when the number of overflows is equal to or less than a certain value. Therefore, the counter output (14c) supplied to the latch circuit 1605 is the same as that supplied with the counter output indicated by the signal (14d). The H.SW signal (14e) is input from the terminal 1606, and the value of the counter output (14d) is latched at the timing of the falling edge of this signal. The output 1609 of the atch circuit 1605 is shown in FIG.
It is supplied to the PWM circuit 1508 and output as a phase error signal.

Problems to be Solved by the Invention In the phase comparison circuit in such a conventional circuit configuration,
There is a problem that the phase pull-in time at the transition time is limited by the power supply voltage and the mix ratio. This is because the lower limit value of the phase error signal output from the terminal 1509 in FIG. 15 is the ground potential, and the upper limit value is the power supply voltage value. The level of the difference between the upper limit value and the lower limit value corresponds to the range in which the rotation speed is modulated. The larger the modulation range, the larger the amount of change in the rotation speed, and the larger the speed at which the phase changes. That is, the time from the position where the phase is deviated to the stable point is shortened. However, the modulation range is limited by the power supply voltage and further limited by the mix ratio.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a novel phase comparison circuit that is not limited by the mix ratio and that can shorten the phase acquisition time.

Means for Solving the Problems In order to solve the above problems, the present invention has a modulation means for modulating the rotation speed, and the modulation means has a constant phase difference between the phase reference signal and the controlled signal. When it is within the phase error range, the amount of the phase error signal is configured to change in proportion to the phase difference, and when the phase difference is outside the constant phase range, the phase comparison timing of the controlled signal at the present time. Time tn between the phase comparison timing of tp and the next controlled signal
In the period with, than the rotation speed at the time of tp,
A period for driving at the accelerated or decelerated rotation speed and a period for maintaining the steady rotation speed are provided, and tp to tn
The acceleration or deceleration level is set so that the amount of change in the rotational phase during the period up to (1) corresponds to one cycle of the rotational phase of the controlled signal during steady rotation.

Action The present invention has the above-mentioned configuration to set the generation position of the next controlled signal to the stable position of the phase control system, and set the rotation speed at the generation position of the next controlled signal to the rotation speed in the steady state. As a result, the pull-in time of the phase control system can be performed in one cycle of the pull control signal, so that the phase pull-in time at the time of transition can be shortened.

Example Before describing a specific example of the present invention, the relationship between the configuration of the phase comparison circuit and the phase pull-in time will be described first. FIG. 13 is a diagram showing the relationship between two types of phase error signal amounts and controlled signals. In the figure, the signal (13a)
Shows the change in the amount of phase error signal with respect to the amount of phase shift from the reference signal, and the signal (13b) shows the controlled signal. The horizontal axis is time, and the signal (13a) is synchronized with the rotation phase of the reference signal. For example, when the rotational phase of the controlled signal is at the position indicated by t ₅₀ , the amount of the phase error signal is indicated by 1301, and when the rotational phase of the controlled signal is indicated by t ₅₁ , the amount of the phase error signal is indicated by 130.
The amount is 2. It is assumed that the phase control system is stable when the phase error signal has an amount indicated by 1301.

When the power is turned on, the number of rotations of the motor is gradually accelerated from the stopped state, the speed control circuit controls the rotation speed to a substantially constant speed, and the phase control circuit keeps the rotation phase and the reference signal constant. Controlled by. Now, when the rotation speed of the motor reaches a predetermined speed, it is assumed that the reference signal and the rotation phase of the rotating cylinder have a relationship of t ₅₁ shown in FIGS. 13 (a) and 13 (b). At this time, assuming that the rotation speed of the rotating cylinder exactly matches the target rotation speed, the pulse signal 1303 indicating the rotation phase is displayed.
Occurs at a position indicated by 1304 after a fixed time (time corresponding to one cycle). That is, the relative positional relationship between the signal (13a) synchronized with the phase of the reference signal and the pulse signals 1303 and 1304 does not change. However, in reality, the rotation speed is accelerated by the phase error amount 1302 obtained at time t ₅₁ , and a pulse signal is generated at the position indicated by 1305 after a certain period of time. By repeating such operation, the pulse generation position of the controlled signal (13b) is changed to the signal (13b).
Center of the inclined part of a) (position corresponding to the position indicated by 1301)
It will stabilize after moving up to. The value of the phase correction amount 1306 that moves after a fixed time is the phase error signal amount.
Determined by the amount of change in rotational speed that can be changed by 1302.

The signal shown in FIG. 13 (13c) is the signal shown in (13a) except for the portion other than the portion where the amount of the phase error signal proportionally changes according to the phase difference shown in 1307 (hereinafter referred to as the proportional inclination portion). It shows the amount of phase error when the level is larger or smaller than the level. Such a level can be freely selected when using a method of handling the velocity and phase error signals by numerical values and mixing as will be described later, as long as the numerical values that can be handled do not overflow. Signal (13
d) shows the controlled signal. The stable point of the phase control system is 1308
And 1309 is when the pulse signal of the controlled signal is located at the center position of the inclined portion. Similarly to the previous time, the position of the pulse signal when the motor rotation speed becomes equal to the target rotation speed is the position indicated by t ₅₂ . At this time, if the motor rotation speed is exactly equal to the target rotation speed, the pulse generation position after a certain time is t ₅₄
It becomes the position shown by. Actually, the rotation speed is accelerated by the amount 1310 of the phase error signal obtained at the position of t ₅₂ , and the generation position of the pulse signal after a certain time becomes the position shown by t ₅₃ . At this time, the phase correction amount that moves after a certain time is the amount indicated by 1311. The phase correction amount 1311 is (13
It becomes larger than the phase correction amount 1306 shown in b). This is 1
This is because the phase error amount indicated by 310 is larger than the phase error amount indicated by 1302, and the rotation speed can be increased accordingly. If the amount of phase correction is large, the time required to reach the stable point is shortened and the pull-in time can be shortened.

In order to minimize the pull-in time of the phase control system, use the phase error signal at that time so that the pulse generation position of the next controlled signal will occur at the stable point and that overrun will not occur. do it. For example, taking the pull-in from the position of t ₅₂ shown in (13d) as an example, the next pulse generation position is the stable point of the proportional inclination part, that is, the position indicated by 1309, and if overrun is not performed. It will be good.

According to the present invention, when the pulse generation position of the controlled signal when the rotation speed is substantially constant is at a position other than the proportional inclination part, the next pulse generation position is at the substantially center (stable point) of the proportional inclination part. The present invention provides a method of modulating the rotational speed that is positioned and does not cause overrun. When the first pulse generation position of the controlled signal is on the proportional slope,
It suffices to perform the pull-in by the response of the normal phase control system.
The pull-in time at this time is not long enough to be a problem.

Next, it will be described that changing the phase error amount is equivalent to changing the speed reference value.

FIG. 11 is a block diagram showing a part of the speed and phase control system, and FIG. 12 is an equivalent conversion of FIG.

In FIG. 11, ωi is a reference value of the rotation speed, and is specifically given as a numerical value. ωo is a value indicating the actual rotation speed of the rotating body, and specifically, is a numerical value indicating the period of the FG signal. ωi and ωo are input with mutually opposite polarities, and the value of the difference between the two velocities is extracted at the addition point 1105. A block 1101 is a block indicating the speed comparison sensitivity, and the speed difference signal is multiplied by the speed difference value to obtain a speed error signal 1108.

θi is a phase reference value, and θo is a value indicating the rotational phase of the rotating body. The phase difference signal 1109 is obtained by multiplying the value of the difference between the two phases extracted at the addition point 1106 by the value of the phase comparison sensitivity indicated by 1102. Even if the phase difference with the reference signal is the same, different phase error signals can be obtained by changing the value of the phase comparison sensitivity. That is, different values such as 1302 and 1310 shown in FIG. 13 can be set.

The velocity error signal and the phase error signal are combined at the addition point 1107, filtered by the filter block 1103, and output to the terminal 1104. Terminal not shown
The signal output to 1104 is D / A converted and then sent to the drive circuit of the rotating body to control the rotation speed and rotation phase of the rotating body.

FIG. 12 is a block diagram equivalently converted from FIG. 11, and is a diagram converted into a form in which the phase error signal is added to the reference value of the rotation speed. In both figures, the same symbols represent the same elements. Such equivalent transformation is well known in control theory. Although detailed description is omitted, when changing the addition point of the phase error signal 1109 shown in FIG. 11 from 1107 to 1105, the value of the reciprocal of the transfer function of the block located between both addition points is The error signal should be multiplied.
A block 1204 shown in FIG. 12 is a transfer function having a reciprocal value of the speed comparison sensitivity.

In FIG. 12, the reference value ωi of the rotation speed and the phase error signal 1205
The actual rotation speed ωo is subtracted from the value obtained by adding and. That is, the output signal 1206 of block 1201
Can be considered as the reference value ωi of the rotation speed shown in FIG. From this, it can be said that changing the value of the phase error signal is equivalent to changing the reference value of the rotation speed.

Next, a method of modulating the rotation speed according to the present invention will be described.

FIG. 2 is a diagram for explaining how a change in rotation speed affects a rotation phase. In the figure, (2
a) shows a signal which is phase-synchronized with the reference signal. (2b1),
(2b2) and (2b3) are diagrams respectively showing the rotation phase, rotation speed, and rotation position of the rotating body under the same condition.
(2c1), (2c2), and (2c3) are diagrams showing the rotation phase, rotation speed, and rotation position of the rotating body under other identical conditions. The time is shown in (2d).

The pulse signal shown in (2b1) is a signal indicating the rotation phase of the rotating body. For example, the pulse signal is generated once for each rotation of the rotating body, and its period is T. When the rotation speed is the speed ωo substantially equal to the reference speed, the position where the pulse signal is generated is the position indicated by t ₂₀ , that is, the stable position of the phase control system. At this time, the next pulse generation position is time t ₂₃ , and the position is also stable. The change in rotational position can be obtained by integrating the rotational speed. If the rotation speed is constant at ωo, the change in rotation position is 2 in (2b3).
Make certain changes as indicated by 03. This change in rotational position θh ₁ at an arbitrary time can be expressed by the following equation, where t is a variable of time.

θh ₁ = ωo · t (1) If the rotational position at time t ₂₀ is set to zero, the rotational position 204 at time t ₂₃ should be obtained by substituting one period T for the time t in equation (1). You can Then, if the amount of θh ₁ at this time matches one rotation amount of the rotating body, the pulse signal indicating the rotation phase can always maintain a constant phase relationship with the reference signal.

Next, it is assumed that the pulse generation position when the rotation speed reaches the substantially constant speed ωo is time t ₂₁ as shown in (2c1). Then, consider a change in the rotational position when the rotational speed is changed to ω ₁ at time t ₂₁ and is changed to ω ₀ again at time t ₂₂ . The change in rotational position at this time is shown in (2c3). That is, ω ₀ until time t ₂₁
Shows the change 205 of the rotational position corresponding to the period from time t ₂₁ to t ₂₂ represents the change in the rotational position corresponding to omega _1, the time t ₂₃
After that, the change in the rotational position according to ω ₀ is shown again. Time t
_When the rotational position at ₁₂ is zero, the change amount θh ₂ (indicated by 208) of the rotational position at time t ₂₃ can be expressed by the following equation.

θh ₂ = ω ₁ · (t ₂₂ −t ₂₁ ) + ω ₀ · (t ₂₃ −t ₂₂ ) ... (2) The value of θh ₁ shown in the equation (1) when T is T and (2) When θh ₂ shown in the equation is equal, the next pulse signal shown in (2c1) is generated at the position of time t ₂₃ . This is because the amount of change in rotational position from the pulse signals 209 to 210 shown in (2b1) and the pulse signals 211 to 21 shown in (2c1).
This is because the change amount of the rotational position up to 2 is an amount that corresponds to one rotation of the rotating body and is the same.

From the above, by combining equations (1) and (2) with θh ₁ (t = T) = θh ₂ , equation (3) can be obtained.

Expression (3) is an expression that gives how much the value of ω ₁ should be. For example, the initial pulse signal generation time t
_{If 21} is T / 2, (t ₂₂ −t ₂₁ ) = (t ₂₃ −t ₂₂ ) =
If T / 4, then ω ₁ = 3 · ω ₀ . That is, at this time, the value of ω ₁ should be set to 3 times the value of the reference speed ω ₀ .

The rotation speed at time t ₂₃ is ω ₀ . Therefore, time t ₂₃
Subsequent changes in rotational position will be the same as those shown in (2b3). This pulse generation position after the time t ₂₃ is always indicates that a stable position of the phase control system. That is, no overrun will occur.

As is clear from the above, if the rotation speed is changed as shown in (2c2) according to the pulse signal generation position when the rotation speed becomes substantially constant, the pulse generation position after one cycle Will always be in the stable position of the phase control system and will not overrun.

In FIG. 2, it has been described that the change in the rotation speed occurs instantaneously. However, the change in the actual rotation speed responds with a time delay. The effect of this time delay will be described below.

FIG. 3 is a diagram showing various response waveforms having a time delay. In FIG. 3 (a), a pulse signal indicating the rotation phase is shown. The solid line in FIG. (3b) shows the same change as the rotation speed shown in (2c2). The actual change of the rotation speed has a time delay and has a response shown by a broken line 301. The influence of the time delay at this time appears in the area indicated by the diagonal lines 302 and 303. If the response of the control system is equal during acceleration and during deceleration, the areas of 302 and 303 are equal. Therefore, it can be said that the amount of change in the rotational position until the next pulse signal is generated is the same whether a response with a time delay or an instantaneous response. That is, in this case, it is not necessary to consider the response with a time delay.

FIG. (3c) is an example when the time for changing the rotation speed is lengthened. Also at this time, since the rotation speed has finished changing from ω ₂ to ω ₀ by the time when the next pulse signal is generated, it is not necessary to consider the influence at the transition time as described in FIG. 3B. Further, the value of ω ₂ may be calculated by the above formula (3).

FIG. 3D shows an example when the response of the speed control system is slow and the integral filter is incorporated. The change in the rotation speed at this time shows a substantially linear change as indicated by the broken line. Then, the time for setting the rotation speed command to ω ₃ is the time difference between the time t ₃₁ and the time t _{32 at} which the pulse signal is generated.
If set to half of T ₁ , the rotation speed will be ω at time t ₃₂ .
_Since it becomes ₀ , no overrun is performed. Further, since the amount of change in the rotational position corresponds to the area indicated by the diagonal line 304, the value of this area may be set to be equal to the amount of change in the rotational position for one rotation.

Figure (3e) shows the time difference of the rotation speed
This is an example when the length is shorter than half of T1. At this time as well, overrun is not performed, and a large value of ω ₄ may be selected so that the value of the area 305 becomes equal to the change amount of the rotation position of one rotation.

In Fig. (3f), the time for changing the rotation speed is
This is an example when it is made longer than half of T ₁ . At this time,
Since the rotation speed does not return to ω ₀ at time t ₃₂ , the next pulse signal does not occur at the stable position of the phase control system. That is, an overrun will occur.

As is apparent from the above description, when the rotation speed is changed to ω ₀ after the rotation speed is changed, the change in the actual rotation speed should be converged by the time when the next pulse signal is generated. The rotation phase can be set to a stable state after the time of one rotation, and overrun can be prevented. If the time for changing the rotation speed is set to half the time difference T1 or less than half, the overrun can be prevented regardless of the response time of the speed control system. Also,
When the response time of the speed system is fast, the value for changing the rotation speed may be calculated by the equation (3). On the contrary, when the response time of the speed system is slow, the details are omitted, but an expression integrating the speed change may be obtained, and an expression corresponding to the equation (3) may be obtained by the same method as described above. Further, in a control system having a transient phenomenon that cannot be obtained by a simple calculation formula, the optimum amount of change in rotational speed may be obtained by experiment. In any case, the rotation speed should be modulated according to the amount of the rotation phase difference at a certain time so that it will converge to the steady-state rotation speed and the overrun will not occur until the next pulse signal is generated. Is possible.

Next, specific examples of the present invention will be described.

FIG. 4 is a diagram showing an embodiment of the present invention, which is composed of a microcomputer (hereinafter simply referred to as a microcomputer) section and other hardware circuits. FIG. 1 is a diagram for supplementing the waveforms and explanations of the respective parts of FIG. 4, and the same symbols in both figures indicate the same signals.

In FIG. 4, an FG signal is input to the terminal 401, a reference signal (vertical synchronization signal in this example) is input to the terminal 402, and H.SW is input to the terminal 403.
Each signal is input. The circuits 404, 405, and 406 are input capture registers (hereinafter simply referred to as ICR). Each ICR circuit uses the counter circuit at the time of the rising or falling edge of each signal of terminals 401 to 403.
A latch circuit that latches the count value of 407. The counter circuit 407 is a free counter that counts the clock 408. When the counter overflows, it starts counting again from the minimum value. The count value changes as shown in Fig. 1 (1d). In Fig. 1, H.SW
Count value 101 at the falling edge of the signal (1b)
Are latched in the circuit 406 shown by ICR3 in FIG. Further, the count value 102 at the rising edge of the signal (1c) having a half cycle of the reference signal is latched in the circuit 405 indicated by ICR2. Therefore, if the count value indicated by 102 is subtracted from the count value indicated by 101 and the constant phase reference value indicated by 103 is further subtracted, the amount indicated by the difference 104 indicates the time corresponding to the phase shift amount. . A circuit 409 shown in FIG. 4 is a timer circuit, which is reset at the falling edge of the H.SW signal and thereafter generates a pulse signal (1a) at regular time intervals. As shown in FIG. 1, in this example, the H.SW signal period is 1 /
It is assumed that the timer time is set so that a pulse signal is generated every 12 times. Ir shown in FIG.
Each signal of q1, irq2, irq3 is a pulse signal generated when each ICR circuit latches the value of the counter circuit,
It is used as an interrupt signal to the microcomputer. The output signal irq4 of the timer circuit 409 is similarly used as an interrupt signal. The circuit 410 is a microcomputer and includes a central processing unit 411, a ROM 412, a RAM 413, and an interrupt processing circuit 414. In the microcomputer, as will be described later, the velocity error signal and the phase error signal are calculated by using the values latched in each ICR circuit, and both signals are combined and then filtered.
The result is supplied to the D / A conversion circuit 415. The output signal after D / A conversion output to the terminal 416 is supplied to the motor drive circuit and controls the rotation speed and rotation phase of the motor.

FIG. 1 (1e) shows the phase error signal output. The signal shown in (1e) corresponds to the proportional slope portion 107 and other portions 106 and 108.
Consists of. This signal is in phase synchronization with the H.SW signal (b). Since the phase reference value 103 is a constant value, the signal (1
The phase error signal when the rising edge in c) is at the position shown in FIG. 1 is the level at the position indicated by 105. The amount of the phase error signal when the signal (1c) shifts to the left from the position shown in the figure relative to the H.SW signal shifts from the position indicated by 105 to the left on the page by the same amount. It becomes the value at the position. The same idea should be applied when the signal (1c) is shifted to the right. When the phase error signal at the position shown by 119 is obtained, the rising edge of the signal (1c) is t _{9 in the} same figure (1a).
It is at the time position indicated by. When the phase error signal at the position indicated by 110 is obtained, the rising edge of the signal (1c) is at the time position indicated by t7 in FIG. Therefore, ti when the rising edge of the signal (1c) is input, that is, when the interrupt of irq2 shown in FIG. 4 occurs.
If the value of (i = 1, 2, 3, ...) Is known, it is possible to know which of 106, 107, and 108 the phase error region is. When the phase difference between the rotation phase of the rotating body and the reference signal is in the area of the proportional inclination portion 107, the value indicated by 104 is output as the phase error signal. When the phase shift is in the regions 106 and 108 outside the proportionally inclined portion, a phase error signal corresponding to the level of the staircase wave signal as shown in the figure is output. Each level of the staircase signal, eg 111 and 1
The level of 12 is changed every timer interrupt indicated by irq4. As described above, at each level of the staircase wave signal, the pulse signal of the next rotation phase (here, the falling edge of the H.SW signal) is near the stable position of the phase control system (the central position of the proportional inclination part). Is chosen to occur.

FIG. 5 is a diagram showing a procedure of signal processing performed by the microcomputer. In the figure, FG (k) indicates the count value latched in ICR1 at the time of the rising edge of the kth FG signal, for example. FG (k-1) is the (k-1) th
Time of rising edge of FG signal, that is, FG (k)
This is the value latched one cycle before the FG signal. FG
The value 501 of the difference between the values of (k) and FG (k-1) corresponds to the cycle of the FG signal. A value 502, which is the difference between this value 501 and the speed reference value, is the speed error signal.

On the other hand, as a process for obtaining the phase error signal, HS indicated by 503 is used.
The count value latched at the falling edge of the W signal and 5
The phase error signal is calculated by calculating the difference 505 from the count value latched at the rising edge of the 1/2 cycle signal (1/2 V _SYNC ) of the reference signal shown in 04, and subtracting the phase reference value from this 505 value. Get 506. Mix ratio setting process 507
Is a process for setting a mix ratio when the velocity error signal 502 and the phase error signal 506 are combined, and is a process for determining the amount of phase error output shown in FIG. 1 (1e). The specific process of setting the mix ratio is performed by the process of the interrupt irq3 generated by the falling edge of the H.SW signal.

A composite signal 508 of the velocity error signal and the phase error signal is, for example, a digital filter processing 509 such as a proportional integral filter.
After being obtained, it is output to the D / A conversion circuit in process 510.

Next, a specific processing procedure by the microcomputer for realizing the signal processing described with reference to FIG. 5 will be described with reference to FIGS. 6 to 10.

FIG. 6 is a flowchart showing a main processing routine that is started after the power is turned on. In the figure, process 60
1 is a process for setting an initial value, which performs a process such as setting the value of each RAM to zero. In process 602, the H.SW signal level is Hig.
It is determined whether or not it is at the h level, and if it is not at the High level, it waits for time, and if it is at the High level, processing 1 indicated by 603 is executed. In process 604, the H.Sw signal level is Low.
It is determined whether or not it is the level, and if it is not the Low level, it waits for time, and if it is the Low level, the process 2 indicated by 605 is executed. After executing the process 2, the process 602 is executed again. 6
Processes 1 and 2 indicated by 03 and 605, for example, perform a process of decoding the serial data transmitted from the system control circuit and determining what the current mode is, but are not directly related to the present invention. Since it is not present, detailed description thereof is omitted. When each of the interrupt signals irq1 to irq4 described in FIG. 4 is generated during execution of the main processing routine shown in FIG. 6, each interrupt processing is appropriately performed.

In each process below, the symbols enclosed in ()
Indicates the name of RAM. For example, (FGN) means (FGN)
It means the RAM indicated by, but in the following explanation, (FGN)
Will be described as having the same meaning.

FIG. 7 is a process executed when an interrupt of irq1 occurs, which is a process for obtaining a speed error signal. In the figure, a process 701 is a process of transferring the count value of the counter circuit 407 at the time when the interrupt of irq1 occurs to (FGN). In process 702, the count value stored in (FGO) when the interrupt signal of irq1 one cycle before the FG signal is generated is subtracted from the count value of (FGN) and stored in (WK1). In process 703, the value obtained by subtracting the speed reference value from the value of (WK1), that is, the speed error signal is calculated as (SP
This is the process of storing in D). By this processing, FIG.
The value indicated by is stored in (SPD). Process 704
Is a process of storing the current count value stored in (FGN) in (FGO) in preparation for the next interrupt calculation of irq1. The value of (FGO) is used in the process 702 when the next interrupt of irqi1 occurs.

Each process shown in FIG. 8 is a process executed when an interrupt of irq2 occurs. In the figure, the process 801 is (CT
This is a process of increasing the value of V) by 1. (CTV) is a RAM required to divide the input reference signal by half. In process 802, it is determined whether or not the value of (CTV) is smaller than 2, and if it is smaller, the process of irq2 ends. If it is larger, the processes 803 and 804 are executed, the value of (CTV) is set to zero in the process 805, and the process of irq2 ends. By performing such processing, the processings 803, 804, and 805 are executed once every two times when the interrupt of irq2 occurs. That is, this is the same as dividing the reference signal by half. The process 803 is executed for each cycle obtained by dividing the reference signal by half, and the count value of the counter circuit 407 at this time is (V
S). The value of this (VS) is 5 described in Fig. 5.
Equivalent to a value of 04. Process 804 is a process of storing the value of (CTT) in (PTV). The value of the subscript i of ti (i = 1, 2, 3, ...) Shown in FIG. 1 (1a) is stored in (CTT). Therefore, depending on this (PTV) value,
In order to obtain the phase error signal shown in e), the process of varying the mix ratio of the phase error signal to be combined with the velocity error signal may be performed. This process is performed by the process of irq3.

Each process shown in FIG. 9 is a process executed when an interrupt of irq3 occurs, and shows a main process for realizing the present invention. In process 901, the value of (CTT) is set to 1. That is, this is a process of resetting the value of ti shown in FIG. 1 (1a) to t1 at the timing of the falling edge of the H.SW signal (1b). Process 902 is a process of storing the output value of the counter circuit 407 at this time in (HS). Process 903 is (H
This is a process of subtracting the value of (VS) described in the process of FIG. 803 from the value of S) and storing it in (WK2). In process 904, (WK
The value obtained by subtracting the phase reference value from the value in 2) is stored in (PHE). By these processes, the value of the phase error signal shown in FIG. 5 506 is stored in (PHE). Process 905 (PTV)
The value of the mix ratio according to the value of is read from the ROM table. A value for weighting the phase error signal 506, that is, a mix ratio value is written in the ROM table in order to obtain the phase error output shown in FIG. 1 (1e). This value is extracted according to the value of (PTV), and the next processing 906 is performed. Process 906 is a process of dividing the phase error signal (PHE) by the mix ratio, storing it again in (PHE), and creating an actual phase error signal to be combined with the speed error signal. The process 906 shows the process of dividing the phase error signal (PHE) by the mix ratio.
It goes without saying that the value of E) may be multiplied by the mix ratio. By performing the above processing, a phase error signal weighted according to the phase error amount can be created.

Each process shown in FIG. 10 is a process executed when an interrupt of irq4 occurs. In this processing, the value of i indicated by ti is set to +1. Process 1002 is obtained in process 703 of irq1 (SP
The process of combining the value of D) and the value of (PHE) obtained by the process of riq3, that is, the speed error signal (SPD) and the phase error signal (P
HE) and each value are combined, and the combined value is stored in (SPD). The process 1003 is a process of performing a calculation of the filter unit required as a control system, but since this calculation is not the main purpose of the present invention, detailed description thereof will be omitted. A process 1004 is a process of synthesizing the speed error signal and the phase error signal and outputting them to the D / A conversion circuit.

The above is a description of specific examples of the present invention.

In the above description, as a method of modulating the rotation speed, a method of changing the output of the phase error signal has been described, but the same effect can be obtained by changing the reference value of the rotation speed to modulate the rotation speed. It will be apparent from the description in FIGS. 11 and 12 that

In addition, the response frequency of the speed control system is set higher than the response frequency in the steady state until the phase control system becomes stable after the speed of the rotating body becomes substantially constant. It is also possible to make a quick response as shown in FIG.

Further, in the above description, the cycle of the pulse signal indicating the rotation phase has been described as being equivalent to one rotation of the rotating body. However, the pulse signal indicating the rotation phase is a pulse signal generated a plurality of times per rotation. Needless to say, the same effect can be expected by using.

Further, in the description of the present invention, the control method after the rotation speed becomes a substantially constant value has been described in detail, but as the phase error signal output until the rotation speed becomes a substantially constant value, for example, a stable state It may be fixed to a value equal to the phase error signal output value in.

EFFECTS OF THE INVENTION As is clear from the above description, according to the present invention, by modulating the rotation speed in accordance with the generation position of the pulse signal indicating the rotation phase when the rotation speed becomes substantially constant,
The generation position of the pulse signal indicating the next rotation phase can be set to the pulse signal generation position where the phase control system is in a stable state, and overrun can be prevented. That is, the pull-in time of the phase control system can be shortened to the time corresponding to one cycle of the pulse signal indicating the rotation phase.

[Brief description of drawings]

FIG. 1 is a signal waveform diagram in one embodiment of the present invention, FIG. 2 is an explanatory view showing the concept of a method for modulating the rotational speed according to the present invention, and FIG. 3 is an actual rotational speed when the present invention is carried out. FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is an explanatory view showing a signal flow in a specific embodiment of the present invention, and FIG. 6 is a main processing routine. A flowchart, FIG. 7 is a flowchart for obtaining a speed error signal, FIG. 8 is a flowchart showing a processing procedure for holding a count value at a cycle of 1/2 of a reference signal, and FIG. 9 is a processing procedure for obtaining a phase error signal. A flow chart showing
FIG. 10 is a flowchart showing each processing executed at the time of timer interrupt processing, FIG. 11 is a block diagram of a portion for mixing a speed error signal and a phase error signal, and FIG. 12 is a block diagram obtained by modifying FIG. FIG. 13 is an explanatory diagram showing the concept of the pull-in time of the phase control system, FIG. 14 is a waveform diagram showing the waveform of each part of the conventional phase comparison circuit shown in FIG. 16, and FIG. 15 is a conventional speed and phase control. FIG. 16 is a block diagram of a conventional phase comparison circuit. 404-406 …… Input capture register, 414 ……
Interrupt processing circuit, SPD ... RAM that stores the value of speed error signal, CTT ... RAM that stores the number of timer interrupts, P
TV: RAM that stores the value of the timer interrupt when the reference signal is input every 1/2 cycle, PHE: RAM that stores the value of the phase error signal.

Claims (2)

[Claims] 1. A control circuit for obtaining a speed error signal and a phase error signal as digital signals, and driving a controlled object with a signal obtained by combining the speed error signal and the phase error signal, has a modulation means for modulating the rotational speed. However, the modulating means is configured such that when the phase difference between the phase reference signal and the controlled signal is within a constant phase error range, the amount of the phase error signal changes in proportion to the phase difference. When the phase difference is out of the fixed phase range, the phase comparison timing tp of the current controlled signal and the time tn of the phase comparison timing of the next controlled signal, during the period tn, than the rotation speed at the time tp, A period for driving at an accelerated or decelerated rotation speed and a period for maintaining the rotation speed at steady state are provided, and the change amount of the rotation phase during the time from tp to tn is A phase control circuit, wherein the acceleration or deceleration level is set so as to correspond to one cycle of the rotational phase of the controlled signal. 2. A patent characterized in that the time for accelerating or decelerating in the time from tp to tn is set to 1/2 of the time from tp to tn or less than that time. The phase control circuit according to claim 1.