JPH0668673B2 - Liquid crystal device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a liquid crystal device, and more particularly to a thin film transistor (TF
The present invention relates to an active matrix type liquid crystal device using T) as a switching element.

[Prior Art] and [Problems to be Solved by the Invention] TF is a typical active matrix circuit board.
A liquid crystal display device using T as an analog switching element is conceivable. In recent years, this liquid crystal display device has a higher density,
As the area increases, the number of signal lines has risen to nearly 2000, and the problems of connection with external circuits and the increase of driving ICs have become more serious, leading to lower yields and higher costs.

FIG. 7 shows an example of a conventional active matrix type liquid crystal display device. In the figure, 1 is the display unit, which is ANM.
Is a pixel driving TFT switching element, 2 is a signal line driving circuit, and 3 is a scanning line driving circuit. Reference numeral 4 is a connecting portion between the display unit 1 and the signal line drive circuit 2.

Further, FIG. 8 shows a video signal sampled and held by the signal line driving circuit 2 so as to be applied to the signal lines S (1) to S (M) of the display unit 1, and the scanning line G (1) to G (N) signals. FIG. Number of scanning lines x signal lines N x M
When the matrix 4 is used, there are M connecting portions 4. Regarding the density, for example, the number of scanning lines N = 480
Considering a liquid crystal full-color TV with a book, an aspect ratio of 3: 4 (diagonal ratio of 5), and a screen size of 7 inches, the number of signal lines is M = 1920, and the horizontal length 1 of the screen is 1 = 7 × 25.4 mm. × 4/5 ≒ 142mm Therefore, the signal line density d is The density is 13.5 per 1 mm.

Conventionally, since the high density and a large number of signal lines are connected to the external signal line driving circuit 2, the mounting reliability and the yield decrease,
In addition, the increase in cost for external drive ICs poses a problem. In addition, the size of the board is increased due to the mounting of these ICs, and the imbalance that the external circuit section is larger than the display section has been a problem.

The present invention has been made in view of the above-mentioned problems of the prior art,
The number of connections of the signal line of the active matrix circuit board to the external drive circuit is reduced to simplify the mounting, improve the yield, reduce the mounting cost, reduce the number of external signal line driving ICs, and reduce the external drive circuit. Small, compact,
The purpose is to reduce costs associated therewith.

[Means for Solving Problems] and [Operation] The present invention provides a switching element (ANM) arranged along a plurality of rows and columns, and a first control in which the switching elements are commonly connected for each row. Line (G (1), G (2) ・
..G (N-1) and G (N)) and a second control (S) in which the switching elements are commonly connected for each column
(1), S (2) ... S (M-1), S (M)) lines, a first substrate on which pixel electrodes connected to each of the switching elements are arranged, and the first substrate In a liquid crystal device having a second substrate provided with a common electrode facing each other and a liquid crystal arranged between the first substrate and the second substrate, the second control line is divided into a plurality of blocks. , Wiring the third control lines (g (1), g (2) ... g (n)) commonly connecting the control lines in the block,
A switching element 6 is arranged at each connection between the third control line and the control line in the block, and a fourth control line (s (1),
The liquid crystal device is characterized in that s (2) ... s (m)) are wired and a metal line is wired to the common electrode provided on the second substrate.

EXAMPLES The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and N × M shown in FIG.
1 is an overall view of an N × M active matrix type liquid crystal display device provided with a switching element for each pixel and an n × m active matrix circuit 5 surrounded by a broken line on the same substrate. FIG. 2 shows the inside of the n × m active matrix circuit 5 of FIG. 1, in which 6 is an analog switching transistor for video signals (hereinafter abbreviated as AS transistor), and 7 is a capacitor for video signal sample hold. , S (1) to S (m) are latched video signal lines to the AS transistor 6, and g (1) to g (n) are AS signals.
The signal line for switching of the transistor 6 is shown. Now, if the M signal lines in FIG. 7 are made into matrix wiring common to m, the signal lines S (1) to S (m) and g (1) to g (n in FIG. ) Signal line and n × m AS
A matrix circuit including the transistor 6 and the capacitor 7 can be used. However, n is an integer of 1 or more, Is. The timing of the video signal at this time and the transistor of the AS transistor 6 of FIG. 2 and the transistor of the display unit 1 of FIG. 1 has the relationship of FIG. 4 when the video signal latch circuit of FIG. 3 is used. Looking more closely,
First, in FIG. 3, when the input analog video signal 9 is output at the timing of φ ₁ , it is sampled by the transistor 10 by the pulse from the shift register 8 and held by the capacitor 11, and further the source follower buffer 12 Is buffered with. The A / D converted video signal is latched by the transistor 13 at the same timing of φ ₂ and is input to S (1) to S (m) in FIG. 1 or 2. When the latch timings are respectively t ₁ , t _2, ..., The relationship between the video signal and S (1) to S (m) shown in FIG. 4 is obtained. The transistor of the AS transistor 6 in FIG. ₂ is Δt = t ₂ −t ₁ = t ₃ −t at each timing of t ₁ , t ₂ ... tn.
_{During 2} = ..., it is turned on and the video signal output from each FIG. 3 is held in the condenser 7. Then, the horizontal retrace time of the video signal after being held at the timing of tn and the period of tG between the next latch timing and tn + 1, the transistor switching signal line of the display unit 1 in FIG. 1, that is, the pixel operation line. One of them is turned on and the A / D converted video signal is transmitted to the pixel.

By repeating the above operation for the number of operation lines, the video data for one screen is transmitted to each pixel and displayed on one screen.

Now, when trying to display an NTCSTV signal with a frame frequency of 60 Hz at N = 480 and M = 1920 at m = 240n = 8, one horizontal operation period is 63.5 μsec, and the horizontal retrace time is 11 μsec, so Δt ≦
(63.5-11) /8=6.56 μsec tG ≦ (11 + 6.56) = 17.
56 μsec. It is actually output from FIG. 3 that the timing when g (n) is turned on and the timing when G (i) (the meaning of the i-th scanning line) is turned on are simultaneously output (sample-held). There is no problem because the video signal is directly transmitted to the pixel via the transistor of the AS transistor 6 in FIG. By doing so, the charging time of the pixel switching transistor can be extended, so the load can be reduced and a compact transistor can be used.

At this time, the number of connections between the external video signal processing circuit and S (1) to S (m) in FIG. 3 and FIG. 1 or 2 is m = 240.
Since it is a book, the signal line density d is It becomes possible to FIG. 5 shows an example in which the switching signal lines S (1) to S (m) shown in FIG. 1 or 2 are arranged at a low density. Further, FIG. 6 shows S (1) to S
It is another low-density arrangement example of (m) and g (1) to g (n) (m = 240 wires and n = 8 wires are wired in a side length of 142 mm). In this case, the signal line density is Although the density is slightly increased, it has little effect on the effect of reducing the number of connections, but there is an advantage that the 12 buffers of the external signal processing unit in FIG. 3 can be made to have the same performance. That is, g (1) to g in FIG.
Since the wiring capacitances of S (1) to S (m) of (n) formed on the matrix circuit substrate at the upper and lower crossing portions are the same, the data fluctuation from the circuit of FIG. 3 can be suppressed uniformly. It can be designed to easily suppress image variations.

Note that the dividing switching transistor has the same structure as the pixel switching transistor, and the data holding capacitor can be provided in the transistor manufacturing process by a known technique, or is unnecessary when using the wiring capacitance or the like. Therefore, it is obvious that they are provided on the same substrate without mentioning details in some cases.

In particular, in the present invention, as shown in FIG. 4, the polarities of the ITO-horizontal scanning period (1H) corresponding to the common electrode provided on the second substrate are inverted with each other. However, the delay distribution can be reduced by wiring the metal (silver, aluminum, chrome, gold) on the common electrode. For example, when the common electrode is formed of an ITO electrode, this metal can be arranged in a frame shape around the ITO electrode, or can be wired in a mesh shape over the entire surface of the ITO electrode. Of course, it is also possible to combine both the frame-shaped metal and the mesh-shaped metal described above. Further, the terminals of the common electrode at this time can be provided at least at two positions of the four corners of the frame-shaped metal.

Further, in the present invention, a passive matrix type ferroelectric liquid crystal element disclosed in US Pat. No. 4,367,924 can be used in place of the active matrix liquid crystal element provided with a switching transistor for each pixel. The signal line of this ferroelectric liquid crystal element can be made common by making it block by the TFT by the method described above. At this time, as the ferroelectric liquid crystal, a chiral smectic liquid phase, particularly its C phase, H phase, I phase, J phase, K phase, G phase, F phase is suitable.

[Advantages of the Invention] As is apparent from the above-described embodiments, conventionally, 1920 signal lines can be 240 or 248, and the signal line density can be reduced.
It can be greatly reduced from 13.5 lines / mm to 1.69 lines / mm (87.5% reduction) or 1.75 lines / mm (87.0% reduction). Therefore, simplification of mounting, improvement of yield, IC for external signal processing
Not only is it advantageous in terms of cost, such as a reduction in the number, but it is also possible to make the external signal circuit smaller, more compact, and less expensive, and it is possible to prevent delay at the time of 1H inversion.

In the description, an analog video signal is taken as an example, but the present invention may be another signal, for example, a digital signal, and is not limited.

[Brief description of drawings]

FIG. 1 shows the active matrix (N × M pixels) of the present invention.
FIG. 2 is an explanatory view showing an embodiment of a liquid crystal display device, FIG. 2 is a partially enlarged view of an arrangement of M active matrixes of n × m matrix wiring of the present invention, and FIG. 3 is a diagram showing m signal lines according to the present invention. Video signal output circuit diagram, FIG. 4 is FIG. 1 or FIG.
FIG. 5 is a timing diagram of a video signal and a signal line in the case of using the third circuit and a switching signal and a pixel scanning signal to M switching elements arranged in the present invention, and FIG. Density signal line layout diagram, FIG. 6 is a low density signal line layout diagram of another embodiment of the present invention, FIG. 7 is an explanatory view showing an N × M active matrix liquid crystal display device, and FIG. 8 is a signal line and scanning. FIG. 6 is a timing diagram of lines.

Claims (1)

[Claims] 1. A switching element (ANM) arranged along a plurality of rows and columns, and a first control line (G (1), G (2)) in which the switching element is commonly connected to each row.
... G (N-1), G (N)) and a second control (S) in which the switching elements are commonly connected for each column.
(1), S (2) ... S (M-1), S (M)) lines, a first substrate on which pixel electrodes connected to each of the switching elements are arranged, and the first substrate In a liquid crystal device having a second substrate provided with a common electrode facing each other and a liquid crystal arranged between the first substrate and the second substrate, the second control line is divided into a plurality of blocks. , Wiring the third control lines (g (1), g (2) ... g (n)) commonly connecting the control lines in the block,
A switching element 6 is arranged at each connection between the third control line and the control line in the block, and a fourth control line (s (1),
s (2) ... s (m)) are wired, and a metal line is wired to a common electrode provided on the second substrate.