JPH0668727B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention executes a plurality of tasks of a program written in a high-level language in parallel in response to changes in execution conditions in real time according to designated priorities. The present invention relates to an information processing device having a function.

[Prior Art] Conventionally, as an information processing apparatus having a function of executing a plurality of processing parts (tasks) written in a high-level language in parallel in response to changes in execution conditions in real time in accordance with a designated priority, The following two methods are used.

The first method switches the execution right between tasks regardless of the instruction step of a high-level language. When each task is activated, it becomes READY state, and among the tasks in READY state, the task having the highest priority goes to RUN state, and the program written in the high-level language is executed.

If a high-level language instruction waits for the occurrence of a specific event, the task is placed in the waiting state. In this case, if there is another task in the ready state, the task has the highest priority. The task having is put in the execution state instead.

When a waiting event occurs, the task in the waiting state is set to the executable state, and the execution right is switched again according to the priority of each task.

In this method, the task execution right is switched in response to the priority assigned to each task and the occurrence of an event in real time according to the above rules.

Since a high-level language instruction is composed of a plurality of machine language instructions of the CPU, it is generally executed when a task having a higher priority enters the execution state during execution of a task. The execution right is switched even during the middle high-level language instruction.

The second method is to switch the execution right between tasks with the instruction step of the high-level language being the minimum execution unit.

In this method, the conditions for determining the task to be put into the running state from among the started tasks are the same as those in the first method. If a high-level language instruction is being executed in the task, the execution right is switched after the execution of the instruction is completed.

[Problems to be Solved by the Invention] In such a conventional information processing apparatus, the first method,
The second method has the following drawbacks.

In the first method, although the processing content of each task is described by the high-level language instruction, the switching of the execution right between the tasks is performed in the unit of the machine language that constitutes the high-level language instruction. The execution order of the entire program depends on the conditions inside the information processing apparatus, and it is difficult to accurately grasp the execution progress.

In the second method, the switching of the execution right between the tasks is delayed until the execution of the high-level language instruction is completed, so that the delay time until the execution right is actually switched becomes long.
In addition, since the execution time of each instruction in the high-level language is different, such delay time is not constant.

The first method has excellent task responsiveness to changes in execution conditions, the second method allows easy operation confirmation at a high-level language level, and one command of a high-level language is executed as an indivisible process. Therefore, common variables can be placed between tasks and commonly accessed. On the other hand, both of them have the above-mentioned drawbacks, and it is desirable to select which method to use according to the intended use. However, conventionally, a method for selecting or combining these in one information processing apparatus is used. Therefore, the users could not efficiently use each type of application.

In order to solve the above problems, the present invention provides a task in which execution rights are switched in machine language units and a task in which execution rights are switched in high-level language instructions in one information processing device. By enabling the description and execution in a composite manner, it is possible for the user to properly use the above two methods depending on the purpose.

[Means for Solving Problems] In order to solve the above problems, an information processing apparatus according to the present invention activates a single CPU (10a) and a plurality of tasks configured by the machine language of the CPU. To the executable state, select the task with the highest priority among the tasks in the executable state corresponding to the task status and priority, and select the execution right for the task in units of machine language execution steps. And event management means (11b) for detecting a hardware signal and changing the state of a task in a waiting state waiting for the generation of the hardware signal to an executable state. An operating system (11); a memory (10b) for storing a program (13) composed of high-level language instructions; A high-level language processing unit (12) for sequentially fetching high-level language instructions from a program stored in a memory and executing the processing of the instructions; and a program (13) stored in the memory (10b) in the information processing device.
Is composed of a plurality of (1, 2, ..., N) upper tasks, and each upper task is a plurality (1, 1, ..., M) of internal tasks (1-1, 1) having different priorities. -2, ..., 1-M), (2-1, 2-2, ..., 2-M), ... (N-1, N-2, ..., NM) The unit (12) uses the priority assigned to the internal task every time the internal task to which the predetermined priority is assigned is started to execute.
(a) is activated by the program (13) to sequentially fetch the instructions of the high-level language constituting the internal task to execute the instruction processing, and immediately before attempting to execute one instruction of the high-level language constituting the internal task. A higher priority than the priority assigned to all internal tasks included in the upper task is set in the high-level language processing unit (12) itself as the priority of the internal task, and immediately after the execution of the one instruction, Again, the high priority language processing unit (1
2) It is configured to be set to itself to prevent the execution right from being switched between internal tasks during execution of one instruction in a high-level language in each higher-level task,
The feature is that the execution right can be switched between internal tasks belonging to different higher-level tasks in units of machine language execution steps.

DETAILED DESCRIPTION OF THE INVENTION [Embodiment] An embodiment of an information processing apparatus according to the present invention will be described below with reference to the drawings.

FIG. 2A shows the configuration of tasks executed by the information processing apparatus according to the present invention.

The information processing apparatus according to the present invention executes a plurality (N) of upper tasks shown in FIG. 2 (a) in parallel. These upper tasks are further configured as a group of a plurality (M) of internal tasks. Each internal task is a program having an independent processing procedure described by a high-level language instruction.

Then, a non-overlapping priority is assigned to each upper task, and a non-overlapping priority is assigned to each internal task in the upper task within the upper task.

The priority of the internal task is indicated by a value (NM) that is a combination of the higher task priority (N) and the internal task priority (M), and the operating system (11) uses this combined value (NM). Manage small tasks as high priority.

Each upper task (N) has a priority called an “execution level” in addition to the internal task priority assigned to the internal task (M). In the "execution level", the value of the part corresponding to the internal task priority is zero, so the higher task (N)
Has a higher priority than any of the internal tasks (NM). The "execution level" is not assigned to a specific internal task (M), but is used to increase the priority of the internal task (M) that is being executed temporarily when a high-level language instruction is executed.

Then, by assigning the priorities shown in FIG. 2 (a),
For example, the internal task (2-2) belonging to the higher-level task (2)
Is lower in priority than the internal task (1-M) in the higher-level task (1) having a higher priority, and is an internal task (N-1) in the higher-level task (N) having a lower priority. Has higher priority than. Furthermore, the priority of the "execution level" is temporarily set to the internal task (NM) in a certain higher-level task each time execution of one instruction of a high-level language is started, and the priority of the internal task is set to zero. To the original priority when the execution of the instruction is completed.

By assigning the above-mentioned priority, the execution right of the task is switched between the internal tasks in the higher-level task in units of one instruction in the high-level language. The execution right of the task can be switched in the unit of the machine language of the CPU regardless of.

FIG. 2B is a diagram showing a logical configuration of the information processing apparatus according to the present invention.

In this figure, the usage right of the CPU 10a, the memory 10b,
The hardware 10c is positioned as the resource 10 managed by the operating system 11. The high-level language processing unit 12 (hereinafter referred to as the high-level language processing system 12. The high-level language processing system 12 is composed of a program.) Is an operating system 11.
Is given the right of use of the CPU 10a and the memory 10b, and the hardware 10c is accessed through the operating system 11. The operating system 11 has a task management function 11a and an event management function 1
1b, a memory management function 11c, and an input / output management function 11d.

The task management function 11a activates the program 13 written in a high-level language stored in the memory 10b from a specified address (task activation), and if there is another task activated, The execution right is switched according to the priority. In this case, the execution right is switched by the CPU 10a.
The machine language is used as a unit.

The event management function 11b detects a change in the condition generated from the hardware 10c and changes the state of the task activated in response to the change. When a task requests the operating system 11 to wait for a change in a certain condition, the task state is changed from the "execution state" to the "waiting state". A task in "waiting state" is changed to "executable state" when the waiting condition is satisfied.

The task management function 11a switches the execution right in response to such a change in the task status.

The high-level language processing system 12 includes an instruction execution management unit 12a and an instruction execution unit 12b, and an operating system 1
It is executed as one of the tasks under the control of 1. The high-level language processing system 12 reads a program (application program) 13 written in a high-level language one instruction at a time and interprets and executes the content to be executed. However, the actual execution is included in the high-level language processing system 12. The instruction execution management unit 12a and the instruction execution unit 12b.
The high-level language processing system 12 uses the operating system 1 according to the contents of the program 13 written in the high-level language.
The task is registered to 1 and the activation is requested.

FIG. 1B is a diagram showing a hardware configuration.
In the figure, the CPU 10a is a 16-bit microcomputer, and the OSC 10ab is a crystal oscillator. A part of the software constituting the high-level language processing device is recorded in the ROM 10ba of the memory 10b and is activated when the power is turned on to load the required software from the auxiliary storage device 10cd to the RAM 10bb via the input / output control circuit 10ca. It enables operation of the operating system 11. Instructions for the operating system 11 are input from the keyboard 10cb, and messages from the system are displayed on the CRT 10cc. Auxiliary storage device 10 cd
Is used to record programs and data.

Then, FIG. 3 is a flowchart showing an execution procedure of the instruction execution management unit 12a of the high-level language processing system 12 according to the present invention. Each internal task of the program 13 written in a high level language having the task structure shown in FIG.
When activated, the memory required to execute the program is individually given, and execution is started from the start address of the program forming the high-level language processing system 12 shown in FIG. 1 (a). The instruction execution management unit 12a is made in a re-entrant form that can be (logically) simultaneously executed by each task provided with a memory. FIG. 4 shows the third
It shows a detailed execution procedure in the case where the instruction executed in P8 of the figure is an instruction to put an internal task in a waiting state such as waiting for a certain period of time or waiting for a change in an external condition.

Next, the operation of the instruction execution management unit 12a of the high-level language processing system 12 will be described in detail with reference to FIGS.

The instruction execution management unit 12a repeatedly executes the operation of reading and executing instructions one by one from the application program 13 written in a high-level language. When the high-level language processing system 12 is instructed to start the execution of the program 13 written in the high-level language, the high-level language processing system 1
2 sets a pointer for reading an instruction at the head of the program 13 written in a high-level language, sets a pointer indicating the execution start address of the instruction of the CPU 10a at P1 in FIG. 3, and activates a task in the operating system 11. To request. When the task activated in this way is given the execution right, the task starts to execute from P1 in FIG. 3, and P1 → P2
→ P3 → P4 → P5 → P6 → P7 → P8 → P9, and then normally P3 → P7 → P8 → P9. If the high-level language instruction to be executed in P8 has a content of activating a task defined by the program 13 written in the high-level language, a process for starting execution of the program 13 written in the high-level language The operating system 11 is requested to start a task by the same processing as. Therefore, the instruction execution management unit 12
a is a program 1 written in a high-level language that has been started
The same number as the number of tasks of 3 will be used simultaneously. While repeating execution of high-level language instructions, P
The priority of the internal task is "execution level" by the processing of 2
Therefore, even if an internal task with any priority in the same higher-level task becomes ready for execution, P
Until the number reaches 3, the executing internal task holds the execution right. The flag used for the determination in P3 is information for requesting the internal task that is newly executed to switch the execution right to the internal task that is newly executed, and the execution of one instruction of the high-level language is completed. Sometimes, it is useful for performing the process of switching the execution right only when necessary. When it is detected in P3 that the interrupt flag is ON, P5 sets the priority of the internal task that was being executed to the original priority (internal task level) that is assigned in advance.

If there is an internal task that has a higher priority and is in an executable state, the execution right is transferred to that internal task. After that, when the internal task to which the execution right is transferred enters a waiting state or stops execution, the original internal task is given the execution right again and restarts execution from P6.

If the instruction executed in P8 of FIG. 3 is an instruction that puts an internal task in a waiting state such as waiting for a certain period of time or a change in external condition, the instruction is executed in the procedure shown in FIG. It P11 is a preparation for enabling the processing of P13 and P14 to be executed with the highest priority when the condition is satisfied after entering the waiting state. Here, the “interrupt level” is a priority higher than any priority set for the internal task activated by the high-level language processing system 12. After changing the priority in P11, the state of the internal task is immediately changed to the waiting state in P12. At this time, if there is another internal task in the executable state, the execution right is given to the internal task having the highest priority among them. The internal task in the waiting state immediately enters the execution state and executes P13 and P14 when the specified condition occurs. Here, the execution right is simply requested to be switched by P13 to the internal task that is executing the high-level language instruction, and when P14 is executed, the execution right is returned to the internal task that is executing the instruction. Then, when the internal task which is executing the instruction reaches P3 in FIG. 3, the interrupt flag is detected, and the priority is set to the preallocated (internal task level) in P5, the execution right is switched. , The internal task that was executing the procedure of FIG. 4 restarts from P15.

Next, an example in which the information processing apparatus according to the present invention is applied to an automatic control system will be described. FIG. 5 shows an example of the program, and FIG. 6 shows the configuration of the automatic control system. The high-level language used in the program of FIG. 5 is the BASIC language defined by the JIS standard with the addition of a function to describe multiple independent execution procedures as tasks.
In FIG. 6, the information processing device 14 is a controller in this automatic control system having the hardware configuration as shown in FIG. This system uses the adapter 1 when the sample carried on the manufacturing line reaches a predetermined position.
The control circuit 1 detects the position of the sample by the sensor of 8
7 as an interrupt signal to the information processing device 14,
In response to this, the program of FIG. 7 executed by the information processing apparatus 14 adjusts the sample through the adapter 18, measures the adjustment result by the measuring device 16, and records the data in the external auxiliary storage 15 as a file. .

The program in Fig. 5 has two high-level tasks DATA and CONT.
It is a program that has line numbers independently of each other. The instruction PROGRAM in the first line of each program declares the name of the upper task. The upper task DATA is further composed of two internal tasks. The instruction PARACT at line number 30 is the internal task name SAVEDA
The TA and the priority are declared, and the instruction END PARACT at line number 250 indicates the end of the internal task. Similarly, the line numbers 270 to 380 are the second internal task MEASURE. The upper task CONT has only one internal task MAIN. The instruction PROCESS EVENT at line number 20 of the upper task DATA declares the name MEASEND of the external event and defines the correspondence with the hardware condition. This declaration is common to each internal task in the higher-level task, and in line number 20, the event name MEASEND is associated with the condition that a measurement completion signal is generated from the measuring device 16 in FIG. In line number 20 of higher-level task CONT, the event name ADJUSUT is
It corresponds to the condition that the sample detection signal is generated from the adapter 18 in the figure. In addition, the main functions of the instructions included in these higher-level tasks will be briefly described.

COM Declares the COMMON variable in the upper task.

LOAD TASK Loads the upper task from the file with the specified name into memory.

START TASK Start the task.

START Starts an internal task.

CONNECT EVENT Enables event occurrence.

WAIT EVENT Puts the internal task in the wait state until the specified event occurs.

An outline of the program operation of FIG. 5 will be described.

First, when the upper task DATA is stored in the memory and activated, the first internal task SAVEDATA starts execution. This internal task sequentially reads the data written in the buffer using the COMMON variable by the internal task MEASURE and stores it in the file. The buffer has a capacity capable of storing 100 pieces of data, and after the final data is accessed, the leading data is repeatedly used in a ring shape. The access position of the buffer is indicated by the COMMON variable SAVEPT at the write position, and by the COMMON variable READPT at the read position. Internal task SAVEDATA is line 100, line 11
0 starts the high-level task CONT, and at line 120 the internal task ME
After invoking ASURE and enabling the occurrence of event MEASEND at line 130, the loop from line 140 to line 200 sequentially writes the read data from the buffer to the file.

The internal task MEASURE waits until the measurement completion signal is generated from the program measuring instrument 16 in FIG. 6 by the WAIT EVENT instruction in line 310, and then reads the data from the measuring instrument in line 320 and writes it in the buffer.

The upper task CONT waits for the sample detection signal to be generated from the adapter 18 in FIG. 6 and then sends the data for adjusting the sample and the data designating the start of measurement to the adapter. In the program of FIG. 7, the upper task CONT has the highest priority, and the internal task MEASURE has a higher priority than the internal task SAVEDATA in the upper task DATA. Therefore, internal task SAVEDATA program line 140 to line 20
When the measurement complete signal is generated while executing the loop up to 0,
After one instruction being executed is completed, the execution right is given to the internal task MEASURE and the lines 320 to 350 are executed. On the other hand, the upper task CONT has a higher priority between the two upper tasks, so when the event ADJUST occurs, the upper task DA
Regardless of whether a high-level language instruction is being executed in the TA, the execution right is immediately given to the internal task MAIN in the higher-level task CONT, and the lines 70 to 80 are executed.

FIG. 7 shows the execution management unit 12a of the information processing system 12 regarding the three internal tasks related to the program of FIG.
This is an individual representation of the procedure of.

In addition, FIGS. 8A to 8I show the execution management unit 12a.
FIG. 10 is a schematic diagram showing priorities assigned to each internal task in a changed state at appropriate times.

This allocation is performed by a program 13 written in a high-level language.
Although it is predetermined according to the contents described in,
As will be described in detail below, the priority may be temporarily changed to the “execution level” or the “interrupt level” in the process of execution.

Further, regarding the priority value, the smaller the value, the higher the priority.

Then, in the unexecuted state, the initial value of the priority of each internal task is assumed to be as shown in FIG. 8 (a). Therefore, in this state, the priority of the upper task N is that the upper task CONT is higher than the upper task DATA,
Internal task MEASURE has the priority of internal task M
It is higher than the internal task SAVEDATA.

The internal task SAVEDATA is normally P103, P107, P1
Lines 140 to 200 of the program are executed by repeating the route 08, p109. Internal task MEASUR
When E executes line 310 of the program, it waits until the event MEASEND occurs. The execution of this line corresponds to P211 and p212 in FIG.

As described above, in the normal execution state of the program written in the high-level language of FIG. 5, the internal task SAVEDATA is at the "execution level", and the internal task MEASURE and the internal task MAIN (belonging to the higher-level task CONT) are "Waiting state", and this state is shown in FIG. 8 (b).

The internal task M = 0 indicates that the internal task is at the “execution level”. Further, the priority indicated by () is the priority of the internal task in the "waiting state".
Furthermore, the combined value of the upper task N and the internal task M NM = 0
Indicates the "interrupt level". When the event MEASEND occurs, P213 and P214 are executed. That is, at this time, the internal task MEASURE goes from the “waiting state” to the “executable state” and then to the “execution state”. The transition from the “waiting state” to the “execution state” is the eighth
This is because the internal task MEASURE has the highest priority as shown in FIG.

Then, after executing P214 of FIG. 7, this internal task
The priority of MEASURE is changed to the initial value as shown in FIG. Due to this, the internal task SAVEDA
The TA is the highest, and the execution of the instruction of the internal task SAVEDATA of the program written in the high-level language that was being executed previously is continued. After that, when the execution of the instruction being executed by the internal task SAVEDATA ends, P103 and P10
4, P105 are sequentially executed. When P105 of FIG. 7 is executed, as shown in FIG. 8 (e), the internal task ME
Since ASURE has the highest priority, the execution right of the task is switched here, and the execution right is given to the internal task MEASURE to execute P215.

And the priority when executing the instruction of the internal task MEASURE is
As shown in FIG. 8 (f), the "execution level" is set.
The initial priority of the internal task MEASURE is higher than that of the internal task SAVEDATA. However, even if the event MEASEND occurs, the instruction of the internal task MEASURE is not executed immediately, and as described above, the internal task MEASURE is executed after the execution of the instruction being executed by the internal task SAVEDATA is completed.
It will be switched to the URE command. Thereafter, lines 320 to 360 and line 300 of the program are executed, and line 310 is again executed.
Is executed, the execution right is switched to the internal task SAVEDATA and the execution is restarted from P106. In this way, between the two parallel processing units in the upper task DATA, the execution right is switched after waiting for the execution of one instruction of the BASIC language to be completed. Also, the only internal task MAIN belonging to the higher-level task CONT executes event 60 when executing line 60 of the program.
As shown in Fig. 8 (b), the internal task MAIN is in the waiting state until JUST occurs, but the execution of this line is the seventh.
In the figure, it corresponds to P311 and P312. Also, the case where event ADJUST occurs is explained. At this time, as shown in FIG. 8 (g), the internal task MAIN goes from the “waiting state” to the “executable state” and then to the “execution state”.
As shown in the figure, since the internal task MAIN has the highest priority, it can shift from the "waiting state" to the "execution state". P
313 and P314 are executed, and when this P314 is executed, the priority of the internal task MAIN is changed to the initial value as shown in FIG. 8 (h). Furthermore, in this state,
Internal task MAIN has the highest priority, and immediately P31
5 is executed, and lines 70 to 90 and line 50 of the program are executed. Then, the priority after the execution of P315 in FIG.
As shown in FIG. 8 (i), the priority of the internal task MAIN is the "execution level" in the upper task CONT. Even in this state, the internal task MAIN has the highest priority. In this case, when an event occurs, the upper task DA
Even if an instruction of a high-level language program is being executed in TA, the execution right is immediately given to the upper task CONT when the event ADJUST occurs.

As described above, in the program shown in FIG. 5, a higher-level task having two internal tasks whose execution rights are switched in units of BASIC language instructions and the internal tasks
Execution of the BASIC language instruction is executed in combination with another higher-level task that can obtain the execution right independently.

As described above, according to the information processing device of the present invention,
It is possible to execute both a task whose execution right is switched in units of machine language that constitutes a high-level language instruction and a task whose execution right is switched in units of high-level language instructions. The former is suitable for processing that should respond to changing conditions with minimal delay. In the latter case, data can be easily converted using common variables (COMMON variables) between tasks,
In addition, since the execution progress as a whole can be grasped in units of high-level language instructions, there is an effect that efficient interrupt control with good efficiency in program development and operation check can be performed. Furthermore, by being able to execute both of these in combination, it becomes possible to make both the responsiveness of the program and the easiness of creating the program compatible by properly using both depending on the nature of the processing target.

[Brief description of drawings]

FIG. 1 (a) is a block diagram showing the present invention, and FIG. 1 (b).
Is a diagram showing a hardware configuration of the device, FIG. 2 (a).
Is a schematic diagram showing a task configuration of the information processing apparatus of the present invention,
FIG. 3B is a diagram showing a logical configuration of the device, FIG. 3 is a flowchart showing an execution means of an instruction execution management unit of the high-level language processing system of the device, and FIG. 4 is a high-level language. FIG. 5 is a flow chart showing “waiting state” management of internal tasks in the instruction execution unit of the processing system, FIG. 5 is a program showing an embodiment in which the information processing apparatus of the present invention is applied to an automatic control system, and FIG. FIG. 7 is a configuration diagram of the automatic control system, FIG. 7 is a flowchart showing an execution procedure for each internal task of the program of FIG. 5 in the automatic control system, and FIGS. 8 (a) to (i) are the automatic control system. 3 is a schematic diagram showing the priority of each internal task of the program in FIG. N ... High-level task group, M ... Internal task group, 10 ... Resource, 10a ... CPU, 10b ... Memory, 10c ...
Hardware, 11 ... Operating system, 1
2 ... High-level language processing system, 12a ... Instruction execution management section, 12b ... Instruction execution section, 13 ... Program written in high-level language (application program).

Claims (1)

[Claims] 1. A single CPU (10a); a plurality of tasks composed of a machine language of the CPU are activated to be in an executable state, and the executable state is associated with the state and priority of the task. Task management means (11a) that selects the task to which the highest priority is assigned from among the tasks, and gives the execution right to the task in units of machine language execution steps; An operating system (11) having an event management means (11b) for changing the state of a task in a waiting state waiting for the generation of a wear signal to an executable state; and a program (13) composed of high-level language instructions. A memory (10b) for storing; a high-level language instruction that is activated by the task management means and is sequentially extracted from the program stored in the memory, and the instruction processing is performed. Level language processing unit for executing (12); an information processing apparatus having the program stored the in the memory (10b) (13)
Is composed of a plurality of (1, 2, ..., N) upper tasks, and each upper task is a plurality (1, 1, ..., M) of internal tasks (1-1, 1) having different priorities. -2, ..., 1-M), (2-1, 2-2, ..., 2-M), ... (N-1, N-2, ..., NM) The unit (12) uses the priority assigned to the internal task every time the internal task to which the predetermined priority is assigned is started to execute.
(a) is activated by the program (13) to sequentially fetch the instructions of the high-level language constituting the internal task to execute the instruction processing, and immediately before attempting to execute one instruction of the high-level language constituting the internal task. A higher priority than the priority assigned to all internal tasks included in the upper task is set in the high-level language processing unit (12) itself as the priority of the internal task, and immediately after the execution of the one instruction, Again, the high priority language processing unit (1
2) It is configured to be set to itself to prevent the execution right from being switched between internal tasks during execution of one instruction in a high-level language in each higher-level task,
An information processing apparatus, wherein execution rights are switched in units of machine language execution steps between internal tasks belonging to different higher-level tasks.