JPH0668743B2 - Storage switchboard line interface configuration method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line interface of a storage exchange, and more particularly to a configuration system of the line interface of a large capacity storage exchange that accommodates a large number of high speed lines.

[Background of the Invention]

Regarding the configuration of the exchange using the protocol LSI (large-scale integrated circuit) and the number of accommodated lines, IC (IC
C) '83 B3.7.1 to B3.7.5 "A.B.S.I.
Four Communication Control (A VLSI
For Communication Control) ”,
The number of lines accommodated is limited by the allowable waiting time for memory access of the protocol LSI and the allowable value of overrun / underrun. As a result, the number of accommodated lines must be limited or reduced even if the capacity of the exchange is increased by using a high-speed processing device or the like to increase the accommodated lines or to further increase the accommodated lines.

[Object of the Invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a line-corresponding section configuration system that equivalently increases the allowable waiting time when accessing a memory of a protocol LSI and increases the number of lines accommodated in a storage exchange.

[Outline of Invention]

The present invention relates to a memory access of a protocol LSI,
Read access eliminates contention of multiple lines and waiting for memory access time by read-ahead, and write access uses first-in first-out memory (FIF
O) is used to temporarily store the request from the protocol LSI in the FIFO and eliminate the waiting time as in the case of the read side access, thereby increasing the allowable waiting time equivalently.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. First
In the figure, 1 is a protocol LSI (large-scale integrated circuit), 2 is a peripheral part of the protocol LSI according to the present invention, 3 is an AND gate, 4 is an inverter, 5 is a memory access controller (ACTL), 6 is a read access controller (RCTL). ), 7 is a write access controller (WCTL), 8 is a protocol LSI
Read / write control line (R / W) from, 9 is protocol L
A memory access request line (BRQ) from SI, 10 is an address during read access or address during write access, and strobe signal line (STB) 11 indicates that data has been confirmed. 11 is a memory access request reception from a protocol LSI. Signal line (BACK), 12 memory access completion signal line (DACK), 13 address and data bus from protocol LSI, 14 memory access request signal line (MBRQ) from RCTL or WCTL, 15 memory from ACTL Accessing signal (MBACK), 16 is a reception signal (MACK) for a memory access request from ACTL, 17 is a memory access end signal (ACK), 18 is a memory access request signal (MRQ) from ACTL, 19 is a read or Write access instruction signal (RWCTL), 20 is a strobe signal indicating that the address and data at memory access are fixed (ADS), 21 is an address data bus between the memory and the.

In FIG. 1, the protocol LSI 1 sends a memory access request by the BRQ 9 when the buffer in the LSI becomes empty or full in the sending operation or the receiving operation, and when the memory access request acceptance is received by the BACK 11, the read or the read by the R / W 8 is performed. It is assumed that write is designated, information is sent to the address and data bus 13, memory access is performed by STB10, memory access completion is recognized by DACK12, and data is fetched in the case of read access. RCTL6 of protocol LSI peripheral part 2
Has a function of accessing the memory for one word in advance, and has an address register for storing an accessed address and a data register for storing read data. First, if there is a read access to the memory address N, the address N is accessed, the read data is sent to the protocol LSI 1, and then the address is incremented to N + 1.
The address is accessed, the read data is stored in the data register, and the content of the address register is set to N + 1. Next, if there is a read access from the protocol LSI 1 to the address N + 1, the contents of the data register are compared with the contents of the address register.
The address register contents to N + 2,
The address N + 2 is accessed and the read data is stored in the data register. After that, the address is sequentially incremented and the access is continued. The WCTL7 has a function of storing 1 W of write access, and has an address register and a data register. When there is a write access from the protocol LSI, the address is stored in the address register and the data is stored in the data register, the protocol LSI 1 is notified of the completion of the access by DACK 12, and at the same time the memory access is started, and when the memory access is completed, the address register and the data register are registered. To be empty and ready for the next write access.
ACTL5 is MBRQ from RCTL6 and WCTL7
14 contention control and interface signal with memory are created.

An example of the memory access time chart described above is shown in FIGS. Figure 2 shows the protocol LSI
The case where the RCTL 6 or WCTL 7 can perform the preceding processing for the access from 1 is shown, and the access is completed in a short time. FIG. 3 shows a case where the RCTL6 or WCTL7 cannot perform the preceding processing, and it takes a considerable time to return the DACK12. FIG. 4 shows memory access from RCTL6, and FIG. 5 shows memory access from WCTL7.

As described above, according to the present invention, by performing the preceding process for one access, the allowable waiting time for the memory access from the protocol LSI 1 is doubled, and the number of accommodated lines limited by the overrun or underrun probability. Can be increased.

〔The invention's effect〕

According to the present invention, the allowable waiting time at the time of memory access from the protocol LSI can be increased, which is effective in increasing the number of lines accommodated in the storage exchange. For example, if the preceding process for one access is performed, the allowable waiting time is doubled, and if the overrun probability is fixed, the number of accommodated lines defined by the traffic calculation formula such as M / D / 1 increases. effective.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a line interface unit according to the present invention, FIGS. 2 and 3 are time charts when a memory is accessed from a protocol LSI, and FIGS. 4 and 5 are diagrams from a peripheral part of the protocol LSI according to the present invention. It is a time chart at the time of memory access. 1 ... Protocol LSI, 2 ... Protocol LSI peripheral section, 3 ... AND gate, 4 ... Inverter, 5 ... Memory access control section, 6 ... Read access control section, 7 ... Write access control section, 8 ...... Read / write control line, 9 ... Memory access request line, 10 ... Strobe signal line, 11 ... Memory access request acceptance signal line, 12 ... Memory access completion signal line, 13 ... Address and data bus, 14 ...... Memory access request signal line, 15 ...... Memory access signal, 16 ...... Memory access request acceptance signal, 17 ...... Memory access end signal, 18 ...... Memory access request signal, 19 ...... Read write access instruction signal, 20 ... Strobe signal, 21 ... Address and data bus.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Zenichi Yashiro 3-9-11 Midoricho, Musashino-shi, Tokyo Nippon Telegraph and Telephone Corporation, Communication Network 1st Research Laboratories (56) Reference JP-A-53-68921 (JP) , A) JP-A-50-99045 (JP, A)

Claims (2)

[Claims] 1. A write access for processing a direct memory access request activated from the protocol processing circuit in a line interface of a storage exchange using a protocol processing circuit having a direct memory access control function for processing a communication protocol. A control circuit, a read access control circuit, and a contention control circuit for controlling contention between write access and read access are provided between the protocol processing circuit and the memory, and the write access control circuit has a predetermined number of times. First-in first-out accumulating means for accumulating write access information, and the read access control circuit carries out a predetermined plurality of read accesses based on the first read address transmitted from the protocol processing circuit. Address for creating the second read address Read access preceding means comprising a converting means, a first accumulating means for accumulating a second read address, and a second accumulating means for accumulating the data read from the memory at the second read address; Comparing means for comparing the first read address with the second read address, and control means for transmitting the data of the second accumulating means to the protocol processing circuit and controlling the address converting means by the output of the comparing means. The line control unit configuration system of the storage exchange, wherein the contention control circuit controls at least the write access control circuit, the read access control circuit, and the memory. 2. A read access to the control means of the read access control circuit according to claim 1, prior to transmission data read access from the protocol processing circuit, when transmission start of data to the protocol processing circuit occurs. The line corresponding part configuration system of the storage exchange according to claim 1, further comprising a function of transmitting a request signal.