JPH0668769B2 - Pattern recognizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern recognition device, and more particularly, to a pattern recognition device that can recognize a pattern in an analog manner without being affected by the orientation and size of the entire pattern. is there.

2. Description of the Related Art Today, so-called pattern recognition devices are widely put to practical use in the industrial field as character reading devices and component sorting devices. The common point of the method of configuring these devices is that various characteristics that the recognition object group have in common are arithmetically extracted from the input pattern data to perform category classification.

Generally, the arithmetic processing unit of such a pattern recognition device is
It is composed of a digital processor and a dedicated circuit such as a fast Fourier transform circuit for extracting a specific feature amount. The contents of the program used in the digital processor are determined according to the object. The specialization of such a recognition function is based on a request for industrial application whose primary purpose is to perform recognition at higher speed.

On the other hand, however, the specialization requires the design of a device in the recognition target category and the creation of a program, and the technology for that purpose is specialized, and the design and correction work have become complicated.
In addition, the complexity of the category classification process reduces the reliability of the recognition result and makes quality control of the product difficult. From a manufacturer's point of view, this indicates that high-level design work corresponding to each order specification is required, and the production cost will increase, including the training of specialized engineers.

In addition, on the side of the user who uses the recognition device, there is a problem that the technical information about the recognition target itself, which should originally stay inside the user, leaks to the maker side, and it is also used technically such as replacement with a new model to improve its function. There is also a cost problem.

Problems to be Solved by the Invention As described above, the pattern recognition device is currently facing the harmful effects of its specialization and complication.

Therefore, the applicant of the present invention solves the various drawbacks of the conventional pattern recognition device as described above and proposes a general-purpose pattern recognition device, which is disclosed in Japanese Patent Application No. 59-249249.
7075), Japanese Patent Application No. 59-249250 (Japanese Patent Application Laid-Open No. 61-127076),
In Japanese Patent Application No. 61-158986, we proposed a pattern recognition device that can recognize a pattern in an analog manner without being affected by the direction and size of the entire pattern.

The pattern recognition devices proposed in those applications reduce the dependence of the configuration of software and hardware on the recognition target category to a great extent. On the side, it was possible to accumulate pattern information that did not depend on the outside, and fulfilled its intended purpose. However, it was not a perfect pattern recognition device. For example, it consists of two orthogonal lines Furthermore When and are close to each other ', etc. cannot be distinguished from each other,
Furthermore, it was not possible to distinguish between figures formed by "closed lines" such as triangles and squares.

Therefore, the present invention is to provide a pattern recognition device capable of recognizing a graphic in an analog manner without being affected by the direction and size of the entire pattern.

Background of the Invention Like a conventional pattern recognition device, various features that a recognition target group commonly has are arithmetically extracted and collated from input pattern data, and as long as a method for performing category classification is adopted,
As the accuracy of the pattern recognition device is improved, it is inevitable that it will be specialized and complicated.

As discussed in Japanese Patent Application No. 59-249249 (Japanese Unexamined Patent Publication No. 61-127075) and Japanese Patent Application No. 59-249250 (Japanese Unexamined Patent Publication No. 61-127076), the recognition made by humans and other living things is , A method completely different from the data processing of the conventional pattern recognition device is used.

The living body receives various stimuli that are input from the external environment, that is, the so-called five senses such as vision, and is not only interpreted and accumulated by the brain or the plexus in light of its experience, but also constant for events that have never been experienced. Can be interpreted. Also,
The living body reflects not only foreign information but also changes in its own internal state (endocrine, disease, etc.) in its interpretation work. It is clear that the unique cognitive ability as described above enabled the long-term continuity of billions of years of life.

The structure of the brain and plexus that has such ability has a part that is specialized for each recognition target, but most of the structure is a large-scale neural network composed of repeated neural networks with a single structure. Is. According to the teachings of neuroscience, the individual nerve cells that make up the neural network receive electrical stimulation from thousands or tens of thousands of other nerve cells, and become themselves or many other nerve cells. An electric pulse is sent to it. The delivery of this pulse is called "ignition".

Then, the firing condition of a nerve cell is determined by the input stimulus and the internal state of the cell itself, but at the same time, given that certain brain cells perform certain recognition, even a single nerve cell will fire Can be considered to be the result of performing a local interpretation.

Seen from another angle, nerve cells exchange electrical impulses with each other as described above, and there are some methods of giving electrical impulses that suppress firing and others that promote the brain. It looks like a positive feedback and negative feedback control circuit, and an oscillation network. In fact, from the fact that electric brain waves that indicate the activity state of the entire brain are observed, it can be interpreted that the brain is constantly oscillating and performing cognitive and other activities.

Furthermore, regarding the complexity of the neural network, in humans more than 10 billion nerve cells are not connected at all at random, but from the anatomical knowledge, the same connection pattern of tens or thousands of units. It is known to be a repetition of.

The above is the characteristics of the so-called hardware of the brain as a pattern recognition device.

Next, we consider the software aspect of neural network operation. It can be seen that changes in the spatial and temporal distribution on the neural network of firing caused by stimulation from inside and outside the living body indicate the progress of the interpretation in the brain, that is, the movement of the recognition software and the information processed therein. The difference between the brain and the digital processor is that (1) the program and data are not stored separately, and (2) the data processing in each local unit on the neural network is executed completely in parallel, and they are harmonized as a whole. That is to get a good output.

Explaining in a little detail that the program and the data in the above item (1) are not separately stored, although the program and the data are mixed in the memory device in the digital processor, the command word and the data are clearly written when the digital processor is used. Since it is discriminated, it is effectively regarded as a separate storage. On the other hand, the neural network is neither such a stored program digital processor nor a discrete logic circuit which is the opposite of it. In other words, the neural network is considered to have a specific structure in which the progress of data processing gives rise to a new experience and produces the next data processing structure.

Also. If we talk about the parallel data processing on the neural network and the harmony as a whole as described in (2) above, the firing state inside the local neuron group cooperates to create the overall harmony. Can also be said to have some kind of information about the overall state and goals, and that information from other parts was transmitted with a time delay. Such ability is considered to be pattern recognition in a broad sense including not only visual recognition but also voice recognition and other various senses, and moreover, it is essential to the pattern recognition device currently in practical use as described above. Has no drawbacks. In other words, the following recognition software is automatically created by accumulating cognitive nerves.
It is not necessary to provide new software for the next object from the outside, and the hardware is capable of coping with changes in the recognition function by repeating the same structural unit.

The inventor of the present invention, as a result of research focusing on the excellent pattern recognition ability and characteristic structure of such a living body,
The present invention has been completed.

Means for Solving the Problems That is, the pattern recognition apparatus according to the present invention displays the pattern preprocessing unit 1 as shown in FIG.
And an information integration section 2 having a first cell block 2A and a second cell block 2A, and a memory section 3, which are three functional units.

The preprocessing unit 1 converts the input 4 into a two-dimensional bit pattern.

The first cell block 2A has a multi-layer structure, and each layer has 2 layers.
It is composed of a plurality of nonlinear oscillators 2a arranged in a dimensional matrix, and the nonlinear oscillators 2a of each layer are connected via a bus 5 so as to be excited by corresponding bits of the bit pattern, and The two-dimensional bit patterns adjacent to each other in the plane direction of the two-dimensional matrix are connected to each other so that the excitation is mutually strengthened only in a predetermined direction within the plane of the two-dimensional matrix different for each layer. The non-linear oscillator corresponding to the continuous line segment of and having the same direction is selectively excited.

On the other hand, the second cell block 2B also has a multi-layer structure, and each layer is composed of a plurality of non-linear oscillators 2b arranged in a two-dimensional matrix. As excited by the corresponding bit of
For example, in the plane direction of the two-dimensional matrix, the layers are connected to the first cell block 2A via the bus 5 and the excitation is mutually controlled only in a predetermined direction within the plane of the two-dimensional matrix different for each layer. Adjacent ones are connected to each other, and the non-linear oscillators corresponding to the ends of the continuous line segments of the two-dimensional bit pattern are selectively excited for each layer.

The memory unit 3 is composed of a plurality of non-linear oscillators coupled to the first and second cell blocks 2A and 2B via, for example, buses 6 and 7, and the non-linear oscillators output the other output. Are connected so as to be inverted and input, and the plurality of nonlinear vibrators are connected in a connection pattern corresponding to a specific pattern, and the first and second cell blocks 2A and The 2B excitation non-linear oscillator interacts with each other and is selectively excited.

Then, the non-linear oscillators of the memory 3 connected to the specific pattern corresponding to the excitation patterns of the non-linear oscillators 2a and 2b of the first and second cell blocks 2A and 2B are selectively excited. I'm getting used to it.

In the above configuration, the type of the input 4 itself is not particularly limited, and is all information such as visual information, audio information, and other separable features.

Operation In the above-described pattern recognition apparatus according to the present invention, the pattern preprocessing unit 1 analyzes or transforms the input 4 and develops it into a two-dimensional bit pattern having various quantities such as length, position, and brightness as a scale.

In the example of FIG. 1, the result is developed into a two-dimensional bit pattern of (p, q), and the corresponding elementary unit (““ (Marked with "*") indicates that an output change appears and its distribution shape is a pattern in which the L-shape is inverted.

This distribution shape is input to the first block 2A of the information integration unit 2 via the bus 5 as an elementary information signal. First block
2A converts the output of the pattern preprocessing unit 1 into a time-series integrated signal (that is, a signal integrated as a time-varying signal). As described above, the first block 2A is a three-dimensionally stacked non-linear oscillator 2a as shown in FIG. Hereinafter, the non-linear oscillator including the elements used in the first block 2A, the second block 2B and the memory unit 3 will be referred to as a "simple cell" or "angle cell".

The simple cells of the first block 2A are connected via the bus 5 so as to be excited by the corresponding bits of the bit pattern of the pre-processing unit 1, and the predetermined cells in the plane of the two-dimensional matrix different for each layer are provided. Since the two adjacent two-dimensional matrices are connected to each other in the plane direction so as to mutually strengthen the excitation only in the directions, the inclination of the line segment drawn by the (*) mark appearing in the (p, q) plane react. The horizontal layers of the simple cell are (p,
q) A plane is a plane for parallel projection and is called a "hyperplane". On the other hand, the vertical simple cell group is an array in which different simple cells are associated with each other by the inclination (maximum value 180 degrees) of the above-mentioned line segment passing through each elementary unit of the projected (p, q) plane, Each column is a "hyper column"
Called. As shown in FIG. 1A, the pattern recognition apparatus of FIG. 1 corresponds to 0 °, 45 °, 90 ° and 135 ° in order from the top. On the other hand, as a result of assuming that the input 5 given from the pattern preprocessing unit 1 is formed from the line segments with the inclinations of 0 ° and 90 °, the simple cell groups marked with (*) in the figure reacted. It shows the situation.

Thus, it is clear that the pattern of the reaction distribution dispersed in the simple cells of the first block 2A represents the feature included in the input 4. The pattern of the reaction distribution includes an absolute position (for example, a position in three-dimensional coordinates) in the first block 2A of each reacted simple cell and a relative positional relationship between the cells (for example, distance and direction).

On the other hand, the second block 2B is, as shown in FIG. 1B, 0 ° and 180 °, 45 ° and 225 °, 90 ° and 270 °, 135 in order from the top.
It has a 4-layer structure corresponding to ° and 315 °. But,
For example, the simple cell 4 of the first block 2A in each layer
One is connected to one and is excited (1
They may be combined correspondingly one by one, or one may be combined corresponding to a plurality of numbers other than four). Each simple cell is composed of two parts as shown in FIG. 1, and each part of the simple cell has two directions opposite to each other (0 ° in the upper left layer in FIG. 1B). And 180
(Direction of (.degree.)) Is coupled so as to influence the excitation state of the adjacent simple cells in one direction. Specifically, each part of the simple cell of the second block 2B is adjacent to the simple cell in the direction given to that part if it is excited by the corresponding simple cell of the first block 2A. Acts to weaken the excitation of. However, if it is not excited by the corresponding simple cell of the first block 2A, it has no influence on the excitation of the portion of the adjacent simple cell.

Each simple cell of the second block 2B shown in FIG. 1 is shown divided obliquely. In the uppermost layer, the right half of each simple cell weakens the excitation of adjacent simple cells in the direction of 0 °, and the left half weakens the excitation of adjacent simple cells in the direction of 180 °. Has been done. Similarly, the two angles shown at the left end of each layer of the second block 2B shown in FIG. 1 are such that the right angle indicates the direction of the adjacent simple cell in which the right half of each simple cell weakens the excitation, and the left side The left half of each simple cell indicates the direction of the adjacent simple cell that weakens the excitation.

Thus, in the second block 2B, the simple cells corresponding to the excited simple cells of each layer of the first block 2A are excited, but the line segments formed by the excited simple cells of each layer of the first block 2A are excited. Only the simple cell corresponding to the edge holds the excitation. In the second block 2B, therefore, only simple cells corresponding to the ends of the two-dimensional bit pattern are excited, as indicated by the (*) mark in FIG. That is, in the uppermost layer, the simple cell at the left end cannot weaken the excitation from the 0 ° direction, so that the excitation in the 0 ° direction portion of the simple cell at the left end is maintained. However, the simple cell at the left end of the same uppermost layer weakens the excitation from the direction of 180 °, so the excitation at the 180 ° direction part of the simple cell at the left end disappears. On the other hand, the simple cell at the right end of the same upper layer cannot weaken the excitation from the 180 ° direction,
Excitation in the 180 ° direction of the simple cell at the right end is maintained. However, since the simple cell at the right end of the same uppermost layer weakens the excitation from the 0 ° direction, the excitation at the 0 ° direction part of the simple cell at the right end disappears.

Then, the excitation of the simple cells in the first and second blocks 2A and 2B is transmitted to the memory unit 3 to excite the simple cells of the memory unit 3. As described above, the simple cells of the memory unit 3 are connected in pairs so that the other output is inverted and input, and are connected in a connection pattern corresponding to a specific pattern. Here, the “specific pattern” is a recognized pattern, for example, a straight line,
Triangles, squares, etc. That is, the simple cells of the memory unit 3 are connected to a connection pattern corresponding to a straight line, a connection pattern corresponding to a triangle, a connection pattern corresponding to a quadrangle, and the like. Further, the excitation of the simple cells of the memory unit 3 is also fed back to the corresponding simple cells of the first and second blocks 2A and 2B.

Thus, due to the mutual influence and the mixture of the reaction pattern and the memory contents, the excitation of the simple cells of the memory unit 3 connected by the connection pattern corresponding to the reaction pattern finally remains, and the pattern is changed by the simple cells in the memory unit. Be recognized.

When the excitation of the information integration unit 2 and the excitation of the memory unit 3 draw each other, it can be determined that the recognized pattern matches the pattern stored in the memory. However, if the excitation of the information integration unit 2 and the excitation of the memory unit 3 do not attract each other and the excitation simple cell of the memory unit 3 disappears, the recognized pattern is completely different from the pattern stored in the memory. I can judge.

Various circuit systems are known for non-linear oscillators that constitute simple cells, and they are put to practical use in many fields. The common characteristic is that a complicated oscillation waveform can be generated because the next state is determined by the combination of the internal state of the circuit and the external input at each instant. Therefore, each simple cell is equipped with multiple external input terminals and internal output terminals,
The simple cells are connected to each other to form a non-linear vibration circuit network that interferes with each other in a complicated manner. The non-linear vibration circuit network constitutes the first and second blocks 2A and 2B of the information integration section 2 and the memory section 3. Therefore, the memory unit 3 is not a fixed unit that stores the voltages corresponding to the numerical values "1" and "0" as in a normal digital system, but the vibration state is the content of the memory. The basic form of the circuit can be almost the same as the hyper column which is a set of simple cells. Therefore, the simple cells of the memory unit 3 receive the excitation patterns in parallel via the buses 6 and 7 and collate the excitation patterns with the vibration patterns respectively possessed by each. The collation result is sent to the information integration unit to further strengthen the vibration of the simple cell that has shown the corresponding reaction. This process circulates on the loop of the information integration unit 2 memory 3 information integration unit 2, so that the partial simple cells having a high degree of coincidence in the memory unit eventually expand the amplitude preferentially, and other than that. Determines the recognition result by decreasing the amplitude.

First Embodiment A first embodiment of the pattern recognition apparatus according to the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the basic configuration of the embodiment of the pattern recognition apparatus according to the present invention. In the illustrated pattern recognition apparatus, the pattern preprocessing unit 1 in FIG. 1 is composed of a camera 8, a contour line extraction circuit 9, and a distribution conversion circuit 10. The information integration unit 2 includes a simple cell block 11A corresponding to the first block 2A and a first block 2B.
And an S / A conversion block 11C that connects the angle cell block 11B and the angle cell block 11B. The simple cell block 11A and the angle cell block 11B receive a clock from the clock oscillator 12. The memory unit 3 is composed of a memory block 13.
Various devices as shown in the drawings and described later are transmitted and received between the above-mentioned devices 8 to 13, and an operation monitor 133 is provided.

The camera 8 captures a target image and captures a normal video signal.
16 is sent to the contour extraction circuit 9.

The contour extraction circuit 9 extracts the contour line of the object from the grayscale distribution data of the image plane given by the normal video signal 16, and outputs the contour signal 17 to the distribution conversion circuit 10. As this method, the differentiation method for the grayscale distribution is often used and is well known, so the description thereof will be omitted.

As an example, when an object having a shape as indicated by reference numeral 27 in FIG. 3 (c) is shown on the camera 8, the contour signal 17 is on the abstract contour distribution plane 28 as shown in FIG. 3 (b). Draw an almost triangular contour line.

The distribution conversion circuit 10 divides the contour distribution plane 28 into a plurality of meshes such as a rough plane 29 as shown in FIG. 3A, and data of points representing a plurality of contour lines on the plane 28 to which each mesh corresponds. The presence / absence of the contour line in each mesh is obtained from the simple cell block 11A as the converted contour signal 18.
Give to.

Since the function of the distribution conversion circuit 10 can also be easily realized by a known method, the description of the internal structure will be omitted.

Next, the functions of the simple cell block 11A and thereafter will be described. Here, one of the features of this embodiment is that the same type non-linear oscillator circuit (referred to as a unit oscillator) is adopted for the simple cell block 11A, the angle cell block 11B, the clock oscillator 12, and the memory block 13. .
A circuit example of this unit oscillator is shown in FIG.

As shown in FIG. 4, the unit oscillator has operational amplifiers 30 to 36, and (+) and (−) attached to the operational amplifiers 30 to 36 respectively indicate the input and output signal polarities. . Then, by adding a resistor and a capacitor as shown in the figure, the operational amplifiers 30 and 31 become integrators, and the operational amplifier 34
Is a differentiator, and the other operational amplifiers 32, 33, 35 and 36 are used as a sum and connected as shown. Further, multipliers 37 and 38 are provided, and further, variable resistors 39 to
41 is provided, of which the variable resistors 39 and 40 work together.
Input signals are given from terminals A, B and D, and outputs are obtained from terminals P and Q.

This unit oscillator is a basic vibration
It is a kind of so-called Van der Pole type vibration circuit that is generated in the feedback circuit consisting of 30, 31, 32 and the other part gives a non-linear vibration characteristic.

The vibration amplitude increases when an appropriate positive voltage is applied to the input D, and decreases when a negative voltage is applied. Further, the inputs A and B are terminals of an interference input for vibration, and are influenced by other unit oscillators via these terminals. The outputs P and Q are out of phase with each other by 90 ° when there is no interference, and when there is an interference input, the phase difference increases and decreases, and the output frequency and amplitude of the outputs P and Q change.

The unit oscillator described above is represented by a block diagram as shown in FIG. 5 in the following description. In addition,
When the unit oscillator used for the simple cell block 11A vibrates at the angular frequency ω, the unit oscillator used for the angle cell block 11B and the memory block 13 vibrates at the angular frequency ω / 2.

FIG. 6 shows the correspondence with the inclination distribution plane 29 of the simple cell block 11. Simple cell block
The simple cell 41 forming 11A is formed by using the unit oscillator described above. Each mesh of the inclination distribution plane 29 divides the screen image taken by the camera 8, that is, the mesh 46, and an array of four simple cells in the Z-axis direction corresponds to each. For example, the simple cells 42 to 45 are assigned to the mesh 46, and as a result, the simple cells appear as four layers. This correspondence is that when a contour line is detected in the mesh, a positive voltage is applied to the D terminal of the unit oscillator of the simple cells 42 to 45.

The connection on the circuit that enables such voltage application is, for example, a distribution conversion circuit corresponding to the mesh 46 as shown in FIG.
The D signal indicating the presence or absence of the contour line of the partial circuit 46A in 10 is distributed to the simple cell groups 42 to 45 so as to be input, and the same connection is made to all other meshes and simple cells. A negative voltage is supplied to the D terminal in the portion where the contour line does not exist.

In the following, in the conceptual diagram of FIG. 6 like the simple cells 42 to 45, the array of simple cells forming the pillars in the Z direction is called a hyper column, while the planes formed by the simple cells in the XY plane are hyper. It is called a plane.

Each simple cell receives an interference input from another simple cell in the same hypercolumn, an interference input from another simple cell in the same hyperplane, an output of the clock oscillator 12 and a memory 13, and changes its vibration state. .

The internal circuit of a simple cell is shown in FIG. In FIG. 8, a simple cell is indicated generally by the reference numeral 47, and the simple cell is coupled to an intra-block bus 48 through which output signals of all the simple cells in the simple cell block pass. The simple cell 47 receives the cell clock signal synthesized from the output of the clock oscillator 12 via the inputs 49 and 50, the input 51 corresponds to the D input shown in FIG. 7, and the input 52 is the memory 13 The feedback signal from the input conversion circuit 52
Input via A. This input conversion circuit 52A includes a multiplier 52B that receives the Ps pulse from the memory and the output of the SA conversion block 11B, and a second multiplier that receives the output 105 of a point gate and the output of the multiplier 52B described later. Has 52C.

A simple cell that receives such a signal has adders 53 to 58, a multiplier 59, a pulsing circuit 60, and a unit oscillator 61, which are connected to each other as shown in the figure, of the unit oscillator 61. Output signals 62 and 63 are coupled to intra-block bus 48.

The adders 53 and 55 receive and add the P output and Q output of other simple cells in the same hyper column through the gain adjusting resistor groups having appropriate values, respectively. On the other hand, the adders 54 and 56 receive and add the P output and Q output of another simple cell in the same hyperplane through the gain adjusting resistor groups having appropriate values, respectively.

First, the other cells in the same hyper column are connected with polarities such that the amplitudes of P and Q of the unit oscillator become small. This is because each simple cell in the same hyper column corresponds to the direction of the line segment and thus weakens the output from each other.

The inside of the hyperplane will be described with reference to FIG.
In FIG. 9, reference numerals 64 and 65 are simple cells, and reference numerals 66 to 69 are top views of the hyperplane. The inclination of the straight line in each simple cell is the inclination of the contour line corresponding to each simple cell. The same hyperplane has the same inclination. Add this correspondence to the adder
It is generated from the input polarity to 54 and 56.

In FIG. 9, the simple cells existing in the direction of the dark arrows of the simple cells 64 and 65 are connected to the adjacent simple cells via the bus 48 in polarities that mutually strengthen the amplitude, and weaken in the direction of the white arrow. Connected to adjacent simple cells via bus 48 in polarity. Therefore, simple cells 64 and 65
Shows simple cells forming the hyperplanes 66 and 68. Thus, in the simple cell, the angles of the corresponding contour lines of the simple cell are determined by exchanging the P and Q outputs of the adjacent simple cell groups in the arrow direction. The directions of the thin arrows do not give mutual interference in this embodiment. By changing the direction setting of these arrows for each hyperplane, the corresponding angle is determined.

The contour line distribution given by the distribution exchange circuit 10 is a set of mesh points, but since the simple cells excited by the D input are arranged in a certain direction in the portion where the contour line has a certain inclination, it corresponds to that inclination. On the generated hyperplane, the simple cell rows mutually strengthen their amplitudes, and even on the same hyperplane, the operation of more strongly suppressing the lateral direction occurs.

This is, so to speak, a survival competitive action between simple cells, and finally only the most predominant simple cell sequence survives on each hyperplane according to the angle of the contour line, and the output amplitude of other simple cell groups is suppressed. It will be.

The above operation is the interaction in the simple cell block 11A caused by the addition and subtraction 53 to 56. The other parts in the simple cell block 11A, that is, the inputs 50 and 51, the multiplier 59, and the pulsing circuit 60 in each simple cell will be described later.

FIG. 6A illustrates the correspondence between the simple cell block 11A, the SA conversion block 11C, and the angle cell block 11B. In the example shown, simple cell block 11A
The "Hyperplane" is composed of 4x6 simple cells, while the SA conversion block 11C has 2
It is integrated into the × 3 cell 41A. Therefore, each of the six cells 41A of the S-A conversion block 11C receives the output of all the corresponding 2 × 2 “hyper column” simple cells 41 of the simple cell block 11A, and outputs them all together. .

FIG. 7A is a circuit diagram showing an example of a unit cell of the SA conversion block 11C. If the unit cell 41D shown in FIG. 6A is taken as an example, the unit cell 41D is the simple cell block 1
Receives the output of all the simple cells of the corresponding hypercolumns a, b, c, d of 1A. The output of the simple cells belonging to the hyper columns a, b, c, d of each hyper plane is
Logical operation circuit that outputs (X ² + Y ² ) for inputs X and Y
Input to 42A. The output of the logical operation circuit 42A is input to the mutual subtractor 43A belonging to the same hyperplane. The output of each subtractor 43A is input to the adder 45A via the buffer 44A, and the output of the adder 45A is input to the function generator 46A. The function generator 46A outputs "1" or "0" to the angle cell block 11 according to the input.
Output to the corresponding cell of B.

Angle cell block 11B is a 2x3 simple cell 41B.
(In the following, in the case of an angle cell block, it is referred to as “angle cell” depending on the time). Angle cell 41B of each layer is S / A conversion block 11C
2 × 3 cells 41A, and the cells are excited by the corresponding cells 41A.

The internal circuit of the angle cell 41B is shown in FIG. 8A. As is clear from the comparison between FIGS. 8A and 8, the angle cell has almost the same structure as the simple cell. Therefore, the same parts are designated by the same reference numerals and the description thereof will be omitted. However, the terminal 52 connected to one input of the multiplier 59 is connected to the output of the adder 97 instead of via the input circuit 52A. The input of the adder 97 is output 10 for all points in the same item of the memory block described later.
4 is supplied.

Further, the angle cell is a block bus 48 through which output signals of all angle cells in the angle cell block pass.
Is bound to. And the angle cell 47 is input 49
And 50, the cell clock signal synthesized from the output of the clock oscillator 12 is received, and the output of the corresponding unit cell 41A of the SA conversion block 11C is input to the input 51. The angle cell that receives such a signal has adders 53 to 58, a multiplier 59, a pulsing circuit 60, and a unit oscillator 61, which are connected to each other as shown in the figure. The output signals 62 and 63 of 61 are coupled to the intra-block bus 48.

The adders 53 and 55 receive and add the P output and Q output of other simple cells in the same hyper column through the gain adjusting resistor groups having appropriate values, respectively. On the other hand, the adders 54 and 56 receive and add the P output and Q output of another simple cell in the same hyperplane through the gain adjusting resistor groups having appropriate values, respectively.

First, the other cells in the same hyper column are connected with polarities such that the amplitudes of P and Q of the unit oscillator become small. This is because each simple cell in the same hyper column corresponds to the direction of the line segment and thus weakens the output from each other.

The inside of the hyperplane will be described with reference to FIG. 9A.
In FIG. 9A, reference numerals 64A and 65A are angle cells, reference numerals 66A to 69A are top views of the hyperplane, and the inclination of the straight line in each angle cell indicates the contour line corresponding to each angle cell. The same hyperplane has the same inclination, but is divided into a pair of opposite directions. This correspondence is added to adders 54 and 56.
It is generated from the input polarity to. Then, as described above, the angle cell is composed of a pair of cells which are involved in the above-mentioned opposite directions. That is, in the angle cell 64A, one cell is involved in the direction of 0 ° and the other cell is involved in the direction of 180 °.

In FIG. 9A, the simple cells existing in the direction of the dark arrows of the simple cells 64A and 65A are connected to the adjacent simple cells via the bus 48 in polarities that mutually strengthen the amplitude, and weaken in the direction of the white arrow. Connected to adjacent simple cells via bus 48 in polarity. Therefore, the simple cells 64A and 65A represent the simple cells that form the hyperplanes 66A and 68A. Thus, as described above, the angle cells of the hyperplane are combined with the adjacent angle cells of the same hyperplane so as to weaken the excitation of the unit cells of the adjacent angle cells.

Next, the clock oscillator will be described. This portion is a reference excitation source for operating the simple cell block 11A, the angle cell block 1B, and the memory block 13.
FIG. 10 shows a circuit diagram of the clock oscillator 12.

As shown in FIG. 10, the clock oscillator 12 includes adders 77 to 84 connected as shown and a pair of unit oscillators 76A and 76B. The unit oscillator 76A oscillates at an angular frequency of ω / 2, and its P output and Q
The output is output as a two-phase clock to the memory block 13 via the outputs 85 and 86. Meanwhile, the unit oscillator
76B oscillates at each frequency of ω. Unit oscillator 7
Outputs 49 and 5 of the adders 77 to 84 which receive the P output and the Q output of 6A and 76B through the gain adjusting resistor groups of appropriate values, respectively.
Two of each of 0 and 87 to 92 is output as a two-phase clock common to the entire hyperplane. However, the outputs 49, 50, 87-92 from the unit oscillator 76A are fed to the angle cell block and the unit oscillator 76B
Outputs 49, 50, 87-92 from are supplied to the simple cell block.

Thus, when the excitation of the simple cell block 11A and the angle cell block 11B by the clock oscillator 12 is simulated, the pulse waveform shown in FIG. 10A is obtained. That is, a pulse having a phase corresponding to the direction or direction assigned to each cell is applied to each cell. In addition,
The analog waveform shown in FIG. 11A is an analog signal that matches the direction of each cell.

Then, when the phase of the clock from the clock oscillator 12 and the phase of the input analog signal to the cell of the simple cell block 11A or the angle cell block 11B match, the vibration of the nonlinear oscillator, that is, the damping oscillator of the cell whose phase matches, expands. Then, the phase is fixed. FIG. 11B schematically shows the relationship between such an input analog signal and a clock. In FIG. 11B, the lower stage shows the input to the cell, the upper stage shows the output of the cell, and the upper and lower stages show the voltage of the analog signal on the left vertical axis and the voltage of the clock signal on the right vertical axis. There is. That is, the vibration of the cells whose phases match each other survives, and the vibration pattern of the cells corresponding to the input pattern is formed.

Next, the memory block 13 will be described. The memory block 13 is also composed of a set of unit oscillators, and a vibration waveform corresponding to one figure pattern is generated by a group of a plurality of unit oscillators. This group is called a memory unit. All memory units are excited by the signals 85 and 86 that integrate the states in the simple cell block 11A and the angle cell block 11B, and the memory unit causes a competition such that only the vibration of the most suitable memory unit lasts. Do between each other. In the process of this competition, simple cell block 11A and angle cell block 11B
Excitation is also applied to the side, and the competing operation integrated with the memory block 13 is performed.

FIG. 11 is a configuration diagram showing an overall configuration of the memory block 13.

The memory block 13 has a plurality of memory items 71 connected to the simple cell block 11A and the angle cell block 11B via the data bus 70.
71 is connected to the memory gate 72. Further, the memory gate 72 is connected to a clock gate 73 corresponding to the memory clock generation circuit 14. And each memory item
71 has a plurality of memory points 93.

FIG. 12 is a circuit showing the structure of the memory points, and the output of each memory point is output to the adders 95 to 97 via the memory item internal bus 94, as shown in FIG. The outputs of the adders 95 and 96 are output to the divider 98.

Furthermore, each memory point 93 is a simple cell block 11
A signal that integrates the states inside A and angle cell block 11B
It has an input conversion circuit 99 for receiving 85 and 86. The input conversion circuit 99 is further supplied with the output 105, which is one of the outputs of the memory point 93. The input conversion circuit 99 has a plurality of pairs of outputs, and each pair of outputs is a memory oscillator.
Connected to 100. A pair of pulse generators 101 and 102 is connected to the output of each memory oscillator 100.
One of the pulse generators, the pulse generator 101,
Generates a simple cell pulse P _S and the other pulse generator 10
2 generates an angle cell pulse P _A. The output of the pulse generator 101 in the same memory point is input to the adder 101A, and the output of the pulse generator 102 in the same memory point is input to the adder 102A.

The outputs of the adders 101A and 102A are the point gate 10
Entered in 3. As will be described later in detail, the point gate 103 includes all simple cells of the simple cell block located at the same coordinate in the same mesh, that is, the hyperplane, unit cells of the A / S conversion block, and all angles of the angle cell block. It receives the output of the cell and further receives the feedback signal.

The point gate 103 has a pair of outputs 105 and 106, and via the in-memory item bus 94, an adder 95 and
It has been entered in 96. That is, the adder 95 is connected so as to receive the outputs 105 of all the memory points in the same item, and the adder 96 outputs the outputs of all the memory points in the same item.
Connected to receive 106. The output of the divider 98, which receives the outputs of the adders 95 and 96, feeds back a signal representing the average gate width within a point to the input of each point gate 103 within the same item, as described later.

Further, the point gate 103 has a third output 103A, and its output 103 and output 105 are input to the multiplier 103B. The output of the multiplier 103B is input as the output 104 to the adder 97 via the in-memory item bus 94. That is, the adder 97 is connected to receive the outputs 104 of all the memory points in the same item, and outputs a signal indicating the degree of coincidence between the pulse of the memory item and the pulse of the S-A conversion block. This signal is provided to the input terminal 52 of Figure 8A.

In addition, the output 52, as shown in FIG.
It is supplied to one input of the memory gate 103A provided for each. The memory gate 103A has a pair of outputs 105A.
And 106A, and are input to the adders 95A and 96A via the entire memory bus 94A. That is, the adder 95A has the output 105 of the memory gate 103A for each memory item.
Connected to receive A, adder 96A is also connected to receive output 106A of memory gate 103A for each memory item. The output 119A of the divider 98A that receives the outputs of the adders 95A and 96A, that is, the average gate width, is fed back to the other input of the memory gate 103A.

This memory gate 103A has an output 52A, as shown in FIG.
Has an integrator 120 for receiving the output of the adder 1
30 connected to one input. The output 119A of the divider 98A, that is, the average gate width is input to the other input of the adder 130. The output of the adder 130 is the multiplier 1
It is connected to one input of 31. The output of the multiplier 131 is connected to the input of the integrator 127. Its integrator 1
The output of 27 constitutes the gate width output 105A. Further, the output of the integrator 127 is directly connected to one input of the multiplier 131 and is connected to both inputs of the multiplier 128. The squared output from the multiplier 128 is connected to one input of the subtractor 129. A constant value is input to the other input of the subtractor 129. The outputs of the integrators 120 and 127 are input to the multiplier 132, and the output is output.
It is output as 106A.

Thus the competing circuit is configured and the input 52 is the average gate width.
If it is larger than 119A, the memory gate width output 105A is acceleratedly increased. On the contrary, if the input 52 is smaller than the average gate width 119A, the memory gate width output 105A is acceleratedly decreased. Such a memory gate 103A is provided in all memory items to form the memory gate 72.

In addition, the memory gate width output 105A for each memory item is
Input conversion circuit 114 for clock gate 73 as shown in FIG.
Entered in. The illustrated input conversion circuit 114 has a gain setting circuit 107 that receives the memory gate width output 105A,
The output of the gain setting circuit 107 is input to each of the conversion circuits 115 provided for each memory oscillator 100. That is, as many conversion circuits 115 as the number of the memory oscillators 100 are provided for each memory item.
Further, the memory clock 85 of the clock oscillator 12 and
86 is input to each conversion circuit 115.

Each conversion circuit 115 has a multiplier 108, connected as shown in the figure.
109, 110 and 111 and adders 112 and 113 are provided. With this configuration, the proportional operation is performed by the multipliers 108 to 111, and the memory clocks 85 and 86 are output at the gate width output 105A.
Is converted into a two-phase signal and output to the memory oscillator 100.

FIG. 16 is a diagram showing the configuration of the input conversion circuit 99 shown in FIG. As shown in FIG. 16, in the input conversion circuit 99, the output 105 of the point gate, all outputs of the simple cell block (P, Q) located at one set of coordinates via the bus 70, and the angle cell The output of the block is input.

The output of the simple cell block is input to the adder 99A for each same (P, Q), and the output of each adder 99A is input to one of the attached multipliers 99B. The output 105 of the point gate is supplied to the other input of each multiplier 99B.
The output of the full multiplier 99B is input to another adder 99C. The output of the adder 99C is connected to one input of the multiplier 99D, and the other input is connected to the output of the pulse generator 101 of the simple cell pulse P _S.

The output of the angle cell block is connected to one input of a multiplier 99E provided for each (P, Q), and the multiplier 99E
The other input of is supplied with the output 105 of the point gate. The output of the full multiplier 99E is input to the other adder 99F. The output of the adder 99F is connected to one input of the multiplier 99G, and the other input is
It is connected to the output of the pulse generator 102 of the angle cell pulse P _A.

The outputs of the multipliers 99D and 99G are connected to the input of the adder 99H. One of the pair of clocks is input to the other input of the adder 99H, and the other clock is directly input to the input A of the memory acylator 100. The output of the adder 99H is the input B of the memory agitator 100.
It is connected to the.

17A, 17B and 17C are interconnection diagrams of the memory oscillator 100. The memory oscillator is composed of a unit oscillator. FIG. 17A is a connection pattern for recognizing a rod, that is, a line, and is composed of a pair of unit oscillators. The B input of each unit oscillator receives the output of the point gate (or bus line) via the analog adder 100A, and further receives the Q output of the other unit oscillator via the inverter 100B. And the Q output of each unit oscillator is
This is a pulse output and is input to the pulse generator 101 for the simple cell pulse P _{S and} the pulse generator 102 for the angle cell pulse P _A.

The meaning of the connection relationships in FIG. 17A will be described with reference to FIG. In FIG. 18, black and white arrows facing each other are 180 degrees out of phase, and black and white circles facing each other are 180 degrees out of phase.

Assuming that the pattern shown in the upper part of the "spatial information" column of FIG. 18 is extracted into the angle cell block, the pattern shown in the upper part of the "temporal information" column, namely,
Seen on the time axis, cells with a phase shift of 180 degrees are excited.
Thus, when signals whose inputs are shifted by 180 degrees from each other are applied to the pair of unit oscillators shown in FIG. 17A, the Q output of each unit oscillator is inverted and applied to the B input of the other unit oscillator. Therefore, they excite each other so that their inputs increase, that is, their outputs increase. That is, this relationship is the relationship shown in the upper part of the column of “memorized information” in FIG. 18, and is the memory information of the pair of unit oscillators in the connection relationship of FIG. 17A.

FIG. 17B shows a connection pattern for recognizing a triangle, which is composed of three pairs of unit oscillators. The B input of each unit oscillator receives the output of the point gate (or the bus line) via the analog adder 100A, and further receives the Q output of the other unit oscillator of which the pair is lost via the inverter 100B. The B input of each unit oscillator is received via the Q output inverting analog adder 100C of the other two unit oscillators located on the same side. And the Q output of each unit oscillator is
This is a pulse output and is input to the pulse generator 101 for the simple cell pulse P _{S and} the pulse generator 102 for the angle cell pulse P _A.

The meaning of the connection relationships in FIG. 17B will be described with reference to FIG. It is assumed that the pattern shown in the lower part of the "spatial information" column in FIG. 18 is extracted in the angle cell block. That is, in the case of a triangle, there are three pairs of black and white arrows facing each other, and the total angle of each black arrow with respect to a certain reference line is 180 degrees. The total angle made to the line is 180 degrees. If such black and white arrows are represented on the time axis, the pattern becomes as shown in the lower part of the "time information" column. That is, on the time axis, the black and white circles facing each other are
If the phases are 180 degrees out of phase and you see only the black circles or the white circles, one black circle (or white circle) balances the composition of the remaining two black circles (or white circles).

The connection in Figure 17B shows exactly this relationship,
The three unit oscillators in the right half of FIG. 7B correspond to three black circles (or white circles), and the three unit oscillators in the left half correspond to three white circles (or black circles). That is, the paired unit oscillators are out of phase with each other.
When they receive signals that are 180 degrees apart, they excite each other. On the other hand, the B input of each of the three unit oscillators, the right half or the left half, undergoes the inversion of the synthesis of the Q outputs of the remaining two oscillators, so if the black circle (or white circle) is balanced, The three unit oscillators, the half or the left half, balance each other.

That is, this relationship is the relationship shown in the lower part of the "memory information" column of FIG. 18, and is the memory information of the three pairs of unit oscillators in the connection relationship of FIG. 17B.

FIG. 17C is a connection pattern for recognizing a quadrangle, which is composed of four pairs of unit oscillators. The B input of each unit oscillator receives the output of the point gate (or bus line) via the analog adder 100A, and further receives the Q output of the other paired unit oscillator via the inverter 100B. The B input of each unit oscillator receives the Q outputs of the other three unit oscillators located on the same side through the inverting analog adder 100C. The Q output of each unit oscillator is a pulse output, and the pulse generator of the simple cell P _S is used.
101 and the pulse generator 102 for the angle cell pulse P _A.

FIG. 19 is a circuit configuration diagram of the point gate 103 provided in each memory point shown in FIG. It should be noted that elements similar to those of the memory gate 103A are designated by the same reference numerals and the description thereof is omitted.

The point gater 103 outputs the outputs 117 of all the simple cells 41 belonging to the four hyper columns (for example, a, b, c, d) corresponding to the unit cell 41A (for example, 41) of the corresponding one SA conversion block 11C. It has an adder 117A receiving in parallel, and its output is connected to one input of the multiplier 117B. The other input of the multiplier 117B is connected to the unit cell 41A (for example, 4 units) of the corresponding SA conversion block 11C.
The output 116 of 1) is input. The output of the multiplier 117B is
It is connected to one input of the other multiplier 117C.
The point gate 103 is connected to the other input of the multiplier 117C.
The gate width output 105 of itself is fed back and input.
The output of the multiplier 117C is connected to one input of the subtractor 122, and a constant voltage is applied to the other input. The difference output is input to one input of the multiplier 125. Further, a subtractor 123 is provided in which the output 104 of the memory point 103 itself is fed back to one input, a constant voltage is applied to the other input, and the difference output thereof is the other output of the multiplier 125. Input has been entered. The output of the multiplier 125 is connected to one input of the adder 126.

Furthermore, the output 117A of the output of the corresponding angle cell of the angle cell block 11B is connected to one input of the subtractor 122A, and a constant voltage is applied to the other input. The difference output is input to one input of the multiplier 125A. Further, a subtracter 123A is provided in which the output 104 of the memory point 103 itself is fed back to one input, a constant voltage is applied to the other input, and the difference output is the other output of the multiplier 125A. Input has been entered. The output of the multiplier 125A is connected to the other input of the adder 126.

The output of the adder 126 is the output of the memory point 103 itself.
It is output as 104 and is also input to the integrator 120. The output of the integrator 120 is connected to one input of the adder 130. The other input of the adder 130 has a 12th
The average gate width output 119 of the divider 98 shown in the figure is input. The output of the adder 130 is connected to one input of the multiplier 131. The output of the multiplier 131 is the integrator 127.
Connected to the input of. The output of the integrator 127 forms the gate width output 105, is directly connected to one input of the multiplier 131, and is connected to both inputs of the multiplier 128. Then, the squared output from the multiplier 128 is the subtractor 129.
Connected to one input. A constant value is input to the other input of the subtractor 129. Also, the integrator 120
The outputs of 127 and 127 are input to the multiplier 132, and the output thereof is output as the output 106.

Thus, if a competing circuit is constructed and the output 104 of the adder 126 is larger than the average gate width 119, the point gate width output 105 is increased at an accelerating rate, and conversely if it is smaller than the average gate width 119A, the point gate width output 105 is increased. Operates so as to decrease at an accelerating rate.

Next, the result of observing the state of each part by the monitor 133 when the pattern recognition apparatus is operated is shown. FIG. 20 shows an example thereof. However, in the example shown in FIG. 20, the hamper plane of the simple cell block is 6 ×.
The hamper plane of the angle cell block is composed of 3 × 3 angle cells. Further, in the illustrated example, the excited angle cells are not connected to each other in all the virtual directions by connecting them to each other, and the oblique directions are not processed.

If a diagonal line pattern as shown in FIG. 20 (a) is input, simple cells are excited with the diagonal line pattern as shown in FIG. 20 (b). Note that FIG. 20 (b)
Shows a simple cell in which hyperplanes are overlapped, and the length and direction of the line in the grid indicate the degree and direction of excitation.

When such a pattern is supplied to the angle cell block, the angle cell is supplied as shown in FIG. 20 (c). Also in FIG. 20 (c), the angle cells are shown by overlapping the humper planes, and the extent and direction of excitation of the angle cells are shown by the length and direction of the arrow in the grid.

Of the memory items that receive the output of such an excited angle cell block and the simple cells of the simple cell block, each memory point gate of the memory item that matches the input pattern is shown in FIG. 20 (d), (e). ) And (f), the portion corresponding to the excitation angle cell is excited.

To encourage, a connected memory oscillator that corresponds to a hook-like pattern does not match the input pattern and each memory point gate of the memory item is somewhat open at the matching portion. However, the attached clock gate is closed as shown in FIG. 20 (h), the necessary excitation clock is not supplied, and the memory cell 2 is not excited as shown in FIG. 20 (g).

However, in memory oscillators that are connected corresponding to a bar-like pattern, which matches the input pattern, each memory point gate of the memory item is excited as shown in Figure 20 (k). At that time, the attached clock gate is also
Open as shown in Figure 20 (l) and supply the required excitation clock.

Thus, only the pattern in memory that matches the input pattern wins the competition and is therefore recognizable.

FIG. 21 is a waveform diagram of each part during the above pattern recognition operation.

The amplitudes of the clocks for both ω and ω / 2 increase with the passage of time from the start. Along with this, the simple cell block pulse is excited with a slight delay, and the angle cell block pulse is also excited with a further delay. In the angle cell block pulse, three large pulses appear consecutively, and the three pulses correspond to the three angle cells being excited.

And in the memory pulse (bar), with the passage of time,
The memory clock gate opens and the memory cell pulse appears. However, with the memory pulse (key-shaped), the memory clock gate closed and the memory cell pulse disappeared over time.

In the above embodiment, the clock gate and the memory gate are used. However, they can be omitted. In this case, the structure can be further simplified by omitting the point gate.

FIG. 22 is a diagram showing an operation example in this case.

If a triangular pattern as shown in FIG. 22 (a) is input, simple cells are excited with the triangular pattern as shown in FIG. 20 (b). Incidentally, FIG. 22 (b)
Shows a simple cell in which hyperplanes are overlapped, and the length and direction of the line in the grid indicate the degree and direction of excitation.

When such a pattern is supplied to the angle cell block, the angle cell is excited as shown in FIG. 22 (c). Also in FIG. 22 (c), the hyperplanes are overlapped to show an angle cell, and the extent and direction of excitation of the angle cell are shown by the length and direction of the arrow in the grid.

The phase relationship of the memory cells excited by receiving the output of the angle cell block thus excited is shown in Fig. 23 (a) for the memory oscillator corresponding to the rod-shaped pattern, and the memory corresponding to the triangle is shown. No. on the oscillator
It becomes like FIG.23 (b), and becomes like FIG.23 (c) in the memory oscillator corresponding to a square. In FIG. 23, numbers indicate memory oscillators, and their positions indicate phases. Thus, the memory oscillators corresponding to the triangle shown in FIG. 23 (b) are in a relationship of mutually strengthening the excitation.

FIG. 24 is a waveform diagram of each part during the above pattern recognition operation. In the memory pulse (triangle), the memory cell pulse increases with time. However, in the memory pulse (bar) and the memory pulse (square), the memory cell pulse disappeared over time.

FIG. 25 shows the case where a triangular pattern different from the example in FIG. 22 is input. If a triangular pattern as shown in FIG. 25 (a) is input, simple cells are excited with the triangular pattern as shown in FIG. 25 (b). When such a pattern is supplied to the angle cell block, the angle cell is excited as shown in FIG. 25 (c).

The phase relationship of the memory cells excited by receiving the output of the angle cell block thus excited is shown in FIG. 26 in the memory oscillator corresponding to the triangle.
In FIG. 26, as in FIG. 23, numbers indicate memory oscillators, and their positions indicate phases.

FIG. 27 is a waveform diagram of each part during the above pattern recognition operation. In the memory pulse (triangle), the memory cell pulse increases with time.

As is clear from the above description, when the memory oscillators connected corresponding to the respective patterns are input in the corresponding patterns, the memory oscillators that have a bar-shaped pattern are irrelevant regardless of position, size, rotation direction, similarity, etc. The concept can be recognized as a rod-shaped pattern and as a triangle as a triangle.

Therefore, various polygons can be recognized by connecting the memory oscillator to patterns corresponding to various polygons to be recognized.

EFFECTS OF THE INVENTION As is apparent from the above description, the pattern recognition device of the present invention performs the pattern processing by operating the analog operation circuits in completely parallel, so that there is no processing time delay associated with the sequential processing of the digital processor system. . Furthermore,
Since not only the existence of the decomposed line segment but also the position and the directional relationship of the end of the line segment (which also includes the borrow angle between the lines) are recognized, more accurate recognition can be performed.

Further, for an ambiguous figure or a figure that has no data to be referenced in the memory, the memory and the simple cell section can automatically change their states via a clock and output some interpretation result.

Since all unit oscillators of the same shape are used for creating the vibration waveform, it is possible to increase the reliability of circuit element failure. The fully parallel operation described above also contributes to reducing the probability that a failure will significantly affect the overall processing result.

In this embodiment, the circuit structure of the unit oscillator is a van der pole whose basic vibration characteristic is stable.
Since it uses a shaped circuit, it is highly reliable in terms of waveform stability.
However, it goes without saying that another non-linear circuit may be used as the unit oscillator.

When embodying the present pattern recognition apparatus, in addition to the analog circuit system as in the present embodiment, a digital circuit capable of calculating non-linear vibration is used, and any other mechanical element or chemical that can generate non-linear vibration. Any of the reactive elements may be used.

The above embodiment is an example in which the present invention is applied to an image pattern recognition device, but the pattern recognition device according to the present invention is not limited to image input of figures, characters, etc., but also various other events that change in time series. It is also applicable to a device for extracting features such as. For example, in the case of sound, it can be recognized by Fourier transforming the frequency of the sound and converting each component into a two-dimensional pattern by fitting each component into each bit of a given two-dimensional bit pattern. . Therefore, the present invention can realize a general-purpose pattern recognition device.

[Brief description of drawings]

FIG. 1 is a functional block diagram illustrating the basic configuration of the pattern recognition device according to the present invention. FIG. 1A is a diagram illustrating the directivity of a simple cell in the first block of the information integration unit of the pattern recognition apparatus in FIG. FIG. 1B is a diagram illustrating the directivity of a simple cell of the second block of the information integration unit of the pattern recognition device of FIG. FIG. 2 is a block diagram showing the basic configuration of the pattern recognition device according to the present invention. FIG. 3 is an illustrative view showing a relationship between an object to be recognized, a pattern before being processed by the pattern preprocessing unit shown in FIG. 1, and a simple cell in the first block of the information integrating unit. FIG. 4 is a circuit diagram showing a configuration example of the unit oscillator. FIG. 5 is an explanatory diagram of blocks displaying the unit oscillator. FIG. 6 is a diagram illustrating the correspondence with the inclination distribution plane of the simple cell block. FIG. 6A illustrates the correspondence between the simple cell block 11A, the SA conversion block 11C, and the angle cell block 11B. FIG. 7 is a diagram illustrating a connection relationship of unit oscillators in a hyper column of a simple cell block. FIG. 7A is a circuit diagram showing an example of a unit cell of the SA conversion block. FIG. 8 is a block circuit diagram showing the circuit configuration of a simple cell. FIG. 8A is a block circuit diagram showing a circuit configuration of an angle cell. FIG. 9 is a diagram illustrating the directivity of each simple cell in the simple cell block, the directivity of each simple cell in the same hyperplane, and the connection relationship between adjacent cells. FIG. 9A is a diagram illustrating the directionality of each angle cell of the angle cell block, the directionality of each angle cell in the same hyperplane, and the connection relationship between adjacent cells. FIG. 10 shows a circuit diagram of the clock oscillator. FIG. 10A is a diagram schematically showing excitation by pulses of different phases by the clock oscillator. FIG. 10B is a diagram simulating the excitation when the phases of the clock and the analog signal match. FIG. 11 is a configuration diagram showing an overall configuration of the memory block. FIG. 12 is a circuit diagram showing the structure of a memory point. FIG. 13 is a circuit diagram of a circuit for receiving the output of the memory item. FIG. 14 is a circuit diagram showing the structure of the memory gate. FIG. 15 is a circuit diagram of a clock gate input conversion circuit. FIG. 16 is a circuit diagram showing a configuration of the input conversion circuit shown in FIG. FIG. 17A is a circuit diagram showing the configuration of the memory oscillator, and FIGS. 17B and 17C are circuit diagrams. FIG. 18 is a diagram illustrating the connection relationship between the pattern and the memory oscillator. FIG. 19 is a circuit configuration diagram of a point gate provided in each memory point shown in FIG. FIG. 20 is an excitation pattern diagram illustrating an operation example of the first embodiment of the pattern recognition apparatus according to the present invention. FIG. 21 is a waveform diagram of each part during the pattern recognition operation shown in FIG. 22 to 27 are an excitation pattern diagram and a waveform diagram of each part illustrating an operation example of the second embodiment of the pattern recognition apparatus according to the present invention. FIG. 28 is a diagram illustrating an example of a concept that can be recognized by the pattern recognition device according to the present invention. [Main reference numbers] 1 …… Pattern preprocessing unit 2 …… Information integration unit 2A …… Simple cell block 2B …… Angle cell block 3 …… Memory unit 8 …… Camera 9 …… Contour line extraction circuit 10 …… Distribution conversion circuit 11 …… Simple cell block 12 …… Clock oscillator 13 …… Memory block

Claims (1)

[Claims] 1. A pre-processing unit for converting an input pattern into a two-dimensional bit pattern, and a multi-layered structure, each layer being composed of a plurality of non-linear oscillators arranged in a two-dimensional matrix. The linear oscillator is connected to the pre-processing unit so as to be excited by the corresponding bits of the two-dimensional bit pattern of the pre-processing unit, and is arranged in a predetermined direction within a plane of a two-dimensional matrix different for each layer. Only to strengthen the mutual excitation,
The non-linear oscillators, which are adjacent to each other in the plane direction of the two-dimensional matrix and are connected to each other and correspond to the continuous line segments of the two-dimensional bit pattern in each layer and have the same direction, are selectively excited. And a first cell block having the above-mentioned structure, each layer having a multi-layer structure, and each layer being composed of a plurality of non-linear oscillators arranged in a two-dimensional matrix. Two-dimensionally connected to the first cell block so as to be excited by corresponding bits of a pattern, and two-dimensionally controlled to mutually excite only in a predetermined direction within a plane of a two-dimensional matrix which is different for each layer. The non-linear oscillators that are adjacent to each other in the plane direction of the matrix and are connected to each other and that correspond to the ends of the continuous line segments of the two-dimensional bit pattern for each layer are selectively excited. The second cell block is configured to be shaken, and a plurality of non-linear oscillators connected in pairs so that the output of the other is inverted and input to one of the inputs, The plurality of nonlinear oscillators are connected to the first and second cell blocks, are selectively excited according to the excited nonlinear oscillators of the first and second cell blocks, and The excitations of the plurality of non-linear oscillators are fed back to the corresponding non-linear oscillators of the first and second cell blocks, and the plurality of non-linear oscillators recognize a specific pattern. And a memory unit that is selectively excited in accordance with the exciting nonlinear oscillators of the first and second cell blocks, and the first and second cell blocks. Excitation pattern of nonlinear oscillator Corresponding to a pattern recognition apparatus characterized by said non-linear oscillator in the in the memory unit that is connected with the connection pattern for recognizing a specific pattern is selectively excited.