JPH0669081B2 - Method of manufacturing semiconductor memory - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor memory in which a soft error does not occur.

[Prior Art] FIG. 3 is a cross-sectional structural view of an essential part showing an example of a conventional 1-transistor / 1-capacitor type semiconductor memory. In the figure, (1) is a silicon semiconductor substrate, (2) is an element isolation insulating film, (3) is a capacitor insulating film such as a silicon oxide film, (4) is a capacitor electrode such as polycrystalline silicon, etc. (5) is a MOS structure made of, for example, a thin oxide film and polycrystalline silicon, and (6) is an impurity diffusion layer. In this semiconductor memory, a capacitor insulating film (3) forms a memory capacitor having a capacitor electrode (4) as an electrode, and a signal charge corresponding to "1" or "0" is stored in this memory capacitor. Further, the MOS structure (5) uses the impurity diffusion layer (6) as a source electrode and a drain electrode.
A MOS transistor is formed, and the signal charge is read from or written in the memory capacitor by the switching operation of the MOS transistor.

The semiconductor memory having the above structure has a U or Th content that is contained in a very small amount in LSI materials such as packages and wiring.
It is known that the so-called soft error occurs in which the polarity of the signal charge of the capacitance is inverted by the charge generated by the α-ray generated from the radioactive substance such as the incident on the silicon semiconductor substrate (1). FIG. 4 is a diagram schematically showing the principle of occurrence of such a soft error. When the α-ray particles (α) enter the P-type silicon semiconductor substrate (1) having a thickness of about 20 μm, about 10 ⁶ electron-hole pairs are generated. The holes generated by the incidence of α-ray particles penetrate deeply into the substrate (1) because the P-type silicon semiconductor substrate (1) is held at a negative potential, but most of the electrons are on the surface of the substrate (1). Side diffused, part of which is the insulating film for capacitors (3)
Reach the depletion layer region (3a). When the signal charge corresponding to “1”, that is, positive charge is accumulated in the depletion layer region (3a), when the number of electrons reaching the depletion layer region (3a) is large, The signal charge is inverted from "1" to "0", resulting in a soft error.

[Problems to be Solved by the Invention] There are various means for preventing the occurrence of the soft error. FIG. 5 is a sectional view of a semiconductor memory in which a soft error occurrence countermeasure is taken by a conventional method.
Reference numeral (7) is an N ⁺ buried diffusion layer buried between the silicon semiconductor substrates (1) and (1 ') below the capacitor insulating film (3). By fixing the N ⁺ buried diffusion layer (7) to a positive potential, electrons generated in the silicon semiconductor substrate (1) can be trapped. In this case, there is a problem that the concentration of the N ⁺ buried diffusion layer (7), the control and the N ⁺ buried diffusion layer (7) electrically connected, such as difficulty in the manufacturing process to such thickness is added.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor memory that prevents the occurrence of soft errors.

[Means for Solving the Problems] In the method for manufacturing a semiconductor memory according to the present invention, a first isolation insulating film is selectively formed on a silicon side conductor substrate doped with a predetermined impurity, and the first isolation insulating film is formed. A second isolation insulating film is selectively formed on the substrate including the isolation insulating film, and an epitaxial growth layer doped with the same kind of impurities as the substrate is formed on the substrate and the second isolation insulating film. Forming a memory capacitor by selectively forming a capacitor insulating film on the layer, and then forming a capacitor electrode on the capacitor insulating film, and forming an impurity diffusion layer and a gate electrode on the epitaxial growth layer. Thus, a switching MOS transistor for reading and writing the signal charge of the memory capacitor is formed.

[Operation] In the semiconductor memory having the above structure, even if electrons are generated in the semiconductor substrate due to the incidence of α rays,
The electrons are prevented from reaching the depletion layer region of the memory capacitor by being blocked by the second isolation insulating film.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view of an essential part of a semiconductor memory manufactured according to the present invention. In the figure, (1) is a silicon semiconductor substrate, (3) is a capacitor insulating film, (4) is a capacitor electrode, (5) is a MOS structure, (6) is an impurity diffusion layer, and (8) is a first layer. An isolation insulating film, (9) is a second insulating film, and (10) is an epitaxial layer of silicon mixed with the same impurities as the silicon semiconductor substrate (1).

The capacitor insulating film (3), the capacitor electrode (4), the MOS structure (5), and the impurity diffusion layer (6) use the first isolation insulating film (8) as an element isolation insulating film. 1) There shall be a plurality above.

In this semiconductor memory, a capacitor insulating film (3) forms a memory capacitor having a capacitor electrode (4) as an electrode, and a signal charge corresponding to "1" or "0" is stored in this memory capacitor. Further, the MOS structure (5) is a MOS having the impurity diffusion layer (6) as a source electrode and a drain electrode.
A transistor is formed, and the signal charge is read from or written in the memory capacitor by the switching operation of the MOS transistor.

The first isolation insulating film (8) is formed of, for example, a silicon oxide film, and electrically insulates a plurality of memory capacitors formed on the semiconductor substrate (1). The second isolation insulating film (9) is formed of, for example, a silicon oxide film or a silicon nitride film, and electrically connects the memory capacitor formed on the semiconductor substrate (1) and the semiconductor substrate (1). Electrically insulate.

Next, FIG. 2 shows the manufacturing process of the present invention. First, a first isolation insulating film (8) is selectively formed on a silicon semiconductor substrate (1) doped with a predetermined impurity (see FIG. 2A), and then on the silicon semiconductor substrate (1). Then, a second isolation insulating film (9) is selectively formed (see FIG. 2B).

Next, on the semiconductor substrate (1) on which the first isolation insulating film (8) and the second isolation insulating film (9) are formed by the epitaxial growth method in which the same kind of impurities as those of the silicon semiconductor substrate (1) are doped, The epitaxial growth layer (10) is formed so as to have almost the same height as the raised portion of the second isolation insulating film (9) (see FIG. 2 (c)).

Next, a memory capacitor is formed by forming a capacitor insulating film (3) and a capacitor electrode (4) on the epitaxial growth layer (10), and further a MOS structure (5) and an impurity diffusion layer (6) are formed. Thus, a MOS transistor is formed (see FIG. 2 (d)).

In the semiconductor memory manufactured by the above-mentioned method, even if electrons are generated in the semiconductor substrate (1) due to the incidence of α rays into the semiconductor substrate (1), the electrons are generated in the second isolation insulating film (9). Is completely shut off, and the depletion layer region of the memory capacitor is never reached.

The present invention forms a capacitor on the entire surface of the epitaxial growth layer, connects the epitaxial growth layer and the silicon semiconductor substrate, and the epitaxial growth layer is surrounded only as a part of the semiconductor substrate (meaning that it is not used as an electrode such as a cell plate). The semiconductor substrate and the epitaxial growth layer maintain the same potential. Therefore, the concentration of the epitaxial growth layer is ~ 10 ¹⁶ / cm ³ which is usually used as the substrate.
It is _{sufficient that} the control of V _th of the MOS transistor formed on the upper side and the improvement of punch-through resistance by the back bias are easily achieved.

Although the present embodiment has been described with respect to the one-transistor / one-capacitor type semiconductor memory, it does not prevent application to other types of semiconductor memories.

As described above, according to the present invention, since the memory capacitor is separated from the semiconductor substrate by the second isolation insulating film, electrons generated in the semiconductor substrate can reach the memory capacitor. There is no soft error.

In addition to the simple increase in the capacitance of the capacitor and the blocking of α-rays, it is possible to achieve not only the improvement of various characteristics such as the MOS transistor in the dynamic RAM and the blocking of α-rays, but also the remarkable operational effects. is there.

[Brief description of drawings]

FIG. 1 is a sectional structure view of a main part of a semiconductor memory manufactured according to the present invention, FIG. 2 is a process diagram of an embodiment of a method for manufacturing a semiconductor memory according to the present invention, and FIG. 3 is a main part of a conventional semiconductor memory. Cross-sectional structure diagram, Fig. 4 is a principle diagram of soft error occurrence,
FIG. 5 is a sectional view of a semiconductor memory in which a soft error occurrence countermeasure is taken by a conventional method. In the figure, 1 is a silicon semiconductor substrate, 3 is a capacitor insulating film, 4 is a capacitor electrode, 5 is a MOS structure, 6 is an impurity diffusion layer, 8 is a first isolation insulating film, and 9 is a second isolation insulating film. , 10 are epitaxial growth layers. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Yoneda 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSE Research Institute (72) Inventor Masahiro Hatanaka 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. LSI Research Institute (72) Inventor Toshiaki Ogawa 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Kiyoki Kobayashi Mizuhara, Itami City, Hyogo Prefecture 4 chome 1 Mitsubishi Electric Co., Ltd. LSI Research Institute (56) Reference JP-A-56-107571 (JP, A) JP-A-59-110154 (JP, A) JP-A-58-212160 (JP , A) JP-A-56-62333 (JP, A)

Claims (3)

[Claims] 1. A first isolation insulating film is selectively formed on a silicon semiconductor substrate doped with a predetermined impurity, and a second isolation insulating film is formed on the substrate including the first isolation insulating film. After being selectively formed, an epitaxial growth layer doped with the same kind of impurities as that of the substrate is formed on the substrate and the second isolation insulating film, and an insulating film for a capacitor is selectively formed on the epitaxial growth layer. A memory MOS capacitor is formed by forming a capacitor electrode on the capacitor insulating film, and an impurity diffusion layer and a gate electrode are formed in the epitaxial growth layer to read and write the signal charge of the memory capacitor. A method of manufacturing a semiconductor memory, comprising: 2. The method of manufacturing a semiconductor memory according to claim 1, wherein the first isolation insulating film and the second isolation insulating film are formed of silicon oxide. 3. The manufacturing of a semiconductor memory according to claim 1, wherein the first isolation insulating film is made of silicon oxide, and the second isolation insulating film is made of silicon nitride. Method.