JPH0669092B2 - Method of manufacturing gate turn-off thyristor - Google Patents

Description

Detailed Description of the Invention TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a gate turn-off thyristor (hereinafter abbreviated as GTO thyristor).

[Prior art and its problems]

As an example, a partial cross-sectional view of a general GTO thyristor is shown in FIG. The GTO thyristor element body 1 having a PNPN four-layer structure is formed, for example, by adding impurities to an N-type silicon substrate, and has a P-type emitter layer 11, an N-type base layer 12, a P-type base layer 13, and an N-type base layer 13. The mold emitter layer 14 is connected to the support plate 3 via the brazing material 2.
The main surface on the side opposite to the support plate 3 is divided into a plurality of segments by forming a concave portion 6 which penetrates the N-type emitter layer 14 and reaches the P-type base layer 13 in a mesh shape by etching with acid or the like. There is. A gate electrode film 42 is provided on the P-type base layer 13 exposed in the recess 6, and a cathode electrode film 41 is provided on the N-type emitter layer 14 of the segment. The oxide film 5 serves to protect the PN junction between the N-type emitter layer 14 and the P-type base layer 13 exposed on the surface of the silicon body 1. The characteristic of the GTO thyristor having such a structure is that a current flowing from the support plate 3 toward the cathode electrode film 41 at the time of energization is applied to the gate electrode film 42 with a negative voltage with respect to the cathode electrode film 41. The point is that it is led out to the gate electrode film 42 to be blocked. This current blocking ability is mainly obtained from immediately below the gate electrode film 42 to the segment N-type emitter layer 14
Depends on the magnitude of the gate impedance 15, which is the electrical resistance of the P-type base layer 13 in the current path reaching directly below the center,
A smaller GTO thyristor with a gate impedance of 15 has a larger current interruption capability. Next, an example of a method of manufacturing the GTO thyristor element body 1 will be described with reference to FIGS. 3 and 4. In the example shown in FIG. 3, for example, boron is added to an N-type silicon substrate by an ion implantation method, and a P-type base layer 13 and a P-type emitter layer 11 (not shown) are formed by thermal diffusion.
It becomes the mold base layer 12 (FIG. 3 (a)). Then, for example, phosphorus is added from the upper surface of the silicon substrate by the ion implantation method, and the N type emitter layer 14 is formed by thermal diffusion (FIG. 3B). Further, an oxide film is formed, and an oxide film mask 51 for processing the recess is formed by photoetching (FIG. 3 (c)). Then, for example, the recess 6 is processed (hereinafter referred to as gate etching down) with a mixed solution of hydrofluoric acid and nitric acid (FIG. 3 (d)). Then, after removing the oxide film mask 51, a second dioxide film mask 5 for protecting the PN junction is formed by oxidation and photoetching (FIG. 3 (e)). Then, a gate electrode film 42 and a cathode electrode film 41 are provided by Al vapor deposition and photoetching (FIG. 3 (f)). GTO made from the element body 1 obtained by the above manufacturing process
The thyristor is hereinafter referred to as the first type GTO thyristor. Then, the GTO thyristor manufactured by using the manufacturing process as shown in FIG. 4 is hereinafter referred to as a second type GTO thyristor. The second type is shown in FIG.
After the same process as the manufacturing process of the first type shown in (d), the oxide film mask 51 is removed, and a second dioxide film mask 52 is provided by oxidation and photoetching (FIG. 3A). Next, the gate contact P layer 16 is formed by, for example, ion implantation of boron and thermal diffusion (FIG. 4 (b)). Further, a contact hole 40 for the cathode electrode film is provided by photo etching (FIG. 4 (c)), and a gate electrode film 42 and a cathode electrode film 41 are formed by Al vapor deposition and photo etching (FIG. 4 (d)). . Of the above two types of GTO thyristors, the first type has the advantage that it can be manufactured at low cost with a small number of steps, but due to gate etching down, a high concentration (low electrical resistance) of the P-type base layer 13 is obtained. There is a drawback that the gate ions are high and the current blocking ability is low because the portions are removed. The second type GTO thyristor has a low gate impedance due to the presence of the gate P layer 16 and can have a high current blocking capability, but it has a high cost due to the large number of steps, and the displacement of the second film mask 52 is also great. Because of the variation in gate impedance,
There is a problem that it is difficult to obtain a sufficient current interruption capability. Further, in common to both types, when there is a pinhole in the oxide film mask 51, the cathode electrode film 41 and the P-type base layer 13 are short-circuited in the segment under the mask, resulting in a defective segment, resulting in a yield. There was a problem of lowering.

[Object of the Invention]

An object of the present invention is to provide a GTO thyristor with a low gate impedance, a small variation in the gate impedance, and an extremely high current interruption capability at a low cost and with a high yield.
It is to provide a method for manufacturing an O thyristor.

[Points of the Invention]

The present invention has a base layer of the second conductivity type on one surface side of a base layer of the first conductivity type, an emitter layer of the first conductivity type, and an emitter layer of the second conductivity type on the other surface side. In the production of a GTO thyristor in which a recess reaching the base layer of the second conductivity type is formed, and the exposed portion of the junction between the base layer of the second conductivity type and the emitter layer of the first conductivity type is covered with an insulating film, After depositing an insulating film on the part covering the exposed part of the junction formed by forming the emitter layer of the first conductivity type on the one surface in advance, by etching using the insulating film as the peripheral part of the mask. After forming a recess and further forming a second conductivity type base layer by introducing impurities from one surface, impurities are introduced into the segment portion surrounded by the recess using the insulating film as a mask to form a first conductivity type emitter layer. Is formed. As a result, both the gate etching down and the impurity introduction on the one surface side are performed by self-alignment using the insulating film used as the PN junction protective film as a mask, and the number of steps can be reduced. Impurities are introduced into the entire bottom surface of the formed recess after the gate etching down, so that the gate impedance can be greatly reduced, the bias in the gate impedance can be eliminated, and there is no short circuit due to the pinhole in the mask. The above-mentioned object is achieved.

Examples of the invention

An embodiment of the present invention will be described below with reference to FIG. 1 in which the same parts as those in FIGS. FIG. 1A shows a state in which an oxide film mask 5 is formed by photoetching after the surface of the N-type silicon substrate 10 is thermally oxidized. Then, a photosensitive polyimide is further applied and a polyimide mask 7 is provided by photoetching. With the oxide film 5 and the polyimide mask 7 as a mask, the silicon substrate 10 is gate-etched down with a mixed solution of, for example, hydrofluoric acid and nitric acid to form a recess. FIG. 1 (b) shows a state in which 6 is formed. At this time, the positional deviation tolerance in forming the polyimide mask 7 is sufficiently large because the width of the oxide film mask 5 is several tens of μm, and the recess 6
Since it only has to serve to form a step between the gate electrode surface and the cathode electrode surface shown in FIG. 1 (f), compared to the case of the GTO thyristor shown in FIGS. 3 and 4. The tolerance of depth becomes extremely large, and the manufacturing yield is greatly improved. Even if the silicon substrate 10 immediately below has pinholes in the oxide film mask 5 and the polyimide mask 7 and thus has etching holes, the P-type base layer 13 and the N-type emitter layer 14 are not formed after that. Since this is performed, the short circuit between the P-type base layer and the cathode electrode film due to the etching hole does not occur, which also greatly improves the manufacturing yield. Next, the polyimide mask 7 shown in FIG.
Is removed, and using the oxide film 5 as a mask, for example, by ion-implantation thermal diffusion of boron, as shown in FIG.
The mold base layer 13 is formed. In this case, since the concentration near the surface of the P base layer 13 exposed in the recess 6 becomes extremely high, a much lower gate impedance can be obtained in approximately the same number of steps as in the case of the first type GTO thyristor. In addition, a lower gate impedance can be obtained in a far smaller number of steps as compared with the case of the second type GTO thyristor, and the gate contact layer due to the shift of the second dioxide film 5 shown in FIG. 4 (b). It is possible to completely prevent the deviation or variation of the gate impedance due to the position shift of 16. Next, a photoresist is applied to the silicon substrate 10 of FIG. 1 (c), a resist mask 8 is formed by photoetching, and then an oxide film mask 5 is formed.
With the resist mask 8 as a mask, for example, phosphorus ions 9
Is performed (FIG. 1 (d)). Then, after removing the resist mask 8, the N-type emitter layer is formed by thermal diffusion.
The state in which 14 is formed is shown in FIG. According to this method, since the recess 6 and the N-type emitter layer 14 are both formed using the oxide film 5 as a mask, the relative positions of the recess 6 or the segment portion surrounded by the recess and the emitter layer 14 are always symmetrical and uniform. Therefore, it is possible to prevent the bias and the variation of the gate impedance, and the step of attaching an oxide film is omitted. Finally, FIG. 4 (f) shows a state in which the gate electrode film 42 and the cathode electrode film 41 are simultaneously formed on the silicon substrate 10 of FIG. 1 (e) by Al vapor deposition and photoetching. In this step, the oxide film 5 used as a mask in FIGS. 1A to 1F is used as it is as a surface protective film for the PN junction at the boundary between the N-type emitter layer 14 and the P-type base layer 13. We are reducing the number of processes. Although not mentioned in the above description, the P-type emitter layer 11 provided on the side of the N-type base layer 12 opposite to the P-type base layer 13 is provided.
May be formed by implanting boron ions from the opposite surface at the same time as the step of forming the P-type base layer 13 in FIG. 1 (c). Alternatively, it may be formed by an impurity diffusion method in another step before that. Good. Needless to say, the GTO thyristor in which the gate electrode is provided in the N-type base layer can be implemented in the same manner as the GTO thyristor in which the gate electrode is provided in the P-type base layer.

【The invention's effect】

According to the present invention, since the base layer on which the gate electrode of the GTO thyristor is deposited is formed after the gate etching down, even if there is a pinhole in the mask during the gate etching down, a short circuit defect does not occur in the segment portion, and the gate The tolerance of the depth of etching down becomes large, the manufacturing yield is improved, and the gate impedance is lowered. In addition, the gate etching down, the base layer on which the gate electrode is deposited, and the emitter layer on the base layer are formed by self-alignment, which can reduce the number of processes and prevent the deviation and variation of the gate impedance. Since the oxide film mask used is used as it is as a PN junction protective film between the base and emitter layers, the number of steps is also reduced in that respect, yield improvement and cost reduction due to the decrease in the number of steps and the improvement of current blocking capability can be achieved. The effect obtained is extremely large.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an essential part showing a manufacturing process of a GTO thyristor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of an essential part of the structure of a general GTO thyristor, and FIGS. GT
FIG. 6 is a cross-sectional view of a main part showing an example of a manufacturing process of an O thyristor. 1: GTO thyristor body, 10: N type silicon substrate, 12: N type base layer, 13: P type base layer, 14: N type emitter layer, 41: Cathode electrode, 42: Gate electrode, 5: Oxide film, 6: concave, 7: polyimide mask, 8: resist mask, 9: phosphorus ion.

Claims (1)

[Claims] 1. A first conductivity type base layer having a second conductivity type base layer on one surface side, a first conductivity type emitter layer, and a second conductivity type emitter layer on the other surface side. When manufacturing a product in which a recess reaching from the surface to the base layer of the second conductivity type is formed and the exposed portion of the junction between the base layer of the second conductivity type and the emitter layer of the first conductivity type is covered with an insulating film. After depositing an insulating film on a portion covering the exposed portion of the junction formed by forming the emitter layer of the first conductivity type on the one surface in advance, etching is performed by using the insulating film as a peripheral portion of the mask. To form a concave portion, and further to form a second conductivity type base layer by introducing impurities from the one surface, and then introducing impurities into the segment portion surrounded by the concave portion using the insulating film as a mask to form a first conductive film. Shaped emitter layer is formed. Method of manufacturing the over door turn-off thyristors.