JPH0669099B2 - MIS type semiconductor device - Google Patents
MIS type semiconductor deviceInfo
- Publication number
- JPH0669099B2 JPH0669099B2 JP59269977A JP26997784A JPH0669099B2 JP H0669099 B2 JPH0669099 B2 JP H0669099B2 JP 59269977 A JP59269977 A JP 59269977A JP 26997784 A JP26997784 A JP 26997784A JP H0669099 B2 JPH0669099 B2 JP H0669099B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- insulating film
- silicon oxide
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Landscapes
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明はMIS型半導体装置に関し、特にE2PROM（Electri
c Erasable ROM）に係わる。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a MIS type semiconductor device, and in particular to an E 2 PROM (Electri
c Erasable ROM).
周知の如く、例えばE2PROMにおいては浮遊ゲート絶縁膜
が用いられているが、該絶縁膜は蓄積した電荷を逃がし
て電気的に消去した内容を書込むためその一部を他の部
分より薄い領域を有している。As is well known, a floating gate insulating film is used in, for example, an E 2 PROM, but the insulating film escapes accumulated charges to write electrically erased contents, so that a part of the insulating film is thinner than other parts. Has an area.
従来、E2PROMは、例えば第３図（ａ）〜（ｈ）に示す如
く製造されている。Conventionally, E 2 PROMs have been manufactured as shown in, for example, FIGS.
まず、半導体基板１の表面にフィールド酸化膜２を形成
する（第３図（ａ）図示）。つづいて、このフィールド
酸化膜２に囲まれた基板１の表面に熱酸化により厚さ50
0〜600Åの浮遊ゲート絶縁膜３を形成する（第３図
（ｂ）図示）。次いで、全面に、トンネル酸化膜形成形
成予定部に対応する部分が開口したレジスト４を形成す
る（第３図（ｃ）図示）。更に、このレジスト４をマス
クとして前記絶縁膜３を選択的にエッチング除去した
後、レジスト４を剥離する（第３図（ｄ）図示）。First, the field oxide film 2 is formed on the surface of the semiconductor substrate 1 (shown in FIG. 3A). Subsequently, the surface of the substrate 1 surrounded by the field oxide film 2 is thermally oxidized to a thickness of 50.
A floating gate insulating film 3 having a thickness of 0 to 600 Å is formed (FIG. 3B). Next, a resist 4 having an opening at a portion corresponding to a portion where a tunnel oxide film is to be formed is formed on the entire surface (shown in FIG. 3C). Further, the insulating film 3 is selectively removed by etching using the resist 4 as a mask, and then the resist 4 is peeled off (shown in FIG. 3 (d)).
次に、露出した基板１の表面に厚さ100〜200Åのトンネ
ル酸化膜５を形成する（第３図（ｅ）図示）。つづい
て、全面に多結晶シリコン層６を形成し（第３図（ｆ）
図示）、パターニングして多結晶シリコンからなる浮遊
ゲート電極７を形成する。次いで、この浮遊ゲート電極
７をマスクとして基板１に不純物をイオン注入し、拡散
層（図示せず）を形成する（第３図（ｇ）図示）。更
に、全面に層間絶縁膜８を形成した後、多結晶シリコン
からなる制御ゲート電極９、保護膜10を形成して、E2PR
OMを製造する（第３図（ｈ）図示）。Next, a tunnel oxide film 5 having a thickness of 100 to 200Å is formed on the exposed surface of the substrate 1 (shown in FIG. 3 (e)). Then, a polycrystalline silicon layer 6 is formed on the entire surface (see FIG. 3 (f)).
Then, the floating gate electrode 7 made of polycrystalline silicon is formed by patterning. Then, using the floating gate electrode 7 as a mask, impurities are ion-implanted into the substrate 1 to form a diffusion layer (not shown) (shown in FIG. 3 (g)). Furthermore, after forming an interlayer insulating film 8 on the entire surface, a control gate electrode 9 and a protective film 10 made of polycrystalline silicon are formed, and E 2 PR
OM is manufactured (shown in FIG. 3 (h)).
しかしながら、従来技術によれば、次に示す問題点を有
する。However, the conventional technique has the following problems.
．トンネル酸化膜５を、浮遊ゲート絶縁膜３を選択的
にエッチング除去した後再酸化することにより形成する
ため、浮遊ゲート酸化膜領域は酸化工程を２度受けるこ
とになり、膜厚の制御性が低下する。． Since the tunnel oxide film 5 is formed by selectively removing the floating gate insulating film 3 by etching and then re-oxidizing the floating gate insulating film 3, the floating gate oxide film region is subjected to the oxidation process twice, and thus the controllability of the film thickness is reduced. descend.
．通常基板表面が露出する前処理では、基板表面に形
成されるNative Oxideと呼ばれる不純物を多く含む数十
Å以下の酸化膜をエッチングしてから酸化する。しか
し、この工程で厚い方の酸化膜が均一にエッチングされ
ず、非常に薄くなる領域ができ、耐圧が劣化する。． Usually, in the pre-treatment where the substrate surface is exposed, an oxide film called Native Oxide, which is formed on the substrate surface and contains many impurities, of several tens of liters or less is etched and then oxidized. However, in this step, the thicker oxide film is not uniformly etched, and a very thin region is formed, which deteriorates the breakdown voltage.
．トンネル酸化膜５の膜厚を変えると厚い浮遊ゲート
絶縁膜３の膜厚に影響を与え、途中から膜厚の変更する
場合に大きな制約となる。． When the film thickness of the tunnel oxide film 5 is changed, it affects the film thickness of the thick floating gate insulating film 3 and becomes a big restriction when changing the film thickness midway.
本発明は上記事情に鑑みてなされたもので、膜厚の制御
性の良い浮遊ゲート絶縁膜を有し、耐圧の劣化を回避で
きるMIS型半導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MIS type semiconductor device having a floating gate insulating film having a good film thickness controllability and capable of avoiding deterioration of breakdown voltage.
本発明は、MIS型半導体装置特にE2PROMに関するもの
で、その要旨はゲート絶縁膜を部分的に薄くするととも
に、ゲート絶縁膜の膜厚の薄い領域であってトンネル作
用を有する部分をシリコン酸化膜から構成しかつ他の部
分をシリコン酸化膜／シリコン窒化膜／シリコン酸化膜
の三層から構成することにより、耐圧の劣化のない制御
性の良い浮遊ゲート絶縁膜を得ることができるものであ
る。The present invention relates to a MIS type semiconductor device, in particular to an E 2 PROM, and its gist is to partially thin a gate insulating film and to reduce a portion of the gate insulating film having a thin film thickness, which has a tunnel effect, by a silicon oxide film. A floating gate insulating film having good controllability without deterioration of breakdown voltage can be obtained by forming the film and forming the other part by three layers of silicon oxide film / silicon nitride film / silicon oxide film. .
以下、本発明を第１図（ａ）〜（ｆ）、第４図（ａ）〜
（ｆ）を参照して説明する。Hereinafter, the present invention will be described with reference to Figs. 1 (a) to (f) and Fig. 4 (a).
This will be described with reference to (f).
実施例１ （１）．まず、例えばＰ型のシリコン基板21の表面にフ
ィールド酸化膜22を形成した（第１図（ａ））。つづい
て、このフィールド酸化膜22で囲まれた基板表面に熱酸
化により厚さ60Åのシリコン酸化膜23を形成した後、CV
D（Chemical Vapour Deposition）法により厚さ80Åの
シリコン窒化膜24を形成し、更にこの窒化膜24上のトン
ネル酸化膜形成形成予定部にレジスト25を形成した（第
１図（ｂ）図示）。次いで、レジスト25をマスクとして
前記窒化膜24をプラズマを利用したドライエッチングに
より除去し、更に同レジスト25をマスクとしてシリコン
酸化膜23を希HF浸漬によりエッチング除去した後、レジ
スト25を剥離した（第１図（ｃ）図示）。しかる後、熱
酸化により厚さ500〜600Åの厚いシリコン酸化膜26を形
成するとともに、窒化膜24上に薄いシリコン酸化膜27を
形成し、これら酸化膜26、27、窒化膜24及び前記酸化膜
23からなる浮遊ゲート絶縁膜28を形成した。この際、ト
ンネル酸化膜形成予定部では窒化膜24が存在することに
より酸化がほとんど進まず、全体膜厚としては20Å以下
であり、厚いシリコン酸化膜26との間に大きな膜厚差を
生じさせることができた。なお、シリコン酸化膜23、シ
リコン窒化膜24及び薄いシリコン酸化膜27を総称してト
ンネル酸化膜29と呼ぶ（第１図（ｄ）図示）。Example 1 (1). First, a field oxide film 22 was formed on the surface of, for example, a P-type silicon substrate 21 (FIG. 1 (a)). Then, after forming a silicon oxide film 23 with a thickness of 60Å on the substrate surface surrounded by the field oxide film 22 by thermal oxidation, CV
A silicon nitride film 24 having a thickness of 80Å was formed by a D (Chemical Vapor Deposition) method, and a resist 25 was formed on a portion of the nitride film 24 where a tunnel oxide film was to be formed (shown in FIG. 1 (b)). Then, using the resist 25 as a mask, the nitride film 24 is removed by dry etching using plasma, the silicon oxide film 23 is further removed by etching with dilute HF using the resist 25 as a mask, and then the resist 25 is peeled ( FIG. 1 (c) is shown). Then, a thick silicon oxide film 26 having a thickness of 500 to 600 Å is formed by thermal oxidation, and a thin silicon oxide film 27 is formed on the nitride film 24. The oxide films 26, 27, the nitride film 24 and the oxide film are formed.
A floating gate insulating film 28 made of 23 was formed. At this time, the oxidation hardly progresses due to the presence of the nitride film 24 in the tunnel oxide film formation planned portion, and the total film thickness is 20 Å or less, which causes a large film thickness difference with the thick silicon oxide film 26. I was able to. The silicon oxide film 23, the silicon nitride film 24, and the thin silicon oxide film 27 are generically called a tunnel oxide film 29 (shown in FIG. 1 (d)).
次に、全面に多結晶シリコン層（図示せず）を形成した
後、パターニングして多結晶シリコンからなる浮遊ゲー
ト電極30を形成した。つづいて、この浮遊ゲート電極30
をマスクとして基板21にイオン注入しＮ型の拡散層（図
示せず）を形成した（第１図（ｅ）図示）。次いで、全
面に層間絶縁膜31を形成し、更にこの上に多結晶シリコ
ンからなる制御ゲート電極32を形成した後、保護膜33を
形成してE2PROMを製造した（第１図（ｆ）、第２図及び
第５図図示）。ここで、第２図は第１図（ｆ）の平面
図、第５図は第１図の基本回路図である。また、第２図
で、34はＮ＋型の拡散層を示す。Next, a polycrystalline silicon layer (not shown) was formed on the entire surface and then patterned to form a floating gate electrode 30 made of polycrystalline silicon. Next, this floating gate electrode 30
Using as a mask, ions were implanted into the substrate 21 to form an N type diffusion layer (not shown) (shown in FIG. 1 (e)). Next, an interlayer insulating film 31 is formed on the entire surface, and a control gate electrode 32 made of polycrystalline silicon is further formed on the interlayer insulating film 31, and then a protective film 33 is formed to manufacture an E 2 PROM (FIG. 1 (f)). , FIG. 2 and FIG. 5). Here, FIG. 2 is a plan view of FIG. 1 (f), and FIG. 5 is a basic circuit diagram of FIG. Further, in FIG. 2, 34 denotes an N + type diffusion layer.
本発明に係るE2PROMは、第１図（ｆ）に示す如く、シリ
コン基板21上に浮遊ゲート絶縁膜28を設け、該浮遊ゲー
ト絶縁膜28をシリコン酸化膜23／シリコン窒化膜24／薄
いシリコン酸化膜27の三層からなるトンネル酸化膜29
と、厚いシリコン酸化膜26とから構成し、更に前記浮遊
ゲート絶縁膜28の上方に浮遊ゲート電極30、制御ゲート
電極32を夫々絶縁して設けた構造となっている。In the E 2 PROM according to the present invention, as shown in FIG. 1 (f), a floating gate insulating film 28 is provided on a silicon substrate 21, and the floating gate insulating film 28 is formed of a silicon oxide film 23 / silicon nitride film 24 / thin film. Tunnel oxide film 29 consisting of three layers of silicon oxide film 27
And a thick silicon oxide film 26, and a floating gate electrode 30 and a control gate electrode 32 are provided above the floating gate insulating film 28 so as to be insulated from each other.
従って、実施例１によれば、以下に示す効果を有する。Therefore, according to Example 1, there are the following effects.
．厚いシリコン酸化膜26を自由に制御でき、膜厚の制
御性が向上する。これは、第１図（ｄ）に示す如く、シ
リコン基板21とシリコン窒化膜24の大きな酸化レートの
差を利用して、基板21上には厚さ500〜600Åの厚いシリ
コン酸化膜26を形成できるとともに、シリコン窒化膜24
上の薄いシリコン酸化膜27を20Å以下に押えることがで
きることによる。． The thick silicon oxide film 26 can be freely controlled, and the controllability of the film thickness is improved. This is because, as shown in FIG. 1D, a thick silicon oxide film 26 having a thickness of 500 to 600 Å is formed on the substrate 21 by utilizing the large difference in oxidation rate between the silicon substrate 21 and the silicon nitride film 24. Along with the silicon nitride film 24
This is because the upper thin silicon oxide film 27 can be suppressed to 20 Å or less.
．基板21上の不純物を多く含むNative Oxideを除去す
る酸化前処理を行なっても、シリコン窒化膜24はエッチ
ングされないため、膜厚の変化はなくかつ不均一エッチ
ングによる耐圧不良の発生を回避できる。． Since the silicon nitride film 24 is not etched even if the pre-oxidation treatment for removing the native oxide containing a large amount of impurities on the substrate 21 is performed, there is no change in the film thickness and it is possible to avoid the occurrence of breakdown voltage failure due to nonuniform etching.
．浮遊ゲート電極30下の厚いシリコン酸化膜26と薄い
シリコン酸化膜27の夫々の膜厚を独立に制御することが
できる。． The thicknesses of the thick silicon oxide film 26 and the thin silicon oxide film 27 below the floating gate electrode 30 can be independently controlled.
．トンネル酸化膜がシリコン酸化膜23とシリコン窒化
膜24と薄いシリコン酸化膜27とから構成されているた
め、従来のシリコン酸化膜単層の場合と比べ耐圧が優
れ、浮遊ゲート絶縁膜全体の耐圧特性が改善されて特性
が著しく向上する。． Since the tunnel oxide film is composed of the silicon oxide film 23, the silicon nitride film 24, and the thin silicon oxide film 27, the breakdown voltage is superior to that of the conventional silicon oxide single layer, and the breakdown voltage characteristics of the entire floating gate insulating film are high. Is improved and the characteristics are remarkably improved.
実施例２ まず、実施例１と同様にＰ型のシリコン基板21の表面に
フィールド酸化膜22を形成し（第４図（ａ）図示）、更
に基板21表面にシリコン酸化膜23、シリコン窒化膜24を
形成した。つづいて、全面にトンネル酸化膜形成予定部
に対応する部分が開口したレジスト41を形成した（第４
図（ｂ）図示）。次いで、このレジスト41をマスクとし
て前記窒化膜24、酸化膜22を選択的にエッチング除去し
た後、レジスト41を剥離した（第４図（ｃ）図示）。し
かる後、熱酸化を行なった。その結果、上記酸化膜23の
開口された基板21の表面には厚さ100Åのシリコン酸化
膜（トンネル酸化膜）42形成され、また窒化膜24上には
10Å以下のシリコン酸化膜43が形成された。この際、全
体の膜厚の変化は数Å以下であるため、トンネル酸化膜
42の膜厚を独立に制御できる（第４図（ｄ）図示）。な
お、同図（ｄ）において、トンネル酸化膜42と、シリコ
ン酸化膜23／シリコン窒化膜24／シリコン酸化膜43の三
層の酸化膜領域とを総称して浮遊ゲート絶縁膜27と呼
ぶ。更に、多結晶シリコンからなる浮遊ゲート電極30を
形成した（第第４図（ｅ）図示）後、層間絶縁膜膜31、
制御ゲート電極32、保護膜33を形成してE2PROMを製造し
た（第４図（ｆ）図示）。Example 2 First, as in Example 1, a field oxide film 22 is formed on the surface of a P-type silicon substrate 21 (shown in FIG. 4A), and a silicon oxide film 23 and a silicon nitride film are further formed on the surface of the substrate 21. 24 formed. Subsequently, a resist 41 having an opening corresponding to a portion where a tunnel oxide film is to be formed is formed on the entire surface (fourth
Figure (b) illustration). Next, the nitride film 24 and the oxide film 22 are selectively removed by etching using the resist 41 as a mask, and then the resist 41 is peeled off (shown in FIG. 4 (c)). Then, thermal oxidation was performed. As a result, a 100 Å-thick silicon oxide film (tunnel oxide film) 42 is formed on the surface of the substrate 21 where the oxide film 23 is opened, and on the nitride film 24.
A silicon oxide film 43 having a thickness of 10 Å or less was formed. At this time, since the change in the total film thickness is less than several Å, the tunnel oxide film
The film thickness of 42 can be controlled independently (shown in FIG. 4 (d)). In FIG. 3D, the tunnel oxide film 42 and the three-layer oxide film regions of the silicon oxide film 23 / silicon nitride film 24 / silicon oxide film 43 are collectively called a floating gate insulating film 27. Further, after forming a floating gate electrode 30 made of polycrystalline silicon (shown in FIG. 4 (e)), an interlayer insulating film film 31,
An E 2 PROM was manufactured by forming the control gate electrode 32 and the protective film 33 (shown in FIG. 4 (f)).
実施例２に係るE2PROMは、第４図（ｆ）に示す如く、シ
リコン酸化膜（トンネル酸化膜）42と、シリコン酸化膜
23／シリコン窒化膜24／薄いシリコン酸化膜27の三層か
らなる厚い酸化膜領域とから構成された浮遊ゲート絶縁
膜28を有した構造となっている。The E 2 PROM according to the second embodiment has a silicon oxide film (tunnel oxide film) 42 and a silicon oxide film 42 as shown in FIG. 4 (f).
The structure has a floating gate insulating film 28 composed of a thick oxide film region composed of three layers of 23 / silicon nitride film 24 / thin silicon oxide film 27.
以上詳述した如く本発明によれば、膜厚の制御性の良い
浮遊ゲート絶縁膜を有し、もって耐圧の劣化を回避し得
るE2PROM等のMIS型半導体装置を提供できる。As described above in detail, according to the present invention, it is possible to provide an MIS type semiconductor device such as an E 2 PROM which has a floating gate insulating film having a good film thickness controllability and which can avoid deterioration of breakdown voltage.
第１図（ａ）〜（ｆ）は本発明の実施例１に係るE2PROM
を製造工程順に示す断面図、第２図は第１図（ｆ）の平
面図、第３図（ａ）〜（ｈ）は従来のE2PROMを製造工程
順に示す断面図、第４図（ａ）〜（ｆ）は本発明の実施
例２に係るE2PROMを製造工程順に示す断面図、第５図は
実施例１に係るE2PROMの基本回路図である。 21……Ｐ型のシリコン基板、22……フィールド酸化膜、
23、26、27……シリコン酸化膜、24……シリコン窒化
膜、25、41……レジスト、28……浮遊ゲート絶縁膜、2
9、42……トンネル酸化膜、30……浮遊ゲート電極、31
……層間絶縁膜、32……制御ゲート電極、33……保護
膜。FIGS. 1A to 1F are E 2 PROMs according to the first embodiment of the present invention.
Is a sectional view showing the manufacturing steps in the order of manufacturing steps, FIG. 2 is a plan view of FIG. 1 (f), and FIGS. 3 (a) to 3 (h) are sectional views showing the conventional E 2 PROM in the order of manufacturing steps, and FIG. (a) to (f) are sectional views showing the E 2 PROM according to the second embodiment of the present invention in the order of manufacturing steps, and FIG. 5 is a basic circuit diagram of the E 2 PROM according to the first embodiment. 21 …… P-type silicon substrate, 22 …… Field oxide film,
23, 26, 27 …… Silicon oxide film, 24 …… Silicon nitride film, 25, 41 …… Resist, 28 …… Floating gate insulating film, 2
9, 42 …… Tunnel oxide film, 30 …… Floating gate electrode, 31
...... Interlayer insulating film, 32 …… Control gate electrode, 33 …… Protective film.
Claims (1)
拡散層と、この基板上に設けられ部分的に膜厚の薄い領
域を有するゲート絶縁膜と、このゲート絶縁膜上に設け
られた浮遊ゲート電極と、この浮遊ゲート電極上に絶縁
膜を介して設けられた制御ゲート電極とを具備し、 前記ゲート絶縁膜の膜厚の薄い領域であってトンネル作
用を有する部分がシリコン酸化膜からなり、かつ他の部
分のゲート絶縁膜がシリコン酸化膜／シリコン窒化膜／
シリコン酸化膜の三層からなることを特徴とするMIS型
半導体装置。1. A semiconductor substrate, a diffusion layer provided on the surface of the substrate, a gate insulating film provided on the substrate and having a partly thin region, and a gate insulating film provided on the gate insulating film. The floating gate electrode and a control gate electrode provided on the floating gate electrode via an insulating film are provided, and a portion having a thin film thickness of the gate insulating film and having a tunnel action is formed from a silicon oxide film. And the gate insulating film on the other part is silicon oxide film / silicon nitride film /
An MIS type semiconductor device comprising three layers of a silicon oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269977A JPH0669099B2 (en) | 1984-12-21 | 1984-12-21 | MIS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59269977A JPH0669099B2 (en) | 1984-12-21 | 1984-12-21 | MIS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61147576A JPS61147576A (en) | 1986-07-05 |
| JPH0669099B2 true JPH0669099B2 (en) | 1994-08-31 |
Family
ID=17479855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59269977A Expired - Lifetime JPH0669099B2 (en) | 1984-12-21 | 1984-12-21 | MIS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669099B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2670262B2 (en) * | 1987-01-09 | 1997-10-29 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JP2675304B2 (en) * | 1987-05-14 | 1997-11-12 | 三洋電機株式会社 | Method of manufacturing nonvolatile memory element |
| JP2577383B2 (en) * | 1987-06-16 | 1997-01-29 | 株式会社東芝 | Method of manufacturing nonvolatile semiconductor memory device |
| JP2739593B2 (en) * | 1989-06-02 | 1998-04-15 | セイコーインスツルメンツ株式会社 | Semiconductor device manufacturing method |
| JPH0319286A (en) * | 1989-06-15 | 1991-01-28 | Matsushita Electron Corp | Manufacture of nonvolatile semiconductor memory |
| JPH0379083A (en) * | 1989-08-23 | 1991-04-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0388370A (en) * | 1989-08-31 | 1991-04-12 | Toshiba Corp | Manufacture of semiconductor memory device |
| JPH081933B2 (en) * | 1989-12-11 | 1996-01-10 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| US5331189A (en) * | 1992-06-19 | 1994-07-19 | International Business Machines Corporation | Asymmetric multilayered dielectric material and a flash EEPROM using the same |
| KR100572327B1 (en) * | 2004-07-06 | 2006-04-18 | 삼성전자주식회사 | Method of forming tunneling insulating film of nonvolatile memory device |
| JP4834517B2 (en) * | 2006-11-09 | 2011-12-14 | 株式会社東芝 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5955071A (en) * | 1982-09-24 | 1984-03-29 | Hitachi Micro Comput Eng Ltd | Non-volatile semiconductor device |
| JPS5966171A (en) * | 1982-10-08 | 1984-04-14 | Hitachi Ltd | Semiconductor device |
-
1984
- 1984-12-21 JP JP59269977A patent/JPH0669099B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61147576A (en) | 1986-07-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |