JPH0669159B2 - Adaptive receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to adaptive reception techniques for digital signals. In order to demodulate digital signals, especially received signals in wireless transmission, carrier signal reproduction and clock signal extraction are usually indispensable. Among these, if the clock is extracted on the receiving side, the carrier signal can be realized without much problem by controlling the reproduced carrier phase at the symbol rate. On the other hand, for the clock signal, it is necessary to control shorter repeating pulses. For example, if only a sampling timing error of about 1/20 times the symbol rate is allowed, it is necessary to handle a pulse signal that is 20 times higher than the symbol rate. Further, the detection of the timing phase shift is not so easy as the detection of the carrier phase difference.

An object of the present invention is to provide a receiving system for obtaining an optimum timing sample signal without performing related timing extraction on the receiving side.

The present invention comprises: a storage circuit that stores N sampled received signal sequences; a transversal adaptive equalizer that adaptively absorbs waveform distortion and sample timing deviation of the received signal; The first step of storing the value received signal series in the storage circuit in the order of input and optimizing the tap coefficient of the transversal adaptive equalizer by the received signal series is performed, and after the first step is completed, The arrangement order of the tap coefficients of the transversal adaptive equalizer is all reversed so that the N
Output the sampled value received signal sequence in the reverse order of the input,
In addition to the input of the transversal adaptive equalizer, the equalization is performed from the output of the transversal adaptive equalizer by a second step of performing adaptive equalization on the N received signal sequences output in the reverse order. It is an adaptive receiver characterized by obtaining a received signal sequence.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a burst-shaped digital signal 102,1 from the master station 100.
03 is shown to be sent to the child station 101. The digital signals 102 and 103 usually have the structure shown in FIG. That is, a carrier unit 200 that transmits a pure carrier so that the slave station 101 can perform carrier reproduction, a clock transmission unit 201 that is composed of a modulated wave that is subjected to 0π modulation so that clock extraction can be performed subsequently, and After that, the transmission data section 202 follows.

Since carrier regeneration is not particularly relevant to the present invention, it is assumed that carrier regeneration is completely completed by another means. If the transmission data is four-phase PSK, the demodulated waveform on the in-phase or on the quadrature side after synchronous detection has a shape as shown in FIG. 3 (d). The most suitable clock sample phase for the same waveform is shown in FIG. That is, the eye of the signal coincides with the time when the signal is opened most. Here, the transmit clock f _CT and the receive clock f _CR are That is, it is assumed that both clocks are maintained at values very close to each other.

This is a generally accepted condition for data transmission. At this time, the sample phase of the clock gradually deviates from the optimum timing (a) with respect to the received waveform (d) as time passes, as shown in (b) and (c). Here, FIG. 4A, FIG. 4B shows the phase-plane signal point distribution of four-phase PSK when waveforms are sampled at the respective clock phases in FIG. 3A, FIG. ) And (c). As is clear from this figure, while the deviation time τ from the optimum timing of the clock is small, there is not much problem as in (b), but as τ approaches half of the symbol period T, the phase plane signal point distribution becomes large. Finally, as shown in (c), correct identification is impossible.

The above-mentioned deterioration due to the phase shift of the clock can be improved to some extent by the transversal automatic equalizer by the baud rate sampling shown in FIG.

In the figure, reference numerals 50, 51, 52 and 53 denote delay circuits having a symbol period T, and 54, 55 and 5
6, 57 and 58 are variable coefficient taps, and 59 is an adder. When a signal as shown in FIG. 4 (b) is input from the input terminal 500, the output terminal 501 is deteriorated due to the timing phase shift. Then, a signal as shown in FIG. 4 (a) is output.

As shown in FIG. 6, the transversal automatic equalizer's ability to absorb the timing phase shift by baud rate sampling rapidly deteriorates as τ approaches T / 2.
Here, the vertical axis of FIG. 6 is the signal point dispersion after equalization. Is represented.

On the other hand, in the double-sampling automatic equalizer as shown in FIG. 7 in which the input signal is sampled at a half cycle and the doubled data is sent to the equalizer, such deterioration of the timing phase shift absorption capability is caused. It is known that there is no.

In the conventional method, since clock synchronization is probable, there is no problem in the sampling period at the data rate (each sampled at the center of the transmission data pulse). On the other hand, in the case of the collective batch demodulation method, which is a premise of the present invention, since clock synchronization is not established, it is necessary to interpolate a signal at an arbitrary time from the received sample value. For that purpose, as the Shannon sampling theorem teaches, a sampling rate twice as high as the data rate is required.

Conversely, if a sample value that is twice the data rate exists, the transversal equalizer can realize an arbitrary characteristic filter and therefore can also have a characteristic as an interpolation filter. Of course, it is possible to have a carrier phase error absorption function at the same time.

In the figure, 70, 71, 72, 73, 74 are T / 2 delay circuits, 75, 76, 7
7,78,79,80 are coefficient variable taps, and 81 is an adder. According to this equalizer, even if τT / 2, the added sample phase is τ> 0, and the output terminal 701 has a fourth phase.
An equalized signal as shown in FIG. 4 (a) is obtained.

Now, the coefficient control method for taps shown in FIG. 7 is generally the mean square (MS) method. The coefficient Cj of the tap j is controlled according to the formula Cj ⁽ h ^{+ 1)} = Cj ⁽ h ⁾ −α · Sj ^* · E. Here, h is the number of control circuits, Sj is the input signal of the j tap, E is the identification error of the equalizer output (distance vector from the normal signal point), α is a small correction coefficient (α> 0), *
Indicates the complex conjugate of a complex number.

FIG. 8 embodies the above equation. S to input terminal 800
j is added to the input terminal 801 with the output from the equalizer output terminal 701, the discrimination error E is obtained by the discriminator 85 and the subtractor 86, and the multiplier 88 and the imaginary part sign inverter 87 output Sj ^*. E is obtained, and by the inverter of 89 and the potentiometer 90-
α · Sj ^* · E is obtained and this output is added to the current tap value Cj. By connecting this control circuit to the equalizer of FIG. 7, the tap coefficient of the received signal sequence having the timing phase shift applied to the input terminal of the equalizer is gradually optimized, and the final timing phase is obtained. A signal with no deviation comes out from the same output terminal. However, a significant amount of signal must pass through the equalizer before such a signal is obtained. When f _CT ≠ f _CR , the phase difference between the two is changing sequentially, so the taps of the equalizer cannot be fixed semi-fixed.

Under such circumstances, the present invention aims to obtain a signal having no timing phase shift without receiving any signal other than a data signal. 9 (a) and 9 (b) show block diagrams of an embodiment of the present invention.

To the input terminal 900, N demodulated signal sequences sampled at twice the baud rate are added.

The same signal sequence is stored in the memory circuit 95 in the order of input, and at the same time, it is applied to the input of a transversal adaptive equalizer 96 including a double-sampling automatic equalizer and a tap control circuit, and each tap has a sample timing phase. Controlled to absorb the deviation. It is assumed that each tap has already been optimized when all the N demodulated signal sequences have been added.

However, since the transmission / reception timing phase changes every moment, the tap value at this point is optimized for the vicinity of the last data. Therefore, even if the signal system is directly added to the equalizer input in the input order stored in the storage circuit with the tap value as the initial value, a signal in which the timing phase shift is absorbed cannot be obtained. Therefore, in FIG. 9B, the data read from the memory circuit 95 is read in the reverse order of the input,
In addition, the order of each tap coefficient is reversed so that the inverse time signal and the equalizer can handle (in synchronization with the switch 98), the memory circuit output is input to the inverse time equalizer through the switch 98, and the tap control circuit is By letting it work as it is, it is possible to cope with the subsequent change in the timing phase shift.

In this case, the finally obtained data sequence is the reverse of the actual data sequence, but this causes the received signals to be processed in the reverse order in advance to perform the process of the present invention. Return to the original by taking care so that the same data is output in the reverse order at.

The related carrier synchronization processing has already been
It is listed in Japanese Patent Application No. 57-127937 filed on July 22, 57.

As described above, according to the present invention, it is possible to obtain a signal sequence sampled at the optimum timing from the burst signal by receiving the data signal in a burst form without receiving a special signal for clock extraction. You can

[Brief description of drawings]

FIG. 1 is a diagram for explaining burst digital communication,
FIG. 2 is a diagram for explaining the structure of the burst signal, FIG. 3 is a diagram for explaining the relationship between the demodulated baseband signal and the receiving side clock phase, and FIG. 4 is each receiving side clock phase. The figure which shows the phase-plane signal point distribution of the sampled 4-phase PSK. FIG. 5 is a diagram for explaining a transversal automatic equalizer for boat rate sampling, FIG. 6 is a timing phase shift absorption capacity of the automatic equalizer of FIG. 5, and FIG. 7 is a double sampling transversal automatic equalizer. FIG. 8 is a block diagram of the equalizer, FIG. 8 is a block diagram of the tap coefficient control circuit of the equalizer of FIG. 8, and FIG. 9 is an embodiment block of the present invention. In the figure, 95 is a memory circuit, 96 is a forward time transversal adaptive equalizer, and 97 is a reverse time transversal adaptive equalizer.

Claims (1)

[Claims] 1. A storage circuit for storing N sampled received signal sequences; a transversal adaptive equalizer for adaptively absorbing waveform distortion and sample timing deviation of the received signal; The first step of storing the sample value received signal sequence in the storage circuit in the order of input and optimizing the tap coefficient of the transversal adaptive equalizer according to the received signal sequence is performed, and after the first step is completed, the first step is performed. The arrangement order of the tap coefficients of the transversal adaptive equalizer is all reversed so that the N
Output the sampled value received signal sequence in the reverse order of the input,
In addition to the input of the transversal adaptive equalizer, equalization is performed from the output of the transversal adaptive equalizer by a second step of continuously performing adaptive equalization on the N received signal sequences output in the reverse order. An adaptive receiver which obtains a received signal sequence.