JPH0670649B2 - oscilloscope - Google Patents

Description

TECHNICAL FIELD The present invention relates to an oscilloscope and the like.

2. Description of the Related Art In recent years, oscilloscopes are increasingly displaying characters and cursors to facilitate measurement. However, with real-time oscilloscopes, characters and cursors are drawn while drawing the observed waveform, so time-sharing the electron beam of the CRT is inevitable. As a result, when the frequency of the observed waveform is close to the division frequency of the electron beam, the observed waveform is drawn as a discontinuous bright line and is very difficult to observe.

FIG. 5 shows a conventional example. The operation will be described with reference to the waveforms of each part in FIG. Since the basic part of the oscilloscope has been known for many years, only the essential points will be explained.

The observed waveform a applied to the vertical axis input channel 1 input terminal 1 or the vertical axis input channel 2 input terminal 4 is vertically adjusted by increasing or decreasing to a desired amplitude in the vertical axis channel 1 circuit 2 or the vertical axis channel 2 circuit 5. It is added to the axis channel switching circuit 3 and selectively enters the vertical axis signal delay circuit 6. The observed signal having the required delay amount is alternately switched by the vertical axis signal / character switching circuit 7 by the character display switching signal f and the vertical axis signal g for character display, and a composite vertical axis signal / character switching is performed. The circuit output signal i is applied to the vertical axis output amplifier circuit 8, amplified to the amplitude required by the cathode ray tube 9 and applied to the vertical axis deflection plate of the cathode ray tube 9.

A signal similar to the observed signal a is generally given from the vertical axis circuit to the main sweep reference sync signal input terminal 10, and the main sweep reference sync circuit is supplied.
At 11, the synchronizing pulse b is generated at the time when the synchronizing level Vt is reached, and is applied to the main sweep quote sweep signal generating circuit 12 to generate the main sweep signal c. A part of the main sweep signal c is added together with the sweep delay time generation comparison circuit 13 delay position level voltage Va to generate the delay time signal d, and the delay sweep quote synchronization circuit
It is applied to the delayed sweep reference sweep signal generation circuit 16 together with the output of 15 to generate the delayed sweep signal e. The main sweep signal c and the delayed sweep signal e are selectively added to the horizontal axis signal / character switching circuit 18 through the horizontal axis signal switching circuit 17, and are switched between the character display horizontal axis signal h and the character display switching signal f. The horizontal axis signal / character switching circuit output signal j which is switched alternately is applied to the horizontal axis signal switching circuit 17, amplified to the amplitude required by the cathode ray tube 9 and applied to the horizontal axis deflection plate of the cathode ray tube 9.

Erase signal n in the vertical axis signal switching period obtained from the vertical axis channel switching circuit 3, main sweep gate signal 1 obtained from the main sweep reference sweep signal generation circuit 12, and delayed sweep gate obtained from the delayed sweep reference sweep signal generation circuit 16 The signal m is applied to the brightness control signal switching circuit 21 together with the external signal from the brightness control external signal input terminal 20, and switched to the character display brightness control signal by the character display switching signal f for brightness control. The signal / character switching circuit output signal i is amplified and shaped in the brightness control signal amplifier circuit 22 to have an amplitude necessary for brightness control of the cathode ray tube 9 and applied to the first grid of the cathode ray tube 9. The various character signals f, g, h, and o described above are generated by the character signal generation circuit 24, and the display contents, position, display timing, etc. of characters are instructed from the control system circuit 30 mainly of the CPU through the control system bus 29. It

However, the observed signal waveform and the character display are as shown in FIG. 8. In order to display the character during the period of drawing the observed signal waveform depending on the sweep speed and timing. The part where the bright line is cut off is very conspicuous, which hinders the observation. Especially when observing the TV signal waveform, if the observed signal waveform is expanded in the horizontal axis direction by using the delayed sweep function, the dot period of the character signal often becomes close to the sweep time. The loss of the bright line above will cause a fatal obstacle.

SUMMARY OF THE INVENTION The present invention is intended to alleviate and remedy such conventional drawbacks, and an object thereof is to provide an excellent oscilloscope with few missing bright lines even when displaying characters and cursors together with signal waveforms.

Means for Solving the Problems In order to solve the above problems, the present invention uses an oscilloscope having a TV synchronization function, a delayed sweep function, and a character display function, in which the TV synchronization function is used and the sweep speed is a character display function. When the clock frequency approaches, the character display function is partially interrupted.

Effects The present invention can prevent the character display during the delayed sweep period and prevent the observed signal waveform from being interrupted due to the character display function in the delayed sweep enlarged display.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. Except for the thick solid line, it is exactly the same as FIG. 6 of the conventional example. The thick solid line portion will be described.

A part of the delayed sweep gate signal m is supplied to the character signal generation circuit 24 or the character display switching limiting gate 50 for suppressing the character display switching signal f to prohibit the character display operation during the delayed sweep period. As a result, in the delayed sweep enlargement display shown in FIG. 9, the disadvantage that the observed signal waveform is interrupted due to the character display function is solved. In addition, the delayed sweep period is usually about 1/2 times higher than the main sweep period, and even if the characters are not displayed during the delayed sweep period, the character display on the CRT screen has at least 70% or more character brightness. It's maintainable and doesn't lose letters.

FIG. 1 is a block diagram showing the concept of the present invention.
FIG. 3 shows an embodiment of the main part of the present invention centering on the character display circuit portion. FIGS. 3 and 4 show a concrete example embodying the concept shown in FIG. 2, and FIG. FIG. 4 is a signal waveform diagram showing an operation example of FIGS. 2 and 3.

The present invention will be described below with reference to FIGS.
Among the numbers indicating the respective parts in the drawings and the characters indicating the signals, 1 to 30 and a to o which are the same as those in FIGS. 6 to 9 have the same functions, and will be repeatedly described below. Is omitted. That is, the present invention shown in FIGS. 1 and 2 is obtained by adding a modification or extension to a part of the conventional example shown in FIG. Therefore, it is judged that there is no problem even if the explanation is limited to the changed / added parts.

The difference between FIG. 1 and FIG. 6 is that the delayed sweep gate signal m is supplied to the character signal generating circuit 24 to form a new character signal generating circuit 24a.

Second detailed configuration centering on the new character signal generation circuit 24a
In the figure, the character display information r sent from the control system circuit 30 mainly of the CPU through the control system bus circuit 29 is received by the character information receiving register 41 and also received by the character information receiving register 41. Control commands α, β, γ, δ,
The character display screen configuration RAM control signal γ in ε is stored and written in the character display screen configuration RAM 42. When this memory writing operation is completed, the coded character signal q, which is the character information stored in the character display screen configuration RAM 42, is read and coded according to the character position signal p output from the character display position control counter 43. It is supplied to the ROM 44 for converting a character signal to a character display signal, converted into a character display signal s necessary for vector display, and then entered into the character display signal transmission latch 45. The character display signal transmission latch 45 removes the transient disturbance of the signal generated by the ROM 44, and outputs 2 to generate an analog vector signal for actually displaying the character.
Digital-to-analog converters (hereinafter referred to as DACs) 46, 4
Supply to 7. The output t of the latch 45 is divided into two parts, while the character position signal p from the character display position control counter 43 is also divided into two parts, which become a character display vertical position control signal u and a character display horizontal position control signal v, respectively. It is supplied to the display vertical axis signal generating DAC 46 and the character display horizontal axis signal generating DAC 47. Thus, the character display vertical axis signal output circuit 25 and the character display horizontal axis signal output circuit 26 receiving the outputs of the two DACs 46 and 47 respectively obtain the character display vertical axis signal g and the character display horizontal axis signal h. .

Here, the character display position control counter 43 receives the character display clock signal via the character display clock signal control circuit 48.
In response to 49, the position data necessary for character display is sequentially generated, but the character display clock signal control circuit 48 receives the delay sweep gate signal 50 and receives the clock signal during the delay sweep period from time ts to te. In order to suppress the sending, the character display position control counter 43 is also stopped during the progress of the operation from time ts to te, and the character display switching signal output circuit 28 that receives one of the outputs is also a signal for performing the character display. The output operation is stopped from time ts to te. The other input 56 of the character display clock signal control circuit 48 shown in FIG. 2 will be described. The input 56 is supplied with the signal determined by the operation setting in FIG. In FIG. 3, the main sweep sync filter mode switch 51 provides a high level logic signal to the first gate 54 when the mode switch is set to TV sync. On the other hand, the main sweep time axis switch 52 and the delayed sweep time axis switch 53 send the high-level logic signal to the second gate 55 when the sweep speed is set to a state close to the character display clock signal. Supply. First gate 54
Acts as a logical product and the second gate 55 acts as a logical sum. As a result, when the observer observes a TV signal, the output 56 becomes a high level logic output, and the character display clock signal control circuit 48 in FIG. 2 causes the delayed sweep gate signal 50.
It is possible to make it more controlled. Output 56
When is a low-level logic output, it is possible to disable control by the delayed sweep gate signal 50. Fourth
The figure shows a specific example of the character display clock signal control circuit 48.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to eliminate the waveform breakage at the time of observing a TV signal by the character display function of the oroscope by an easy-to-implement method.

[Brief description of drawings]

1 is a block diagram of an oscilloscope according to an embodiment of the present invention, FIG. 2 is a block diagram of a character signal generation circuit according to the same embodiment, FIG. 3 is a specific circuit diagram of FIG. 2, and FIG.
Another specific circuit diagram of the figure, FIG. 5 is a signal waveform diagram of the same embodiment,
FIG. 6 is a block diagram of a conventional example, FIG. 7 is a signal waveform diagram of the conventional example, FIG. 8 is a display screen diagram in which characters and signal waveforms overlap, and FIG. 9 is a general display screen diagram. 7 ... Vertical axis signal / character switching circuit, 9 ... CRT,
12 …… Main sweep reference sweep signal generation circuit, 16 …… Delayed sweep reference sweep signal generation circuit, 17 …… Horizontal axis signal switching circuit, 18 …… Horizontal axis signal / character switching circuit, 21 …… Brightness control signal switching circuit , 24a …… Character signal generation circuit.

Claims (1)

[Claims] 1. An oscilloscope body having a television synchronization function, a delayed sweep function, and a character display function, a first detection means for detecting that the television synchronization function is used, and a main sweep or a delayed sweep sweep. When both the output signals of the second detecting means for detecting that the speed is within the constant frequency range of the clock frequency of the character displaying function and the output signals of the first and second detecting means, the character displaying function is provided. An oscilloscope with interruption means for partially interrupting the.