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JPH0671000B2 - Wiring formation method for semiconductor device - Google Patents
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JPH0671000B2 - Wiring formation method for semiconductor device - Google Patents

Wiring formation method for semiconductor device

Info

Publication number
JPH0671000B2
JPH0671000B2 JP5517385A JP5517385A JPH0671000B2 JP H0671000 B2 JPH0671000 B2 JP H0671000B2 JP 5517385 A JP5517385 A JP 5517385A JP 5517385 A JP5517385 A JP 5517385A JP H0671000 B2 JPH0671000 B2 JP H0671000B2
Authority
JP
Japan
Prior art keywords
insulating film
wiring layer
wiring
metal
metal oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5517385A
Other languages
Japanese (ja)
Other versions
JPS61214451A (en
Inventor
正彦 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP5517385A priority Critical patent/JPH0671000B2/en
Publication of JPS61214451A publication Critical patent/JPS61214451A/en
Publication of JPH0671000B2 publication Critical patent/JPH0671000B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の配線形成法に関し、特にモリ
ブデン(Mo)、タングステン(W)等の高融点金属を用
いた多層配線形成法に関するものである。
Description: TECHNICAL FIELD The present invention relates to a wiring forming method for a semiconductor device, and more particularly to a multilayer wiring forming method using a refractory metal such as molybdenum (Mo) or tungsten (W). Is.

〔発明の概要〕 この発明は、Mo、W等の高融点金属からなる配線層を形
成した後、その表面の金属酸化膜をエツチ除去してから
該配線層をおおうように非酸化性雰囲気中で絶縁膜を成
長させることにより配線層と絶縁膜との密着性を改善す
ると共に配線層に対する確実な電気的接続を可能にした
ものである。
SUMMARY OF THE INVENTION The present invention is directed to the formation of a wiring layer made of a refractory metal such as Mo or W, etching the metal oxide film on the surface thereof, and then covering the wiring layer in a non-oxidizing atmosphere. The growth of the insulating film improves the adhesion between the wiring layer and the insulating film and enables reliable electrical connection to the wiring layer.

〔従来の技術〕[Conventional technology]

従来、Mo、W等の高融点金属を用いてLSI等の微細配線
を形成することは知られている。
Conventionally, it has been known to form fine wiring such as LSI using a refractory metal such as Mo or W.

このような微細配線の形成法としては、高融点金属を被
着した後、ホトレジスト層をマスクとしてプラズマエツ
チ等のドライエツチによりパターニングを行ない、しか
る後酸素プラズマ中でホトレジスト膜をアツシング(灰
化)して除去し、さらにパターニングされた金属層上に
SiO2等の層間絶縁膜を常圧CVD(ケミカル・ペーパー・
デポジション)法により被着する方法が提案されてい
た。
As a method for forming such fine wiring, after depositing a refractory metal, patterning is performed by dry etching such as plasma etching using the photoresist layer as a mask, and then the photoresist film is etched (ashed) in oxygen plasma. Removed and then on the patterned metal layer
The interlayer insulating film such as SiO 2 is formed under normal pressure CVD (chemical paper,
A deposition method has been proposed.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記した従来法によると、次の(イ)及び(ロ)のような問題
点があつた。
According to the above-mentioned conventional method, there are the following problems (a) and (b).

(イ)金属層と絶縁膜との密着性が悪く、絶縁膜上に他の
配線用金属を蒸着又はスパツタ等により被着して熱処理
すると、絶縁膜がその下の金属層海面からはがれる事態
が生じた。
(A) Adhesion between the metal layer and the insulating film is poor, and when another wiring metal is deposited on the insulating film by vapor deposition or sputtering and heat-treated, the insulating film may peel off from the sea surface of the metal layer below. occured.

(ロ)絶縁膜にコンタクト孔を設けた後、他の配線用金属
を被着して上下の金属層を電気的に接続させたが、接続
不良のものが多かつた。
(B) After forming a contact hole in the insulating film, another wiring metal was deposited to electrically connect the upper and lower metal layers, but there were many cases of poor connection.

これらの問題点が生ずる原因を究明したところ、ホトレ
ジスト層をアツシングする際及び常圧CVD装置による膜
成長前の予備加熱(約350〜500℃)の際に高融点金属層
の表面に金属酸化膜が形成されることがわかつた。
The cause of these problems was investigated, and it was found that the metal oxide film was formed on the surface of the refractory metal layer at the time of assuring the photoresist layer and preheating (about 350 to 500 ° C) before film growth by the atmospheric pressure CVD device. It was discovered that

〔問題点を解決するための手段〕[Means for solving problems]

この発明は、上記した問題点を解決するためになされた
ものであつて、高融点金属層の表面から金属酸化膜を除
去すると共に非酸化性雰囲気中で絶縁膜を気相成長させ
ることを特徴とするものである。
The present invention has been made to solve the above-mentioned problems and is characterized in that the metal oxide film is removed from the surface of the refractory metal layer and the insulating film is vapor-phase grown in a non-oxidizing atmosphere. It is what

すなわち、この発明による半導体装置の配線形成法は、
次の(a)〜(c)のような工程を含むものである。
That is, the wiring forming method of the semiconductor device according to the present invention is
It includes the following steps (a) to (c).

(a)半導体基板の表面をおおうSiO2等の第1の絶縁膜の
上にMo、W等の高融点金属からなる配線層を形成する。
(a) A wiring layer made of a refractory metal such as Mo or W is formed on the first insulating film such as SiO 2 covering the surface of the semiconductor substrate.

(b)配線層の表面の金属酸化膜をエツチ除去する。(b) The metal oxide film on the surface of the wiring layer is removed by etching.

(c)金属酸化膜を除去した後、配線層及び第1の絶縁膜
をおおうように非酸化性雰囲気(例えば減圧下、Arガス
等)中でSiO2、Si3N4等の第2の絶縁膜を気相成長させ
る。この場合、減圧CVD法、プラズマCVD法等を用いるこ
とができる。
(c) After removing the metal oxide film, a second layer of SiO 2 , Si 3 N 4, etc. is formed in a non-oxidizing atmosphere (eg, under reduced pressure, Ar gas, etc.) so as to cover the wiring layer and the first insulating film. Vapor growth of the insulating film. In this case, a low pressure CVD method, a plasma CVD method or the like can be used.

〔作用〕[Action]

上記したこの発明の方法によれば、金属酸化膜を除去す
ると共に、非酸化性雰囲気中で第2の絶縁膜を気相成長
させるので、配線層と第2の絶縁膜との間に金属酸化膜
が介在することがなくなり、配線層-絶縁膜間で良好な
密着性が得られる。このため、第2の絶縁膜の上に他の
配線用金属層を被着して熱処理しても、第2の絶縁膜が
その下の金属槽からはがれるといつた事態は未然に防止
できる。
According to the method of the present invention described above, the metal oxide film is removed and the second insulating film is vapor-phase grown in a non-oxidizing atmosphere. Therefore, the metal oxide film is formed between the wiring layer and the second insulating film. There is no intervening film, and good adhesion can be obtained between the wiring layer and the insulating film. Therefore, even if another metal layer for wiring is deposited on the second insulating film and then heat-treated, it is possible to prevent a situation in which the second insulating film is peeled off from the metal bath thereunder.

また、第2の絶縁膜にコンタクト孔を設けた後、他の配
線用金属層を被着して上下の金属層を電気的に接続する
ような場合にも、上下の金属層間には良好なオーミツク
接触が確実に得られる。
In addition, even when a metal layer for wiring is deposited to electrically connect the upper and lower metal layers after providing the contact hole in the second insulating film, it is preferable that the upper and lower metal layers be connected to each other. A reliable ohmic contact is obtained.

〔実施例〕〔Example〕

第1図乃至第4図は、この発明の一実施例による多層配
線形成法工程を示すもので、各々の図番に対応する各工
程(1)〜(d)を順次に説明する。
FIGS. 1 to 4 show steps of a method for forming a multilayer wiring according to an embodiment of the present invention, and steps (1) to (d) corresponding to respective drawing numbers will be sequentially described.

(1)例えばシリコンからなる半導体基板10の表面にSiO2
等からなる第1の絶縁膜12を形成した後、この絶縁膜12
の上に真空蒸着法、スパツタ法等によりMo、W等の高融
点金属を被着し、所定の配線パターンにしたがつてパタ
ーニングを行なうことにより第1の配線層14を形成す
る。この場合、パターニングでは、ホトレジスト層16を
マスクとしてプラズマエツチ等のドライエツチを実施
し、しかる後酸素プラズマ中でホトレジスト層16をアツ
シングして除去する。このアツシングの際に配線層14の
表面には、金属酸化膜18が形成される。
(1) SiO 2 on the surface of a semiconductor substrate 10 made of, for example, silicon
After forming the first insulating film 12 made of
A refractory metal such as Mo or W is deposited on the above by a vacuum vapor deposition method, a sputtering method or the like, and patterning is performed according to a predetermined wiring pattern to form a first wiring layer 14. In this case, in patterning, dry etching such as plasma etching is performed using the photoresist layer 16 as a mask, and then the photoresist layer 16 is removed by ashing in oxygen plasma. At the time of this assembling, a metal oxide film 18 is formed on the surface of the wiring layer 14.

(2)次に、適当なエツチ液を用いて配線層14の表面の金
属酸化膜18をエツチ除去する。これは、次のCVD処理の
直前に行なうとよい。
(2) Next, the metal oxide film 18 on the surface of the wiring layer 14 is etched away using an appropriate etching liquid. This may be done just before the next CVD process.

(3)配線層14及び絶縁膜12をおおうように第2の絶縁膜2
0を減圧(例えば、0.1〜10Torr)下で気相成長させる。
すなわち、一例として減圧CVD法によりSiO2、Si3N4等を
堆積することにより絶縁膜20を形成する。従来は、常圧
CVD法により絶縁膜20を形成したが、その予備加熱の段
階で配線層14の表面に金属酸化膜が生じたことは前述し
た通りである。しかるに、上記のように、減圧CVD法に
よつて絶縁膜20を形成した場合には、CVD膜成長前に酸
化性雰囲気中で予備加熱をしないので、金属酸化膜が生
成されることがなく、絶縁膜20は配線層14と密に結合す
るようになる。
(3) Second insulating film 2 so as to cover the wiring layer 14 and the insulating film 12
0 is vapor-deposited under reduced pressure (for example, 0.1 to 10 Torr).
That is, as an example, the insulating film 20 is formed by depositing SiO 2 , Si 3 N 4, etc. by the low pressure CVD method. Conventionally, normal pressure
Although the insulating film 20 was formed by the CVD method, the metal oxide film was formed on the surface of the wiring layer 14 in the preheating step as described above. However, as described above, when the insulating film 20 is formed by the low pressure CVD method, since preheating is not performed in an oxidizing atmosphere before the CVD film growth, a metal oxide film is not generated, The insulating film 20 comes into close contact with the wiring layer 14.

(4)絶縁膜20に配線層14の一部を露出させるようにコン
タクト孔を設けた後、基板上面にAl等の配線用金属を真
空蒸着法、スパツタ法等により被着して適宜パターニン
グすることにより第2の配線層22を形成する。上記のよ
うに、配線層14の表面には金属酸化膜が存在しないの
で、配線層22は配線層14と確実に且つ良好にオーミツク
接触する。
(4) After forming a contact hole in the insulating film 20 so that a part of the wiring layer 14 is exposed, a wiring metal such as Al is deposited on the upper surface of the substrate by a vacuum deposition method, a sputtering method, or the like and appropriately patterned. As a result, the second wiring layer 22 is formed. As described above, since there is no metal oxide film on the surface of the wiring layer 14, the wiring layer 22 reliably and satisfactorily makes ohmic contact with the wiring layer 14.

〔発明の効果〕〔The invention's effect〕

以上のように、この発明によれば、Mo、W等の酸化しや
すい高融点金属からなる配線層を形成した後、配線層表
面の金属酸化膜をエツチ除去してからその上に絶縁膜を
非酸化性雰囲気中で気相成長させるようにしたので、配
線層と絶縁膜との間に金属酸化膜が介在することがなく
なり、両者の密着性が大幅に改善されると共に配線層に
対する確実な電気的接続が可能となる効果が得られるも
のである。
As described above, according to the present invention, after forming a wiring layer made of a refractory metal such as Mo or W which is easily oxidized, the metal oxide film on the surface of the wiring layer is removed by etching and then an insulating film is formed thereon. Since the vapor phase growth is performed in a non-oxidizing atmosphere, the metal oxide film is not present between the wiring layer and the insulating film, the adhesion between the two is greatly improved, and the reliability of the wiring layer is improved. The effect that electrical connection is possible is obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図乃至第4図は、この発明の一実施例による多層配
線形成工程を示す基板断面図である。 10……半導体基板、12……第1の絶縁膜、14……第1の
配線層、20……第2の絶縁膜、22……第2の配線層。
1 to 4 are cross-sectional views of a substrate showing a multilayer wiring forming process according to an embodiment of the present invention. 10: semiconductor substrate, 12: first insulating film, 14: first wiring layer, 20: second insulating film, 22: second wiring layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】(a)半導体基板の表面をおおう第1の絶縁
膜の上に高融点金属からなる配線層を形成する工程と、 (b)前記配線層の表面をエツチして金属酸化膜を除去す
る工程と、 (c)前記金属酸化膜を除去した後、前記配線層及び前記
第1の絶縁膜をおおうように非酸化性雰囲気中で第2の
絶縁膜を気相成長させる工程と を含む半導体装置の配線形成法。
1. A step of: (a) forming a wiring layer made of a refractory metal on a first insulating film covering a surface of a semiconductor substrate; and (b) etching the surface of the wiring layer to form a metal oxide film. And (c) after removing the metal oxide film, vapor-growing a second insulating film in a non-oxidizing atmosphere so as to cover the wiring layer and the first insulating film. Forming method of semiconductor device including:
JP5517385A 1985-03-19 1985-03-19 Wiring formation method for semiconductor device Expired - Lifetime JPH0671000B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5517385A JPH0671000B2 (en) 1985-03-19 1985-03-19 Wiring formation method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5517385A JPH0671000B2 (en) 1985-03-19 1985-03-19 Wiring formation method for semiconductor device

Publications (2)

Publication Number Publication Date
JPS61214451A JPS61214451A (en) 1986-09-24
JPH0671000B2 true JPH0671000B2 (en) 1994-09-07

Family

ID=12991334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5517385A Expired - Lifetime JPH0671000B2 (en) 1985-03-19 1985-03-19 Wiring formation method for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0671000B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0680739B2 (en) * 1987-05-19 1994-10-12 日本電気株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS61214451A (en) 1986-09-24

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