JPH0671026B2 - Semiconductor mounting method - Google Patents
Semiconductor mounting methodInfo
- Publication number
- JPH0671026B2 JPH0671026B2 JP62072245A JP7224587A JPH0671026B2 JP H0671026 B2 JPH0671026 B2 JP H0671026B2 JP 62072245 A JP62072245 A JP 62072245A JP 7224587 A JP7224587 A JP 7224587A JP H0671026 B2 JPH0671026 B2 JP H0671026B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- insulating resin
- semiconductor element
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体実装方法に関し、特に回路基板への半
導体素子、例えばフリップチップICの実装方法に関する
ものである。The present invention relates to a semiconductor mounting method, and more particularly to a method for mounting a semiconductor element such as a flip chip IC on a circuit board.
近年、電子機器の回路部には多くのICが使用される。こ
れらのICは各種の形態で供給され、特に実装の高密度化
を達成するために、フリップチップICの使用が増加して
きている。In recent years, many ICs have been used in the circuit section of electronic devices. These ICs come in a variety of forms, and the use of flip-chip ICs is increasing, especially to achieve higher packaging density.
半導体素子の実装方法としては、従来は特開昭57-45996
号公報（チップ部品の装着方法）に記載されるように、
はんだ付け方法が用いられている。フリップチップICの
はんだ付け方法としては、はんだペーストの印刷、又は
はんだボール等の成形はんだの配置等により、はんだ材
料を供給した後、ホットプレートにのせて加熱する方法
は広く行われていた。As a method of mounting a semiconductor element, a conventional method is disclosed in JP-A-57-45996.
As described in Japanese Patent Publication (Mounting method for chip parts),
A soldering method is used. As a method of soldering a flip chip IC, a method of supplying a solder material by printing a solder paste or arranging a molding solder such as a solder ball, and then placing it on a hot plate and heating it has been widely used.
また、この方法に改良を加えた方法として第５図に示す
リフロー装置による方法が提案された。第５図は、リフ
ロー装置を示す断面図で銅製のヒートブロック（８）に
ヒータ（９）が埋設されており、その外周にグラスファ
イバーと耐熱製樹脂（例えばデュポン社のテフロン）と
の複合材料でできたベルト（10）を配置したものであ
る。このように構成することにより、ベルト（10）上の
温度分布は、中央部のヒータ（９）の近い部分が最高と
なり、両端に行くに従って低くなる。このベルト（10）
にはんだ付けすべき回路基板（図示せず）を載せて移動
させると、回路基板はベルト（10）の端部から中央部に
移動するにつれて、はんだ付け温度まで次第に昇温され
る。ベルト（10）の中央部ではんだ付けがなされ、さら
にベルト（10）の中央部から端部へ移動するにつれて徐
々に冷やされる。Further, a method using a reflow device shown in FIG. 5 has been proposed as a method obtained by improving this method. FIG. 5 is a cross-sectional view showing a reflow apparatus, in which a heater (9) is embedded in a heat block (8) made of copper, and a composite material of glass fiber and heat-resistant resin (for example, Teflon manufactured by DuPont) is provided around the heater. The belt (10) made of is arranged. With this structure, the temperature distribution on the belt (10) becomes highest at the central portion near the heater (9) and becomes lower toward both ends. This belt (10)
When a circuit board (not shown) to be soldered is placed on and moved, the circuit board is gradually heated to the soldering temperature as it moves from the end portion to the central portion of the belt (10). Soldering is performed at the center of the belt (10), and the belt (10) is gradually cooled as it moves from the center to the end.
従来の半導体の実装方法では、以下に述べる問題点があ
った。回路基板はその底面から全体がはんだの融点（例
えばSn/Pb＝60/40の場合、230℃程度）を超えるまで加
熱されることになり、回路基板上にはんだ付け温度での
耐熱性を持たない回路素子や樹脂コーティング等が存在
する時には適用できず、また、回路基板が加熱されるた
め回路基板にそりが発生するなどの問題点があった。さ
らに、はんだ付けを行うため、はんだが付着可能で、か
つ強度的にも十分な導体材料を選定する必要があった。
このため、工程が複雑になったり、コスト面や信頼性に
おいて好ましくない場合があった。The conventional semiconductor mounting method has the following problems. The entire circuit board will be heated from its bottom surface until it exceeds the melting point of the solder (for example, about 230 ° C for Sn / Pb = 60/40), and it has heat resistance at the soldering temperature on the circuit board. There is a problem that it cannot be applied when there is no circuit element or resin coating, and the circuit board is heated, so that the circuit board is warped. Further, since soldering is performed, it is necessary to select a conductor material that is capable of attaching solder and has sufficient strength.
For this reason, the process may be complicated, and the cost and reliability may not be preferable.
この発明はかかる問題点を解消するためになされたもの
で、はんだ付け温度での耐熱性を持たない回路素子、電
子部品や樹脂コーティング等を有する回路基板にも適用
でき、また加熱により発生する回路基板のそりが起こら
ず、信頼性、生産性が高く、かつ低コストで、回路基板
に半導体素子を実装できる半導体実装方法を提供するこ
とを目的とする。The present invention has been made to solve the above problems, and can be applied to a circuit element having no heat resistance at a soldering temperature, a circuit board having an electronic component or a resin coating, and a circuit generated by heating. It is an object of the present invention to provide a semiconductor mounting method capable of mounting a semiconductor element on a circuit board at a low cost, with high reliability and high productivity without warping of the board.
この発明に係る半導体実装方法は、電極が形成された半
導体素子と導体パターンが形成された回路基板を、導体
パターンと電極とが接触するように位置合わせして配置
する工程、位置合わせされた半導体素子のほぼ全体を被
覆し、かつ回路基板の表面と接触するように絶縁性樹脂
を供給する工程、及び導体パターンと電極が接触した状
態で、供給された絶縁性樹脂を硬化する工程を施し、半
導体素子の電極と回路基板の導体パターンを電気的に接
続するものである。In the semiconductor mounting method according to the present invention, a step of arranging a semiconductor element having an electrode formed thereon and a circuit board having a conductor pattern so that the conductor pattern and the electrode are in contact with each other, and the aligned semiconductor is arranged. Performing a step of covering almost the entire element and supplying an insulating resin so as to contact the surface of the circuit board, and a step of curing the supplied insulating resin in a state where the conductor pattern and the electrode are in contact with each other, The electrode of the semiconductor element and the conductor pattern of the circuit board are electrically connected.
この発明における絶縁性樹脂をはんだ付けのように高温
に加熱しなくても、硬化可能であり、回路基板と位置合
わせして配置された半導体素子を、半導体素子の電極と
回路基板の導体パターンが接触した状態で固定し、電気
的接続を達成する作用を有する。Even if the insulating resin according to the present invention is not heated to a high temperature like soldering, it can be cured, and the semiconductor element arranged in alignment with the circuit board has electrodes of the semiconductor element and a conductor pattern of the circuit board. It has the function of fixing in contact with each other and achieving electrical connection.
以下、この発明の一実施例による半導体実装方法を第１
図及び第２図に基づいて説明する。図において、（１）
は半導体素子で、例えばフリップチップIC、（２）はフ
リップチップIC（１）の表面に形成されたはんだ突起電
極、（３）はフリップチップIC（１）を搭載する回路基
板、（４）は回路基板（３）に形成された導体パターン
でフリップチップIC（１）のはんだ突起電極（２）と接
続される回路基板電極、（５）は絶縁性樹脂、（６）は
絶縁性樹脂、（５）を供給する絶縁性樹脂供給管であ
る。まず、第１図に示すように、フリップチップIC
（１）のはんだ突起電極（２）と回路基板電極（４）を
位置合わせして配置する。次に第２図に示すように、フ
リップチップIC（１）に絶縁性樹脂供給（６）により、
回路基板（３）と接触し、かつ、フリップチップIC
（１）のほぼ全体を被覆するように絶縁性樹脂（５）を
供給する。この絶縁性樹脂（５）は樹脂硬化の際に体積
収縮をおこすものを用いており、この場合は熱硬化型‐
液性エポキシ樹脂である。次にこの絶縁性樹脂（５）を
硬化させることにより、フリップチップIC（１）が回路
基板電極（４）上に固定され、かつ絶縁性樹脂（５）が
硬化時に収縮する。この実施例で使用したエポキシ樹脂
（５）の硬化収縮率は0.7％程度であり、このため絶縁
性樹脂（５）の硬化収縮によって、フリップチップIC
（１）を第２図における矢印Ａ方向に押し付ける収縮力
が発生する。この収縮力によりフリップチップIC（１）
のはんだ突起電極（２）が回路基板電極（４）に圧接さ
れ、回路基板（３）とフリップチップIC（１）の電気的
接続が得られ、実装が達成される。この場合、上記絶縁
性樹脂（５）がフリップチップIC（１）の保護モールド
の役割も果たすので、信頼性を向上できる効果も有す
る。以上述べたように、回路基板（３）とフリップチッ
プIC（１）を樹脂硬化温度で実装でき、適当な硬化温度
の樹脂を選択すればはんだ付け温度での耐熱性を持たな
い回路素子や樹脂コーティングを有する回路基板にも適
用できるなど適用の範囲が広くなる。A semiconductor mounting method according to an embodiment of the present invention will be described below.
A description will be given with reference to FIGS. In the figure, (1)
Is a semiconductor element, for example, a flip chip IC, (2) is a solder bump electrode formed on the surface of the flip chip IC (1), (3) is a circuit board on which the flip chip IC (1) is mounted, and (4) is A circuit board electrode connected to the solder bump electrode (2) of the flip chip IC (1) by a conductor pattern formed on the circuit board (3), (5) an insulating resin, (6) an insulating resin, ( Insulating resin supply pipe for supplying 5). First, as shown in FIG. 1, a flip chip IC
The solder bump electrode (2) of (1) and the circuit board electrode (4) are aligned and arranged. Next, as shown in FIG. 2, by supplying insulating resin (6) to the flip chip IC (1),
Flip chip IC that contacts circuit board (3)
The insulating resin (5) is supplied so as to cover almost all of (1). The insulating resin (5) used is one that causes volume contraction when the resin is cured. In this case, a thermosetting resin-
It is a liquid epoxy resin. Next, by curing the insulating resin (5), the flip chip IC (1) is fixed on the circuit board electrode (4), and the insulating resin (5) contracts during curing. The curing shrinkage of the epoxy resin (5) used in this example is about 0.7%. Therefore, the curing shrinkage of the insulating resin (5) causes a flip chip IC.
A contracting force for pressing (1) in the direction of arrow A in FIG. 2 is generated. Flip chip IC (1)
The solder bump electrode (2) is pressed against the circuit board electrode (4), and the circuit board (3) and the flip chip IC (1) are electrically connected, and the mounting is achieved. In this case, since the insulating resin (5) also serves as a protective mold for the flip chip IC (1), it also has the effect of improving reliability. As described above, the circuit board (3) and the flip-chip IC (1) can be mounted at a resin curing temperature, and if a resin having an appropriate curing temperature is selected, a circuit element or a resin that does not have heat resistance at the soldering temperature. The range of application is broadened, such as application to a circuit board having a coating.
さらに、回路基板（３）上の導体パターンを構成する導
体は通常のはんだ付けの困難なアルミニウム,ITO（Indi
um-Tin-Oxide），クロムなど多くの材料を使用できる。Furthermore, the conductors forming the conductor pattern on the circuit board (3) are made of aluminum, ITO (Indi
Many materials such as um-Tin-Oxide) and chromium can be used.
以下、更にこの一実施例を詳しく説明する。4mm×4mmの
チップに40個の、例えば電極サイズは160μｍφ程度の
はんだ突起電極が形成されたフリップチップIC（１）の
はんだ突起電極（２）と回路基板として例えばガラス基
板（３）上に、導体パターンとして蒸着法により形成さ
れた銅の薄膜電極（４）を位置決めし、エポキシ系絶縁
性樹脂（５）をフリップチップIC（１）に供給した後硬
化させ、回路基板（３）とフリップチップIC（１）を電
気的に接続した試驗片を作った。比較品として上記と同
一のフリップチップIC（１）と回路基板（３）を用い
て、回路基板（３）にフリップチップIC（１）をはんだ
付けした試驗片を作った。これらの試驗片をオーブンで
室温から100℃まで加熱した時の１つの回路基板電極
（４）とフリップチップICのはんだ突起電極（２）の導
通抵抗の変化を測定した。横軸に温度（℃）、縦軸に導
通抵抗（Ω）として第３図に示し、直線Ｂははんだ付け
によるもの、直線Ｃはこの発明の一実施例によるもので
ある。第３図に示されるように、上記実施例（Ｃ）の方
がはんだ付け（Ｂ）よりも接続抵抗が低く、良好な結果
が得られた。以上のように、この発明の一実施例によれ
ば、信頼性の高い、回路基板とフリップチップICの実装
方法を得ることができる。Hereinafter, this embodiment will be described in detail. For example, on a solder bump electrode (2) of a flip chip IC (1) in which 40 solder bump electrodes having an electrode size of about 160 μmφ are formed on a 4 mm × 4 mm chip and a glass substrate (3) as a circuit board, A copper thin film electrode (4) formed by a vapor deposition method as a conductor pattern is positioned, an epoxy-based insulating resin (5) is supplied to the flip chip IC (1) and then cured, and the circuit board (3) and the flip chip are then cured. A test piece was made by electrically connecting the IC (1). As a comparative product, the same flip chip IC (1) and circuit board (3) as described above were used to make a test piece by soldering the flip chip IC (1) to the circuit board (3). The change in conduction resistance between one circuit board electrode (4) and the solder bump electrode (2) of the flip chip IC was measured when these test pieces were heated in an oven from room temperature to 100 ° C. The temperature (° C.) is plotted along the horizontal axis and the conduction resistance (Ω) is plotted along the vertical axis in FIG. 3. The straight line B is for soldering, and the straight line C is for one embodiment of the present invention. As shown in FIG. 3, the example (C) had a lower connection resistance than the soldering (B), and good results were obtained. As described above, according to the embodiment of the present invention, it is possible to obtain a highly reliable mounting method of a circuit board and a flip chip IC.
また、この発明の他の実施例を第４図に示す。第４図に
おいて（７）はフリップチップIC（１）を加圧する加圧
具であり、（１）〜（６）は第２図と同様又は相当のも
のである。上記実施例と同様に、フリップチップIC
（１）を回路基板（３）上にはさんだ突起電極（２）と
回路基板電極（４）とが接触するように位置決めした
後、加圧具（７）によってフリップチップIC（１）を回
路基板（３）に押圧する。このはさんだ突起電極（２）
と回路基板電極（４）とを圧接した状態で、絶縁性樹脂
供給管（６）で絶縁性樹脂（５）を供給し硬化させる。
絶縁性樹脂（５）が硬化後、加圧具（７）をa-a′の位
置で切断する事により、回路基板（３）にフリップチッ
プIC（１）を実装するものである。この実施例によれば
はんだ突起電極（２）に大きさのバラツキが有っても、
はんだ突起電極（２）はやわらかいため、加圧具（７）
による加圧によってはんだ突起電極（２）の大きい部分
がつぶれて、このバラツキを吸収する。このため、安定
した電気的接続が可能となる。さらに絶縁性樹脂の収縮
力に加えて加圧具（７）による加圧力がプラスされるた
め、回路基板電極（４）とフリップチップIC（１）のは
んだ突起電極（２）の圧接力が増加し、回路基板（３）
とフリップチップIC（１）の導通抵抗を下げることがで
き、一層接続の信頼性が向上できる。さらに、フリップ
チップIC（１）に接触した加圧具（７）を残すことによ
り、加圧具（７）の一部は冷却フィンとして機能し、駆
動時のフリップチップIC（１）の温度上昇を抑えること
ができ、信頼性が大幅に改善される。Another embodiment of the present invention is shown in FIG. In FIG. 4, (7) is a pressing tool for pressing the flip chip IC (1), and (1) to (6) are the same as or equivalent to those in FIG. Similar to the above embodiment, flip chip IC
After positioning (1) on the circuit board (3) so that the protruding electrode (2) and the circuit board electrode (4) are in contact with each other, the flip chip IC (1) is circuitized by a pressing tool (7). Press on the substrate (3). This sandwiched protruding electrode (2)
While the circuit board electrode (4) and the circuit board electrode (4) are in pressure contact with each other, the insulating resin (5) is supplied and cured by the insulating resin supply pipe (6).
After the insulating resin (5) is cured, the pressure tool (7) is cut at the position aa 'to mount the flip chip IC (1) on the circuit board (3). According to this embodiment, even if the solder bump electrodes (2) have variations in size,
Since the solder bump electrode (2) is soft, the pressure tool (7)
The large portion of the solder bump electrode (2) is crushed by the pressurization by, and this variation is absorbed. Therefore, stable electrical connection is possible. Further, in addition to the contracting force of the insulating resin, the pressure applied by the pressure tool (7) is added, so that the pressure contact force between the circuit board electrode (4) and the solder bump electrode (2) of the flip chip IC (1) increases. And circuit board (3)
Therefore, the conduction resistance of the flip chip IC (1) can be reduced, and the connection reliability can be further improved. Further, by leaving the pressurizing tool (7) in contact with the flip chip IC (1), a part of the pressurizing tool (7) functions as a cooling fin, and the temperature rise of the flip chip IC (1) during driving. Can be suppressed, and the reliability is greatly improved.
なおまた、複数個の絶縁性樹脂供給管を使用して、回路
基板（３）にフリップチップIC（１）を実装することが
できる。例えば、実装する半導体素子に対応して樹脂成
分の異なる絶縁性樹脂を別の絶縁性樹脂供給管で供給で
き、半導体素子接続の信頼性を高めることができる。Furthermore, the flip-chip IC (1) can be mounted on the circuit board (3) by using a plurality of insulating resin supply pipes. For example, an insulating resin having a different resin component can be supplied through another insulating resin supply pipe corresponding to the mounted semiconductor element, and the reliability of semiconductor element connection can be improved.
なおさらに、半導体素子の大きさ等に応じ、絶縁性樹脂
の供給量を変える事により、絶縁性樹脂（５）の硬化時
の収縮力すなわち回路基板（３）と半導体素子（１）の
圧接力を半導体素子（１）に対応して最適化でき、回路
基板（３）と半導体素子（１）の高信頼の実装が得られ
る。さらに、圧接界面のずれによって半導体素子に加わ
る水平方向の応力緩和の効果も期待できる。Furthermore, by changing the supply amount of the insulating resin according to the size of the semiconductor element, etc., the contracting force when the insulating resin (5) is cured, that is, the pressure contact force between the circuit board (3) and the semiconductor element (1). Can be optimized corresponding to the semiconductor element (1), and highly reliable mounting of the circuit board (3) and the semiconductor element (1) can be obtained. Furthermore, the effect of relaxing the stress in the horizontal direction applied to the semiconductor element due to the displacement of the pressure contact interface can be expected.
また、他の実施例として半導体の裏面側、即ち電極が形
成された面と反対の両側に、この半導体素子の裏面より
も面積の広い平板を接触させた状態で絶縁性樹脂（５）
を供給し、硬化すれば半導体素子（１）と回路基板
（３）との間に作用する圧力が増加し、安定な接続が得
られる。また、この平板の面積を変えることにより、圧
力を調整することもできる。As another embodiment, an insulating resin (5) is used in a state where a flat plate having a larger area than the back surface of the semiconductor element is in contact with the back surface side of the semiconductor, that is, both sides opposite to the surface on which the electrodes are formed.
When it is supplied and cured, the pressure acting between the semiconductor element (1) and the circuit board (3) increases, and a stable connection can be obtained. The pressure can also be adjusted by changing the area of this flat plate.
また、絶縁性樹脂（５）として熱硬化型で熱膨張係数が
正の値を有する樹脂を使用した場合について説明する。
150℃で硬化した後常温まで冷却すると樹脂の冷却によ
る収縮により半導体（１）と回路基板（３）の間の圧力
は増加する。このようにすることにより120℃以下程度
までは半導体素子（１）と回路基板（３）との間に電気
的接続を安定に保持する圧力が加わるため、温度サイク
ル試驗においても極めて安定な信頼性の高い接続が得ら
れる。さらに、常温硬化型の樹脂でも、硬化時の半導体
素子（１）と回路基板（３）との間の圧力が十分得られ
れば、高温時の接続部の安定性は高い。A case where a thermosetting resin having a positive coefficient of thermal expansion is used as the insulating resin (5) will be described.
When the resin is cured at 150 ° C. and then cooled to room temperature, the pressure between the semiconductor (1) and the circuit board (3) increases due to shrinkage of the resin due to cooling. By doing so, pressure up to about 120 ° C or less is applied between the semiconductor element (1) and the circuit board (3) in order to maintain a stable electrical connection, and therefore extremely stable reliability even in a temperature cycle test. High connection. Furthermore, even with a room temperature curable resin, if the pressure between the semiconductor element (1) and the circuit board (3) at the time of curing is sufficiently obtained, the stability of the connection portion at high temperature is high.
さらに、絶縁性樹脂（５）を半導体素子の電極（２）と
回路基板上の導体パターン（４）の圧接部分には存在し
ないようにすることにより、圧接界面への樹脂（５）の
侵入などを防ぎ、更に安定で信頼性の高い電気的接続が
得られる。Furthermore, by preventing the insulating resin (5) from existing in the pressure contact portion between the electrode (2) of the semiconductor element and the conductor pattern (4) on the circuit board, the resin (5) may enter the pressure contact interface. And a stable and reliable electrical connection can be obtained.
また、半導体素子（１）としてはんだバンプのフリップ
チップICの場合を主として述べてきたが、金バンプでも
よく、さらに回路基板（３）に突起電極を形成すればベ
アチップ（電極はアルミニウムパッド）でもよい。さら
に回路基板（３）として蒸着法により薄膜電極（４）が
形成されたガラス基板について実施例で詳細に述べた
が、めっきやスペッタ法によって成膜された基板、厚膜
導体（例えば銀パラジウム導体）が形成されたセラミッ
ク基板、ガラスエポキシ基板等の回路基板についても同
様の効果を奏する。Further, although the semiconductor chip (1) has been mainly described in the case of a flip chip IC of a solder bump, it may be a gold bump, or a bare chip (the electrode is an aluminum pad) if a protruding electrode is formed on the circuit board (3). . Further, the glass substrate on which the thin film electrode (4) is formed by the vapor deposition method as the circuit board (3) has been described in detail in the examples. The substrate formed by plating or the sputter method, the thick film conductor (eg, silver palladium conductor). The same effect can be obtained also on a circuit board such as a ceramic board or a glass epoxy board on which a) is formed.
以上述べたように、この発明によれば、電極が形成され
た半導体素子と導体パターンが形成された回路基板を、
導体パターンと電極とが接触するように位置合わせして
配置する工程、位置合わせされた半導体素子のほぼ全体
を被覆し、かつ回路基板の表面と接触するように絶縁性
樹脂を供給する工程、及び導体パターンと電極が接触し
た状態で供給された絶縁性樹脂を硬化する工程を施し、
半導体素子の電極と回路基板の導体パターンを電気的に
接続することにより、耐熱温度の低い回路素子や樹脂コ
ーティング等を有する回路基板にも適用できる。さら
に、絶縁性樹脂が半導体素子の保護モールドの役割をす
るため、信頼性、生産性が高く、かつ低コストで半導体
素子を回路基板に実装できる半導体実装方法が得られる
効果がある。As described above, according to the present invention, the semiconductor element on which the electrode is formed and the circuit board on which the conductor pattern is formed are
A step of arranging so that the conductor pattern and the electrode are in contact with each other, a step of covering almost the entire aligned semiconductor element and supplying an insulating resin so as to be in contact with the surface of the circuit board, and Performing a step of curing the insulating resin supplied with the conductor pattern and the electrode in contact,
By electrically connecting the electrodes of the semiconductor element and the conductor pattern of the circuit board, it can be applied to a circuit element having a low heat resistant temperature or a circuit board having a resin coating or the like. Further, since the insulating resin serves as a protective mold for the semiconductor element, there is an effect that a semiconductor mounting method that has high reliability and high productivity and can mount the semiconductor element on a circuit board at low cost can be obtained.
第１図はこの発明の一実施例による半導体実装方法に係
り、回路基板と半導体素子を位置合わせして配置した工
程の接続部周辺を示す側面図、第２図は同じく絶縁性樹
脂を供給した工程の接続部周辺を示す断面図、第３図は
この発明の一実施例によって得られた接続部と従来の方
法による接続部の温度に対する導通抵抗を比較して示す
特性図、第４図はそれぞれこの発明の他の実施例に係る
工程途中の接続部周辺を示す断面図、第５図は従来の半
導体実装方法に係るリフロー装置を示す断面図である。 （１）……半導体素子、（２）……電極、（３）……回
路基板、（４）……導体パターン、（５）……絶縁性樹
脂。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 relates to a semiconductor mounting method according to an embodiment of the present invention, and is a side view showing the periphery of a connection portion in a process of aligning a circuit board and a semiconductor element, and FIG. 2 is also supplied with an insulating resin. FIG. 4 is a cross-sectional view showing the periphery of the connection portion in the process, FIG. 3 is a characteristic diagram showing the comparison of the conduction resistance with respect to temperature of the connection portion obtained by one embodiment of the present invention and the connection portion by the conventional method, and FIG. FIG. 5 is a cross-sectional view showing the periphery of a connection portion during a process according to another embodiment of the present invention, and FIG. 5 is a cross-sectional view showing a reflow device according to a conventional semiconductor mounting method. (1) ... Semiconductor element, (2) ... Electrode, (3) ... Circuit board, (4) ... Conductor pattern, (5) ... Insulating resin. In the drawings, the same reference numerals indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 高砂 隼人 兵庫県尼崎市塚口本町８丁目１番１号 三 菱電機株式会社材料研究所内 (56)参考文献 特開 昭62−281360（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hayato Takasago 8-1-1 Tsukaguchi Honcho, Amagasaki City, Hyogo Prefecture Sanryo Electric Co., Ltd. Material Research Laboratory (56) Reference JP-A-62-281360 (JP, A)
Claims (7)
ンが形成された回路基板を、上記導体パターンと上記電
極とが接触するように位置合わせして配置する工程、上
記位置合わせされた半導体素子のほぼ全体を被覆し、か
つ上記回路基板の表面と接触するように絶縁性樹脂を供
給する工程、及び上記導体パターンと上記電極が接触し
た状態で、上記供給された絶縁性樹脂を硬化する工程を
施し、上記半導体素子の電極と上記回路基板の導体パタ
ーンを電気的に接続することを特徴とする半導体実装方
法。1. A step of arranging a semiconductor element having an electrode formed thereon and a circuit board having a conductor pattern aligned so that the conductor pattern and the electrode are in contact with each other, and the aligned semiconductor element. Of supplying the insulating resin so as to cover almost the entire surface of the circuit board and contacting the surface of the circuit board, and curing the supplied insulating resin in the state where the conductor pattern and the electrode are in contact with each other. And electrically connecting the electrodes of the semiconductor element to the conductor patterns of the circuit board.
置する工程の後、上記半導体素子と上記回路基板間を加
圧具を用いて加圧した状態で、上記加圧具と半導体素子
と回路基板に付着するように絶縁性樹脂を供給する工
程、上記供給した絶縁性樹脂を硬化させる工程、及び上
記絶縁性樹脂の硬化した後上記加圧具を切断する工程を
施すようにしたことを特徴とする特許請求の範囲第１項
記載の半導体実装方法。2. After the step of aligning and arranging the semiconductor element and the circuit board, the pressure tool and the semiconductor element are pressed with a pressure tool between the semiconductor element and the circuit board. The step of supplying the insulating resin so as to adhere to the circuit board, the step of curing the supplied insulating resin, and the step of cutting the pressure tool after the insulating resin is cured are performed. The semiconductor mounting method according to claim 1, which is characterized in that.
電極が変形する程度に加圧した状態で、絶縁性樹脂を供
給する工程を施すようにしたことを特徴とする特許請求
の範囲第２項記載の半導体実装方法。3. A step of supplying an insulating resin is carried out in a state where a pressure is applied between the semiconductor element and the circuit board to such an extent that the electrodes are deformed. A semiconductor mounting method according to claim 2.
る樹脂であることを特徴とする特許請求の範囲第１項な
いし第３項のいずれかに記載の半導体実装方法。4. The semiconductor mounting method according to claim 1, wherein the insulating resin is a resin that undergoes volume contraction upon curing.
正の値を有する樹脂であることを特徴とする特許請求の
範囲第１項ないし第３項のいずれかに記載の半導体実装
方法。5. The semiconductor according to claim 1, wherein the insulating resin is a thermosetting resin having a positive coefficient of thermal expansion. How to implement.
とを特徴とする特許請求の範囲第１項ないし第４項のい
ずれかに記載の半導体実装方法。6. The semiconductor mounting method according to any one of claims 1 to 4, wherein the insulating resin is a room temperature curable resin.
の面よりも面積の広い平板を接触させた状態で絶縁性樹
脂を供給する工程、及び上記供給した絶縁性樹脂を硬化
させる工程を施すようにしたことを特徴とする特許請求
の範囲第１項ないし第６項のいずれかに記載の半導体実
装方法。7. A step of supplying an insulating resin to a surface of a semiconductor element opposite to an electrode forming surface in contact with a flat plate having an area larger than this surface, and a step of curing the supplied insulating resin. The semiconductor mounting method according to any one of claims 1 to 6, wherein:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072245A JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
| US07/363,710 US4942140A (en) | 1987-03-25 | 1989-06-09 | Method of packaging semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072245A JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237426A JPS63237426A (en) | 1988-10-03 |
| JPH0671026B2 true JPH0671026B2 (en) | 1994-09-07 |
Family
ID=13483715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62072245A Expired - Lifetime JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671026B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2558512B2 (en) * | 1988-10-19 | 1996-11-27 | 松下電器産業株式会社 | Semiconductor device |
| JP3037229B2 (en) | 1997-10-23 | 2000-04-24 | 新潟日本電気株式会社 | Bare chip mounting method and mounting device |
| WO2006123554A1 (en) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | Flip-chip mounting body and flip-chip mounting method |
| JP5830847B2 (en) * | 2010-10-21 | 2015-12-09 | 富士通株式会社 | Semiconductor device manufacturing method and bonding method |
| US10104772B2 (en) | 2014-08-19 | 2018-10-16 | International Business Machines Incorporated | Metallized particle interconnect with solder components |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62281360A (en) * | 1986-05-29 | 1987-12-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-03-25 JP JP62072245A patent/JPH0671026B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63237426A (en) | 1988-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4942140A (en) | Method of packaging semiconductor device | |
| US6498051B1 (en) | Method of packaging semiconductor device using anisotropic conductive adhesive | |
| US6825552B2 (en) | Connection components with anisotropic conductive material interconnection | |
| US5861678A (en) | Method and system for attaching semiconductor dice to substrates | |
| TWI400013B (en) | Surface mounted chip resistor with flexible leads and manufacturing method thereof | |
| JPH027180B2 (en) | ||
| JP5198265B2 (en) | Apparatus and method for forming a flat surface of a thin flexible substrate | |
| KR100517010B1 (en) | The flip chip bonding method using induction heating body in the AC magnetic field and the apparatus which uses the same method | |
| JPH0671026B2 (en) | Semiconductor mounting method | |
| JPH1187429A (en) | Semiconductor chip mounting method | |
| JP2903697B2 (en) | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus | |
| JP2574369B2 (en) | Semiconductor chip mounted body and mounting method thereof | |
| JPH0666355B2 (en) | Semiconductor device mounting body and mounting method thereof | |
| JPH08222599A (en) | Electronic component mounting method | |
| JPH11163054A (en) | Semiconductor device structure and method of manufacturing the same | |
| JPH01226162A (en) | Connection of semiconductor chip | |
| JP2847954B2 (en) | Method for manufacturing semiconductor device | |
| JP3425531B2 (en) | Electronic circuit device and method of manufacturing the same | |
| JPH03129745A (en) | Mounting of semiconductor device | |
| JPH06103701B2 (en) | Semiconductor device mounting body | |
| JP3408971B2 (en) | Carrier for flip chip mounting | |
| JPH04119644A (en) | Mounting of semicondctor element | |
| JPH0744199B2 (en) | Semiconductor device mounting body and mounting method thereof | |
| JPH02188936A (en) | Semiconductor device and manufacture thereof | |
| JPH04240741A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070907 Year of fee payment: 13 |