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JPH0671028B2 - Semiconductor element mounting method - Google Patents
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JPH0671028B2 - Semiconductor element mounting method - Google Patents

Semiconductor element mounting method

Info

Publication number
JPH0671028B2
JPH0671028B2 JP63178083A JP17808388A JPH0671028B2 JP H0671028 B2 JPH0671028 B2 JP H0671028B2 JP 63178083 A JP63178083 A JP 63178083A JP 17808388 A JP17808388 A JP 17808388A JP H0671028 B2 JPH0671028 B2 JP H0671028B2
Authority
JP
Japan
Prior art keywords
semiconductor element
load
insulating resin
lsi chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63178083A
Other languages
Japanese (ja)
Other versions
JPH0228946A (en
Inventor
博昭 藤本
賢造 畑田
岳雄 越智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63178083A priority Critical patent/JPH0671028B2/en
Publication of JPH0228946A publication Critical patent/JPH0228946A/en
Publication of JPH0671028B2 publication Critical patent/JPH0671028B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、マイクロコンピュータやゲートアレイ等の多
電極、狭ピッチのLSIチップの実装に関するものであ
る。
TECHNICAL FIELD The present invention relates to mounting of a multi-electrode, narrow-pitch LSI chip such as a microcomputer or a gate array.

(従来の技術) 従来の技術を第2図に基づいて説明する。第2図(a)
に示すように、セラミックスガラス等よりなる配線基板
11の導体配線12を有する面に、絶縁性樹脂13を塗布す
る。導体配線12はCr-Au,Al,TiO等であり、絶縁性樹脂13
は熱硬化性あるいは紫外線硬化性のエポキシ樹脂,アク
リル樹脂等である。次に、第2図(b)に示すように、
Au等よりなる突起電極14を有したLSIチップ15を、突起
電極14と導体配線12の位置が一致するように配線基板11
の絶縁性樹脂13が塗布された領域に配置し、加圧ツール
16でLSIチップ15を加圧する。このとき、加圧する荷重
は突起電極14の厚さのバラツキ、および配線基板11の平
面度を突起電極14の変形量で量で吸収できる大きさに設
定する。また、このとき、絶縁性樹脂13は周囲に押し出
され、LSIチップ15の突起電極14と導体配線12は電気的
に接触する。次に、加圧ツール16をLSIチップ15に加圧
した状態で絶縁性樹脂13を硬化し、第2図(C)に示す
ように、加圧ツール16を解除する。このとき、LSIチッ
プ15は配線基板11に絶縁性樹脂13により固着されるとと
もに、LSIチップ15の突起電極14と導体配線12は接触に
より電気的に接続される。
(Conventional Technology) A conventional technology will be described with reference to FIG. Fig. 2 (a)
As shown in, the wiring board made of ceramic glass, etc.
An insulating resin 13 is applied to the surface of the conductor wiring 12 having the conductor wiring 12. Conductor wiring 12 is made of Cr-Au, Al, TiO, etc., and insulating resin 13
Is a thermosetting or ultraviolet curable epoxy resin, acrylic resin, or the like. Next, as shown in FIG. 2 (b),
The LSI chip 15 having the protruding electrodes 14 made of Au or the like is placed on the wiring board 11 so that the positions of the protruding electrodes 14 and the conductor wirings 12 are aligned.
Place the insulating resin 13 in the area coated with
The LSI chip 15 is pressurized at 16. At this time, the load to be applied is set to a size that can absorb the variation in the thickness of the protruding electrode 14 and the flatness of the wiring substrate 11 by the amount of deformation of the protruding electrode 14. Further, at this time, the insulating resin 13 is pushed out to the surroundings, and the protruding electrodes 14 of the LSI chip 15 and the conductor wirings 12 electrically contact with each other. Next, the insulating resin 13 is cured while the pressure tool 16 is pressed against the LSI chip 15, and the pressure tool 16 is released as shown in FIG. 2 (C). At this time, the LSI chip 15 is fixed to the wiring board 11 with the insulating resin 13, and the protruding electrode 14 of the LSI chip 15 and the conductor wiring 12 are electrically connected by contact.

(発明が解決しようとする課題) 上記従来の技術では、LSIチップに突起電極の厚さのバ
ラツキ、配線基板の平面度を突起電極の変形量で吸収で
きる荷重を加えた状態、すなわち非常に大きい荷重を加
えた状態で絶縁性樹脂を硬化するため、LSIチップおよ
び配線基板の残留歪が大きく、後にその歪が少なくなる
ように作用するため、LSIチップの特性劣化、高温およ
び高湿中での絶縁性樹脂の剥離による接続不良が生じる
欠点があった。
(Problems to be Solved by the Invention) In the above conventional technique, the LSI chip is subjected to a variation in the thickness of the protruding electrode and a load capable of absorbing the flatness of the wiring board by the deformation amount of the protruding electrode, that is, a very large amount. Since the insulating resin is cured under load, the residual strain of the LSI chip and wiring board is large, and it acts to reduce the strain later.Therefore, deterioration of the characteristics of the LSI chip, high temperature and high humidity There is a defect that a connection failure occurs due to peeling of the insulating resin.

本発明の目的は、従来の欠点を解消し、絶縁性樹脂を硬
化するとき、LSIチップ等の半導体素子および基板に歪
が生ぜず、LSIチップの特性劣化や接続不良が生じない
半導体素子の実装方法を提供することである。
The object of the present invention is to eliminate the conventional drawbacks, and when the insulating resin is cured, the semiconductor element such as the LSI chip and the substrate are not distorted, and the characteristics of the LSI chip and the connection of the semiconductor element are prevented from causing a connection failure. Is to provide a method.

(課題を解決するための手段) 本発明の半導体素子の実装方法は、LSIチップ等の半導
体素子を高荷重で加圧し、突起電極の変形量を突起電極
の厚さのバラツキ、および配線基板の平面度を吸収でき
る量としておき、そののち、加圧ツールを半導体素子に
接触させた状態で荷重を導体素子および配線基板の歪が
生じない低い値に再設定し、その状態で絶縁性樹脂を硬
化するものである。
(Means for Solving the Problem) A method for mounting a semiconductor element of the present invention is to apply pressure to a semiconductor element such as an LSI chip with a high load to change the amount of deformation of the protruding electrode by varying the thickness of the protruding electrode, and The flatness is set to an amount that can be absorbed, and then the load is reset to a low value that does not cause distortion of the conductor element and wiring board while the pressure tool is in contact with the semiconductor element. It hardens.

(作用) 本発明によれば、絶縁性樹脂を硬化するときの荷重が非
常に低いため、LSIチップ等の半導体素子および基板に
歪が発生せず、後でLSIチップの特性劣化や接続不良が
生ずる恐れがない。
(Operation) According to the present invention, since the load when curing the insulating resin is very low, distortion does not occur in the semiconductor element such as the LSI chip and the substrate, and the characteristic deterioration and connection failure of the LSI chip later occur. There is no fear of it occurring.

(実施例) 本発明の一実施例を第1図に基づいて説明する。第1図
は、本発明の半導体素子の実装工程を示す断面図であ
る。第1図(a)において、ガラス,セラミックス等よ
りなり、導体配線1を有した配線基板2の導体配線1を
含む領域に絶縁性樹脂3を塗布する。配線基板2の厚さ
は0.1〜2.0mm程度であり、導体配線1はCr-Au,Al,TiO等
であり、その厚さは0.1〜10μm程度である。絶縁性樹
脂3はアクリル樹脂,エポキシ樹脂等の光硬化型であ
り、塗布はディスペンサー,印刷等を用いる。次に、第
1図(b)に示すように、Au,Cu,Al,In合金等よりなる
突起電極4を有したLSIチップ5を、突起電極4と導体
配線1の位置が一致するように、配線基板2の絶縁性樹
脂3が塗布された領域に設置する。突起電極4の厚さは
5〜30μ程度であり、その寸法は3〜50μ程度であ
る。
(Example) An example of the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing a mounting process of a semiconductor device of the present invention. In FIG. 1 (a), an insulating resin 3 is applied to a region including a conductor wiring 1 of a wiring board 2 having a conductor wiring 1 and made of glass, ceramics or the like. The wiring board 2 has a thickness of about 0.1 to 2.0 mm, the conductor wiring 1 is made of Cr-Au, Al, TiO, etc., and the thickness thereof is about 0.1 to 10 μm. The insulating resin 3 is a photo-curable type such as acrylic resin or epoxy resin, and is applied by using a dispenser, printing or the like. Next, as shown in FIG. 1B, the LSI chip 5 having the protruding electrode 4 made of Au, Cu, Al, In alloy or the like is placed so that the protruding electrode 4 and the conductor wiring 1 are aligned with each other. The wiring board 2 is installed in the area where the insulating resin 3 is applied. The protruding electrode 4 has a thickness of about 5 to 30 μm and a size of about 3 to 50 μ 2 .

次に、加圧ツール6で、第1の荷重7によりLSIチップ
5を加圧する。第1の荷重7の設定は、突起電極4の加
圧の際の変形量で、突起電極4の厚さのバラツキ、およ
び配線基板2の平面度を吸収する値にする必要がある。
突起電極4の変形量は通常1〜5μ程度であり、第1の
荷重7は、例えば0.5g/突起電極〜30g/突起電極であ
る。このとき、第1の荷重7は非常に大きいため、LSI
チップ5および配線基板2にはそりおよび歪が生じる。
また、このとき、絶縁性樹脂3は周囲に押し出され、LS
Iチップ5の突起電極4と導体配線1は電気的に接触す
る。次に、加圧ツール6をLSIチップ5に接触させた状
態で、荷重LSIチップ5および配線基板2のそりおよび
歪が生じなくなる第2の荷重8に設定する。第2の荷重
8は、例えば第1の荷重の1/3〜1/20程度である。
Next, the pressure tool 6 presses the LSI chip 5 with the first load 7. The setting of the first load 7 is a deformation amount at the time of pressurizing the protruding electrode 4, and needs to be a value that absorbs the variation in the thickness of the protruding electrode 4 and the flatness of the wiring board 2.
The deformation amount of the protruding electrode 4 is usually about 1 to 5 μ, and the first load 7 is, for example, 0.5 g / projecting electrode to 30 g / projecting electrode. At this time, since the first load 7 is very large, the LSI
Warpage and distortion occur in the chip 5 and the wiring board 2.
At this time, the insulating resin 3 is pushed out to the surroundings,
The protruding electrode 4 of the I-chip 5 and the conductor wiring 1 electrically contact with each other. Next, with the pressing tool 6 in contact with the LSI chip 5, a second load 8 is set so that warpage and distortion of the load LSI chip 5 and the wiring board 2 do not occur. The second load 8 is, for example, about 1/3 to 1/20 of the first load.

次に、LSIチップ5を、第2の荷重8で加圧ツール6に
より加圧した状態で絶縁性樹脂3を硬化する。硬化の方
法は、配線基板2がガラス等の透明基板の場合は、配線
基板2の裏面より紫外線を照射する。また、セラミック
ス等の不透明基板の場合は、LSIチップ5の側面より紫
外線を照射する。次に、第1図(c)に示すように、加
圧ツール6を解除する。このとき、LSIチップ5は配線
基板2に固着されると同時に、突起電極4と導体配線1
は接触により電気的に接続される。
Next, the insulating resin 3 is cured while the LSI chip 5 is pressed by the pressing tool 6 with the second load 8. As for the curing method, when the wiring substrate 2 is a transparent substrate such as glass, the back surface of the wiring substrate 2 is irradiated with ultraviolet rays. Further, in the case of an opaque substrate such as ceramics, ultraviolet rays are irradiated from the side surface of the LSI chip 5. Next, as shown in FIG. 1 (c), the pressure tool 6 is released. At this time, the LSI chip 5 is fixed to the wiring board 2 and at the same time, the protruding electrode 4 and the conductor wiring 1
Are electrically connected by contact.

なお、本発明においては、LSIチップに限らず他の種々
の半導体素子にも適用することができる。
The present invention can be applied not only to LSI chips but also to various other semiconductor elements.

(発明の効果) 本発明によれば、半導体素子の加圧時の荷重を、十分な
接触を得るための第1の高荷重と、LSIチップおよび配
線基板のそり、歪が生じない第2の低荷重の2段階に分
け、第2の低荷重のときに絶縁性樹脂を硬化するため、
半導体素子,配線基板にそり、歪が生ぜず、半導体素子
の特性が変化することなく、さらに、高温高湿中におい
ても、絶縁性樹脂の剥離が起こらず、高信頼性の接続が
得られ、その実用上の効果は極めて大である。
(Effects of the Invention) According to the present invention, the load when the semiconductor element is pressed is the first high load for obtaining a sufficient contact, and the second warp of the LSI chip and the wiring board which does not cause distortion. It is divided into two stages of low load, and in order to cure the insulating resin at the second low load,
The semiconductor element and the wiring board are not warped, the characteristics of the semiconductor element do not change, and the insulating resin does not peel off even in high temperature and high humidity, and a highly reliable connection can be obtained. The practical effect is extremely large.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例における半導体素子の実装工
程断面図、第2図は従来の技術による半導体素子の実装
工程断面図である。 1……導体配線、2……配線基板、3……絶縁性樹脂、
4……突起電極、5……LSIチップ、6……加圧ツー
ル、7……第1の荷重、8……第2の荷重。
FIG. 1 is a sectional view of a semiconductor element mounting process according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor element mounting process. 1 ... Conductor wiring, 2 ... Wiring board, 3 ... Insulating resin,
4 ... Projection electrode, 5 ... LSI chip, 6 ... Pressurizing tool, 7 ... First load, 8 ... Second load.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】導体配線を有する絶縁性基板の、前記導体
配線部に絶縁性樹脂を塗布する工程、前記導体配線と半
導体素子の電極の位置を一致させ、前記半導体素子を前
記絶縁性基板の絶縁性樹脂を塗布した領域に設置する工
程、前記半導体素子を加圧ツールにより第1の荷重で加
圧し、一定時間保持したのち、前記半導体素子を第1の
荷重より低い第2の荷重で加圧し、前記半導体素子の電
極と前記半導体配線を接触させ、前記半導体素子を加圧
した状態で前記絶縁性樹脂を硬化させ、前記半導体素子
を前記絶縁性基板に固着するとともに、前記導体配線と
半導体素子の電極を電気的に接続する工程を備えてなる
ことを特徴とする半導体素子の実装方法。
1. A step of applying an insulating resin to the conductor wiring portion of an insulating substrate having conductor wiring, the conductor wiring and the electrode of a semiconductor element are aligned with each other, and the semiconductor element is attached to the insulating substrate. In the step of installing in the region coated with the insulating resin, the semiconductor element is pressurized with a first load by a pressure tool and held for a certain period of time, and then the semiconductor element is applied with a second load lower than the first load. By pressing, the electrode of the semiconductor element and the semiconductor wiring are brought into contact with each other, and the insulating resin is cured while the semiconductor element is pressed, the semiconductor element is fixed to the insulating substrate, and the conductor wiring and the semiconductor A method for mounting a semiconductor device, comprising a step of electrically connecting electrodes of the device.
【請求項2】絶縁性樹脂を半導体素子の電極を有する面
に塗布した請求項(1)記載の半導体素子の実装方法。
2. The method of mounting a semiconductor element according to claim 1, wherein an insulating resin is applied to a surface of the semiconductor element having an electrode.
JP63178083A 1988-07-19 1988-07-19 Semiconductor element mounting method Expired - Fee Related JPH0671028B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63178083A JPH0671028B2 (en) 1988-07-19 1988-07-19 Semiconductor element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63178083A JPH0671028B2 (en) 1988-07-19 1988-07-19 Semiconductor element mounting method

Publications (2)

Publication Number Publication Date
JPH0228946A JPH0228946A (en) 1990-01-31
JPH0671028B2 true JPH0671028B2 (en) 1994-09-07

Family

ID=16042330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63178083A Expired - Fee Related JPH0671028B2 (en) 1988-07-19 1988-07-19 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JPH0671028B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2806348B2 (en) * 1996-03-08 1998-09-30 日本電気株式会社 Semiconductor device mounting structure and method of manufacturing the same
JP2002151551A (en) 2000-11-10 2002-05-24 Hitachi Ltd Flip chip mounting structure, semiconductor device having the mounting structure, and mounting method

Also Published As

Publication number Publication date
JPH0228946A (en) 1990-01-31

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