JPH0671201B2 - Level converter - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention is for a logic circuit using a MIS type transistor,
A logic signal having a high potential level and a low potential level and an amplitude, for a logic circuit using a bipolar transistor,
The present invention relates to a level conversion device for converting a level into a logic signal having a high level and a low level and an amplitude.

[Prior art]

Conventionally, the level conversion device described below with reference to FIG. 2 has been proposed. That is, for the logic circuit using the MIS type transistor,
High potential level V _1H and low potential level V _1L and amplitude | V _1H −V _1L |
Of the first logic signal S1 having a high potential level _V2H and a low potential level on the high potential level _V1H side and being narrower than the amplitude | _V1H - _V1L | of the first logic signal S1. Second to take the amplitude
First level conversion circuit M1 for level conversion to the logic signal S2 of
Have. In this case, the first level conversion circuit M1 has a p-channel first MI whose source is connected to the high-potential power supply terminal E1 '.
The S-type transistor T1 and the drain of the first MIS-type transistor T1 are connected to the drains of a plurality of N diodes d ₁ , d _2.
and a n-channel second MIS-type transistor in which a diode circuit D in which d _N is connected in series is connected in reverse polarity and a source is connected to a low potential power supply terminal E2. An input terminal 1 for inputting the above-mentioned first logic signal S1 as an input signal from the gates of the transistors T1 and T2.
And the output line 2 for outputting the above-mentioned second logic signal S2 from the midpoint of connection between the drain of the transistor T1 and the diode circuit D. Further, the second logic signal S2 from the first Reberu conversion circuit M1, a logic circuit using a bipolar transistor, the high potential level V _3H and the high potential level V _IH side of the first logic signal S1 A first logic signal S1 for a logic circuit using a low potential level _V3L and using a bipolar transistor
Third logic signal with a narrower amplitude than the amplitude | V _1H −V _1L |
It has a second level conversion circuit M2 for converting the level to S3. In this case, the second level conversion circuit M2 connects the base to the output line 2 derived from the first level conversion circuit M1,
The collector is connected to the high-potential power supply terminal E4, and the npn-type transistor Q2 is connected from the emitter to the output terminal 3 that outputs the above-mentioned third logic signal S3 as an output signal. And a diode circuit D ′ in which a plurality of, for example, two diodes d ′ ₁ and d ′ ₂ are connected in series, and the other end is connected to the output terminal 3. In the figure, a resistor RL and a capacitor CL are connected to the output terminal 3 between the output terminal 3 and the low-potential power supply terminal E5 and between the output terminal 3 and the high-potential power supply terminal E6, respectively. Connected as a load. The above is the configuration of the conventionally proposed level conversion apparatus. According to the level conversion device having such a configuration, the logic signal S1 which is input to the input terminal 1 as an input signal now
, High potential level V _1H and low potential level V _1L respectively −
2.2V and -5.2V, the amplitude is | -2.2-(-5.2) | = 3.
And a logic signal that is to 0V, The logic signal S3 is output as an output signal from the output terminal 3, the high potential level V _3H and the low potential level V _3L, respectively -0.8V and -1.
When it is assumed that the logic signal is 6 V and the amplitude is | −0.8 − (− 1.6) | = 0.8 V, the high potential power supply terminal
O1 potential is applied to E1 ′, and low potential power supply terminal E2 is
A potential of −5.2 V corresponding to the low potential level V _1L of the logic signal S1 is applied, and the logic signal S3 is applied to the high potential power supply terminals E4 and E6.
The OV potential corresponding to the high potential level V _3H of
If a potential of −2.0 V corresponding to the low potential level V _3L of the logic signal S3 is applied to the low potential power supply terminal E5, when the logic signal S1 takes the high potential level V _1H (−2.2 V), the MIS type transistor
T1 and T2 turn off and on, respectively. Therefore, the potential of the output line 2 is higher than the potential (−5.2 V) of the low potential power supply terminal E2, and the sum of the voltage drops when the diodes d _{1 to} d _N in the diode circuit D are on (this is referred to as V _D ). ), The potential becomes higher (-5.2 + V _D ) V. When the logic signal S1 has a low potential level V (-5.2V), the MIS transistors T1 and T2 are turned on and off, respectively. Therefore, the potential of the output line 2 is high potential power supply terminal E
It becomes 1'potential (OV). Therefore, the high potential level is applied to the output line 2 of the level conversion circuit M1.
_2H and low potential level V _2L are OV and − (5.2−V _D ), respectively
A second logic signal S2 of V is obtained. Further, since the second logic signal S2 is obtained on the output line 2 by taking the above-described high potential level V _2H and low potential level V _2L , when the logic signal S2 takes the high potential level V _2H (OV). ,
The transistor Q2 is turned on, so that the potential of the output terminal 3 is higher than that of the high potential level V _2H.
Emitter voltage V _BE (usually about 0.8 V) content lower potential (V _2H -
V _BE ) (= 0-0.8 = 0.8V). Further, the logic signal S2 is at the low potential level V _2L (− (5.2−V _D ).
V), the output terminal 3 is turned off, so that the potential of the output terminal 3 is higher than that of the low potential level V _2L (OV) of each of the diodes d ′ ₁ and d ′ _{2 in} the diode circuit D ′. Sum of voltage drop (usually about 0.8V) (0.8
+ 0.8 = 1.6V) lower potential (0-1.6V = -1.6V). Therefore, the high potential level is applied to the output line 3 of the level conversion circuit M2.
The V _3H and the low potential level V _3L respectively and -0.8V and -1.6 V, an amplitude | -0.8-1.6 | = a 0.8 V, the third logic signal S3 is obtained. From the above, according to the level conversion device shown in FIG. 2, the logic signal S1 having the high potential level _V1H and the low potential level _V1L and the amplitude for the logic circuit using the MIS type transistor is obtained.
For a logic circuit using a bipolar transistor,
High potential level V _1H of logic signal S1 High potential level V _3H and
The level can be converted into a logic signal S3 having V _3L and an amplitude.

[Problems to be Solved by the Invention]

In the case of the conventional level conversion device described above with reference to FIG. 2, the input terminal T1 derived from the gates of the MIS type transistors T1 and T2 of the first level conversion circuit M1 is used for a logic circuit using the MIS type transistor. , The first logic signal S1 having the high potential level V _1H and the low potential level V _1L is input, the high potential power supply terminal E1 ′ on the MIS type transistor T1 side of the first level conversion circuit M1 and the MIS type A potential corresponding to the high potential level V _1H (−2.2V) and the low potential level V _1L (−5.2V) of the first logic signal S1 is applied to the low potential power supply terminal E2 on the transistor T2 side, and It is desirable to operate the level conversion circuit M1. In this sense, in the case of the conventional level conversion device described above with reference to FIG. 2, a potential corresponding to the low potential level V _1L (−5.2V) of the first logic signal S1 is applied to the low potential power supply terminal E2. Accordingly, even if no problem since the first level converting circuit M1 operates, the high-potential power supply terminal E1 ', corresponds to the high potential level V _IH of the first logic signal S1 (-2.2 V) - When applying a potential such as 2.2V, apply a potential such as OV to the high potential power supply terminals E4 and E6, and also apply a low potential power supply terminal E5.
As long as the potential of −2.0 V is applied to the low potential level V _3L of the third logic signal S3, the first logic signal S1 takes the high potential level V _1H (0-1.6). even obtained at a potential of V = -1.6 V, since the bipolar transistor Q2 is not turned on, the high potential level V _3H is not obtained in the third logic signal S3. Further, if −2.2V lower than OV is applied to the high potential power supply terminals E4 and E6, and if a potential lower than −2.2V is applied to the low potential power supply terminal E5, the low potential level V3 of the third logic signal S3 is given. _3L
When the first logic signal S1 takes the high potential level V _1H ,
(−2.2−1.6) = − 3.8V, and when the high potential level V _3H of the third logic signal S3 is the low potential level V _1L of the third logic signal S3, -2.2-0.8) = -3.0
V, and thus the high potential level V of the third logic signal S3
_3H and low potential level V _3L cannot be obtained at −0.8V and −1.6V for logic circuits using bipolar type transistors,
Had the inconvenience. The present invention therefore proposes a new level conversion device without the above-mentioned drawbacks.

[Means for Solving the Problems]

The level conversion device according to the present invention is similar to the case of the conventional level conversion device described above with reference to FIG. 2, and is the first for taking the high potential level, the low potential level and the amplitude for the logic circuit using the MIS type transistor. A first level conversion circuit for level-converting the logic signal of (1) into a second logic signal having a high potential level and a low potential level on the high potential level side and a narrower amplitude than the first logic signal, The second logic signal is supplied to a logic circuit including a bipolar transistor,
And a second level conversion circuit for converting the level of the first logic signal into a third logic signal having the high potential level and the low potential level on the high potential level side and the amplitude. However, in the case of the level conversion device according to the present invention, the first level conversion circuit has the p-channel first MIS transistor having the source connected to the first high-potential power supply terminal and the drain having the first Second MIS transistor connected to the drain of the MIS transistor and the source connected to the low potential power supply terminal through the constant current circuit, and the base connected to the first high potential power supply terminal. , An npn type first bipolar type transistor having an emitter connected to the drains of the first and second MIS type transistors and a collector connected to a second high potential power supply terminal through a resistor, and 1st and 2nd MIS
An input terminal for inputting the first logic signal as an input signal from the gate of the first transistor, and the second logic from the midpoint between the collector of the first bipolar transistor and the resistor. It has a configuration in which an output line for outputting a signal is derived. The second level conversion circuit connects the base to the output line, connects the collector to the third low-potential power supply terminal, and derives the output terminal for outputting the third logic signal as an output signal from the emitter. The second bipolar transistor of the npn type is provided.

[Action / effect]

According to the level conversion device of the present invention, the first high-potential power supply terminal on the side of the first MIS type transistor and the low-potential power supply terminal on the side of the second MIS type transistor of the first level conversion circuit are respectively Since the potentials corresponding to the high potential level and the low potential level of the logic signal 1 can be given to operate the first level conversion circuit,

The high potential level and the high potential level for the logic circuit using the MIS type transistor can be obtained without the drawbacks or inconveniences of the conventional level conversion device described above with reference to FIG. The first logic signal having a low potential level can be easily level-converted into a third logic signal having a high potential level and a low potential level for a logic circuit using a bipolar transistor. Further, according to the level conversion device of the present invention, in the first level conversion circuit, when the second logic signal is obtained at the high potential level by the low potential level of the first logic signal, Since the MIS type transistor is turned off, the current does not flow from the second high potential power supply terminal to the low potential power supply terminal through the first bipolar type transistor and the resistor. The level conversion of the first logic signal to the third logic signal is performed, and the conversion can be effectively performed with low power consumption.

【Example】

Next, an embodiment of the level conversion device according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals. The level converter according to the present invention shown in FIG. 1 has a high potential level V _1H for a logic circuit using MIS type transistors, as in the case of the conventional level converter shown in FIG.
And the first logic signal S1 having the low potential level V _1L and the amplitude | V _1H −V _1L |, the high potential level V _1H on the high potential level V _1H side.
_2H and low potential level and the amplitude of the first logic signal S1
It has a first level conversion circuit M1 for converting the level into a second logic signal S2 having a narrower amplitude than that of | V _1H −V _1L |. In addition, the second logic signal S2 from the first level conversion circuit M1
For a logic circuit using a bipolar transistor,
High potential level V of first logic signal S1 High potential level V of _1H side
Take _3H and the low potential level V _3L, and the logic circuit using a bipolar transistor, the amplitude of the first logic signal S1 | third logic signal S3 takes a narrow amplitude compared to | V _IH -V _1L It has a second level conversion circuit M2 for level conversion. However, in the level conversion device according to the present invention shown in FIG. 1, the first level conversion circuit M1 has a p-channel first MI whose source is connected to the first high-potential power supply terminal E1.
An S-type transistor T1 and an n-channel type second MIS-type transistor T2 whose drain is connected to the drain of the first MIS-type transistor T1 and whose source is connected to the low-potential power supply terminal E2 through the constant current circuit 4. , The base is connected to the first high-potential power supply terminal E1, the emitter is connected to the drains of the first and second MIS type transistors T1 and T2, and the collector is connected to the second high-potential power supply terminal E3 through the resistor R. is doing
and an npn-type first bipolar transistor Q1,
Then, the input terminal 1 for inputting the above-mentioned first logic signal S1 as an input signal is derived from the gates of the first and second MIS type transistors T1 and T2, and the collector of the first bipolar type transistor Q1. The output line 2 for outputting the above-mentioned second logic signal S2 is derived from the connection midpoint between the resistor R and the resistor R. In this case, the constant current circuit 4 connects the drain to the source of the second MIS transistor T2 and the n-channel MIS transistor T3 whose source is connected to the low potential power supply terminal E2, and the gate and drain. Both are connected to the gate of the MIS transistor T3 and also connected to the high potential power supply terminal E7 through the constant current source 5, and the source is a low potential power supply terminal.
N-channel MIS transistor T connected to E2
4 has a configuration of a current mirror type constant current circuit having. Further, the second level conversion circuit M2 connects the base to the output line 2 of the first level conversion circuit M1, connects the collector to the third high-potential power supply terminal E4, and connects the emitter to the above-mentioned third logic. The configuration is such that it has an npn-type second bipolar transistor Q2 leading out the output terminal 3 for outputting the signal S3 as an output signal. In the figure, the output terminal 3 and the low-potential power supply terminal E5 are used as in the case of the conventional level converter described in FIG.
A resistor RL and a capacitor CL are connected as a load connected to the output terminal 3, respectively, and between the output terminal 3 and the other high-potential power supply terminal E6. The above is the configuration of the embodiment of the level converting apparatus according to the present invention. According to the level conversion device of the present invention having such a configuration, the logic signal S1 input to the input terminal 1 as an input signal is as in the case of the conventional level conversion device described above with reference to FIG. High potential level V _1H and low potential level V _1L
Are −2.2V and −5.2V respectively, and the amplitude is −−2.2−
(−5.2) | = 3.0V, and a logical signal output from the output terminal 3 as an output signal.
As in the case of the conventional level converter described above with reference to FIG. 2, S3 has the high potential level V _3H and the low potential level V _3L of −0.8 V and −1.6 V, respectively, and the amplitude | −0.8 − (− 1.6) ｜
= 0.8V. If it is required that the logic signal is high, the high potential power supply terminal E1 is connected to the high potential level V of the logic signal S1.
It gives potential of -2.2V corresponding to _1H, also to the low-potential power supply terminal E2, corresponding to the low potential level V _1L logic signal S1 -5.2
Given potential and V, further to the high-potential power supply terminal E3, E4, E6 and E7, given the potential of OV corresponding to the high potential level V _3H logic signal S3, also the low-potential power supply terminal E5, the logic signal If a potential of −2.0 V corresponding to the low potential level V _3L of S3 is given, when the logic signal S1 takes the high potential level V _1H (−2.2 V), the MIS type transistors T1 and T2 are turned off and on, respectively. To do. Therefore, the emitter of the bipolar transistor Q1
Through the constant current circuit 4 and the MIS type transistor T2, a potential substantially equal to the potential (−5.2V) of the low potential power supply terminal E2 is applied, while the base of the bipolar transistor Q1 has the potential of the high potential power supply terminal E1 ( -2.2V), bipolar transistor Q1 turns on. Therefore, if the value of the resistor R is properly selected, the output line 2
Then, through the resistor R, the potential (OV) of the high potential power supply terminal E3
A potential (0-0.8) V = -0.8V lower by -0.8V is obtained. When the logic signal S1 has a low potential level _V1L (-5.2V), the MIS type transistors T1 and T2 are turned on and off, respectively. Therefore, the bipolar transistor Q1 has an MI
Through the S-type transistor T1, a potential almost equal to the potential (−2.2V) of the high potential power supply terminal E1 is applied, while the base of the bipolar transistor Q1 has a high potential power supply terminal E1.
Since the potential (-2.2V) is applied, the bipolar transistor Q1 is turned off. Therefore, the high potential power supply terminal is connected to the output line 2 through the resistor R.
The potential (OV) of E3 is obtained. Therefore, the second logic signal S2 is applied to the output terminal 2 through the input terminal 1
When it takes a high potential level V _1H (-2.2V) according to the first logic signal S1 input to the circuit, it is more bipolar type than the low potential level V _3L (-1.6V) of the third logic signal S3. Higher than the base-emitter voltage V _BE (0.8 V) of transistor Q2 −
When the low potential level V _2L of 0.8V is taken and the logic signal S1 takes the low potential level V _1L (−5.2V), the bipolar type is higher than the high potential level V _3H (−0.8V) of the third logic signal S3. OV higher than the base-emitter voltage V _BE (0.8 V) of transistor Q2
It is obtained by taking the high potential level V _2H of. Further, the output line 2, the second logic signal S2, in response to the first logic signal S1, it takes a high potential level V _IH (-2.2 V) and the low potential level V _1L (-5.2V) At this time, since the low potential level V _2L (−0.8 V) and the high potential level V ^2H (OV) described above are obtained, the second logic signal S2 is changed to the low potential level V 2
_{When 2L} (-0.8V) is taken, the output terminal 3 has a base-emitter voltage V _BE (0.8V) of the bipolar transistor Q2 which is lower than the low potential level V _2L (-0.8V) of the second logic signal S2.
Low potential ((V _2L −V _BE ) V = (− 0.8−0.8) V = −
1.6V) can be obtained. Further, when the second logic signal S2 has a high potential level (OV), the high potential level V _2H of the second logic signal S2 is output to the output terminal 3.
A potential ((V _2H −V _BE ) V− (0 that is lower than (OV) by the base-emitter voltage V _{BE of the} bipolar transistor Q2.
-0.8) V = -0.8V) is obtained. Therefore, when the third logic signal S3 at the output terminal 3 takes the high potential level V _1H (−2.2V) in response to the first logic signal S1 input to the input terminal 1, −1.6V Of the low potential level V _3L of the first logic signal S1 (-5.2
V) is obtained by taking a high potential level V _3H of −0.8V. As apparent from the above, according to the level converting apparatus according to the present invention shown in FIG. 1, and corresponds to the high potential level V _IH logic signal S1 to the high-potential power supply terminal E1 (-2.2 V) potential (-2.2V) is applied and the potential (-5.2V) corresponding to the low potential level (-5.2V) of the logic signal S1 is applied to the low-potential power supply terminal E2. The logic signal S1 having a high potential level V _1H (−2.2V) and a low potential level V _1L (−5.2V) for the circuit is supplied to the low potential level V _3L (−) for the logic circuit using the bipolar transistor. 1.6V) and a high potential level _V3H (-0.8V) can be converted into a logic signal S3. Further, according to the level conversion device of the present invention shown in FIG. 1, in the first level conversion circuit M1, the first logic signal
When the second logic signal S2 is obtained at the high potential level _V2H by the S1 taking the low potential level _V1L , the second MIS type transistor T2 is turned off. From E3, the current is the first bipolar transistor
It does not flow to the low-potential power supply terminal E2 through Q1 and the resistor R. Therefore, the level conversion of the first logic signal S1 described above to the third logic signal S3 is performed, and the conversion is performed with low power consumption. It can be done effectively without being accompanied. In the above description, the potential corresponding to the high potential level V _1H (−2.2V) of the logic signal S1 given to the high potential power supply terminal E1 is equal to the high potential level V _1H (−2.2V), The case has been described where the potential corresponding to the low potential level V _1L (−5.2V) of the logic signal S1 given to the low potential power supply terminal E2 is equal to the low potential level V _1L (−5.2V). , High potential level V of logic signal S1 applied to high potential power supply terminal E1
_The potential corresponding to _1H (−2.2V) is higher than the high potential level V _1H (−2.2V) (sufficiently higher than −5.2V) within the range where the bipolar transistor Q1 does not enter the saturation operation region. , −0.4 V or less), the low potential level V _{1L of the} logic signal S1 supplied to the low potential power supply terminal E2
The potential corresponding to (-5.2V) is the MIS transistor T
It will be apparent that the above-described effects can be obtained even when the potential is higher than the low potential level V _1L (−5.2 V) within the operable range of ₁ to T4.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a level conversion device according to the present invention. FIG. 2 is a connection diagram showing a conventional level conversion device. M1, M2 ...... Level conversion circuit T1 to T4 ...... MIS type transistor Q1, Q2 ...... Bipolar type transistor 1 ...... Input terminal 2 ...... Output line 3 ...... Output terminal 4 ...... Constant current circuit R, RL ...... Resistance CL …… Capacity E1, E3, E4, E6, E7 …… High potential power supply terminal E2, E5 …… Low potential power supply terminal

Claims (1)

[Claims] 1. A first for taking a high potential level, a low potential level and an amplitude for a logic circuit using a MIS type transistor.
A first level conversion circuit for level-converting the logic signal of (1) into a second logic signal having a high potential level and a low potential level on the high potential level side and a narrower amplitude than the first logic signal, A third potential signal for the second logic signal, which has a high potential level and a low potential level on the high potential level side of the first logic signal, and an amplitude for a logic circuit using a bipolar transistor.
And a second level conversion circuit for converting the level of the signal into a logic signal of the first level conversion circuit, wherein the first level conversion circuit has a source connected to a first high-potential power supply terminal. N-channel second MI having a MIS transistor and a drain connected to the drain of the first MIS transistor and a source connected to a low potential power supply terminal through a constant current circuit.
The S-type transistor and the base are connected to the first high-potential power supply terminal, the emitters are connected to the drains of the first and second MIS type transistors, and the collector is connected to the second via a resistor.
And a first npn-type bipolar transistor connected to the high-potential power supply terminal of
An input terminal for inputting the first logic signal as an input signal from the gate of the type transistor, and the second logic signal from the midpoint between the collector of the first bipolar type transistor and the resistor. The second level conversion circuit has a configuration in which an output line for output is derived, the base is connected to the output line, the collector is connected to a third high-potential power supply terminal, and the emitter is connected to the above-mentioned A level conversion device having a configuration including an npn-type second bipolar transistor which derives an output terminal for outputting a third logic signal as an output signal.