JPH0671202B2 - Liquid crystal drive - Google Patents

Abstract

PURPOSE:To attain high speed processing and low power consumption with a simple process by using a complementary signal so as to operate a totempole type MOS transistor(TR) thereby preventing a steady-state DC current from being caused between power terminals. CONSTITUTION:The circuit is so configurated that a couple of noninverting input signal Vin and inverting input signal, the inverse of Vin are converted into a couple of noninverting and inverting output signals Vout, the inverse of Vout with a large current drive capability. Since the noninverting/inverting input signals Vin, the inverse of Vin are fed to a gate of driver MOSQ1, MOSQ3 for an inverter and load MOSQ2, MOSQ4, any of the MOS TR is turned off without fail, resulting that no DC current flows substantially between a power potential terminal VDD and ground. Thus, high speed and low power consumption is attained with a simple process.

Description

The present invention relates to a MOS transistor circuit, and more particularly to a liquid crystal driving device suitable for high speed driving with low power consumption, and particularly suitable for high speed driving with low power consumption. The present invention relates to a liquid crystal drive device using a MOS transistor.

[Conventional technology]

The most commonly used single crystal silicon MOS transistor inverter circuit is the E / E inverter circuit shown in FIG. This circuit is often used because of its simple manufacturing process, but the disadvantages are: 1) Current driving capability is small.

2) High power consumption.

3) The area of the circuit becomes large.

Etc.

In particular, the problem of 1) becomes an obstacle when using an inverter of E / E configuration. In order to solve this problem, the buffer circuits shown in FIGS. 3, 4, and 5 have conventionally been connected to an inverter having an E / E configuration. Incidentally, as a circuit related to this type of circuit, there is JP-A-55-8197.

[Problems to be solved by the invention]

The purpose of the circuit configurations shown in FIGS. 3, 4, and 5 is to transform one input signal into one output signal having a large current driving capability.

The buffer circuit shown in FIGS. 3, 4, and 5 has one input and one input.
Although it is suitable as an output buffer circuit, it is not suitable as a 2-input 2-output buffer circuit.

An object of the present invention is to provide a liquid crystal driving device using a MOS transistor circuit that can achieve high speed and low power consumption by a simple process.

[Means for solving problems]

The object of the present invention can be achieved by using a circuit configuration capable of converting a pair of input signals composed of a positive phase and a negative phase into a pair of output signals composed of a positive phase and a negative phase having a large current driving capability. it can.

[Action]

By operating a totem-ball type MOS transistor with complementary signals, a steady DC current does not flow between the power supply terminals, so high speed and low power consumption can be achieved.

〔Example〕

 A first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, IN1 is a first input terminal to which a positive-phase first input signal Vin having a first or second potential level is applied, and IN2 is a first input signal Vin. Is a complementary second
Alternatively, the second input signal Vi of the opposite phase having the first potential level
The second input terminal to which n is applied, GND, and V _DD are the first
And the second power supply potential terminal, OUT1 and OUT2 are the first and second
Output terminal. In Fig. 1, Q ₁ is the source
The drain path is the first node N ₁ of the first power supply potential terminal GND
And at least one first enhancement type NMOS transistor having a gate connected to IN1 at a first input terminal connected to a second output terminal OUT2
Reference numeral ₂ denotes at least one second enhancement type NMOS whose source / drain path is connected between the second output terminal and the second power supply potential terminal V _DD and whose gate is connected to the second input terminal IN2. The transistor Q ₃ has a source / drain path connected between the first power supply potential dead ground GND and the first output terminal QUT 2 serving as the second node N _2, and has a gate connected to the second output terminal OUT 2 Q ₄ is at least one third enhancement type NMOS transistor, the source / drain path of which is connected between the first output terminal OUT 1 and the second power supply potential terminal V _DD, and the gate of which is Q _4. First input terminal I
At least one fourth enhancement mode NMOS transistor connected to N2.

In Fig. 1, two enhancement-type NMOS transistors with source and drain paths connected in series between the power supply potential terminal V _DD and the ground GND are connected in parallel, and the drain of the driver MOSQ ₁ at the first stage and the drain of the next stage are connected. The gate of the driver MOSQ ₃ is connected, the input signal Vin of the positive phase is input to the gate of the driver MOSQ ₁ of the first stage and the gate of the load MOSQ ₄ of the next stage, and the input signal Vin of the opposite phase is the load MOSQ ₂ of the first stage. And output the positive-phase output signal Vout from the drain of the next-stage driver MOSQ ₃ ,
The reverse phase output signal Vout is taken out from the gate of the driver MOSQ _{3 in} the next stage.

The MOSQ ₁ , Q ₂ , Q ₃ and Q ₄ are preferably polycrystalline silicon thin film transistors formed on a single insulating substrate.

In the circuit shown in Fig. 1, the positive and negative phase input signals Vin and in are applied to the gates of the driver MOSQ ₁ and Q ₃ and the load MOSQ ₂ and Q ₄ of the inverter. As a result, in the steady state, substantially no DC current flows between V _DD and ground.

The fact that no DC current flows through the inverter in a steady state means that the on / off level of the inverter is not determined by the resistance division ratio of the two MOS transistors (driver MOS, load MOS). That is, each MOS transistor Q ₁ ,
When designing Q ₂ , Q ₃ , and Q ₄ , since there is no restriction on the resistance division ratio, all of Q ₁ , Q ₂ , Q ₃ , and Q ₄ can be designed to have a large current driving capability.

As described above, the circuit configuration of FIG. 1 is a circuit configuration capable of converting a pair of input signals composed of a positive phase and a negative phase into a pair of output signals composed of a positive phase and a negative phase having a sufficiently large current driving capability.

A second embodiment of the present invention will be described with reference to FIG.

In FIG. 6 (a), IN1 is a first input terminal to which a positive-phase first input signal Vin having a first or second potential level is applied, and IN2 is a first input terminal. The signal is the second input terminal to which the second input signal of the opposite phase having the complementary second or first potential level is applied, and GND and V
_DD is the first and second power supply potential terminals, OUT1 and OU
T2 is the first and second output terminals, φ ₁ is the first clock terminal to which the first clock signal is applied, and φ ₂ is the second clock signal to which the second clock signal is applied. This is the clock terminal. Furthermore, in FIG. 6 (a), Q ₁
The source and drain paths are the first power supply potential terminal GND and the first
Node is at least one first enhancement type NMOS transistor connected between the N _1, Q _2, the source-drain path the first node N ₁ and the second power supply potential terminal V _DD Q ₃ is at least one second enhancement type NMOS transistor having a source / drain path connected to the first power supply potential terminal GND and the second node N.
Is connected between the _2, Gade is at least one of the third enhancement type NMOS transistor that is connected to the first node N _1, Q _4, the source-drain path and a second node N _2, and at least one of the fourth enhancement type NMOS transistor connected between a second power supply potential terminal V _DD, Q _5, the source-drain path between the first input terminal IN1 the first NMOS transistor Q ₁ gate and 4th N
At least one fifth enhancement type NMOS transistor connected to the gate of the MOS transistor Q _{4 and having} its gate connected to the first clock terminal φ ₁ .
Q ₆ has the source / drain path connected to the second input terminal IN 2 and the second
Of at least one sixth enhancement-type NMOS transistor, the gate of which is connected to the gate of the NMOS transistor Q _{2 and} whose gate is connected to the first clock terminal φ ₁ .
Q ₇ is at least one seventh enhancement type in which the source / drain path is connected between the second node N ₂ and the first output terminal QUT 1, and the gate is connected to the second clock terminal φ _2. An NMOS transistor, Q ₈ has at least one source / drain path connected between the first node N ₁ and the second output terminal OUT 2 and a gate connected to the second clock terminal φ ₂ . It is an eighth enhancement type NMOS transistor.

The NMOS transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q ₈ are preferably polycrystalline silicon thin film transistors formed on a single insulating substrate.

FIG. 6 (a) shows transfer gate MOS transistors (TGT: Transfer Gate Transistor) Q ₅ , Q ₆ , Q ₇ , at both ends (4 terminals) of the circuit of the first embodiment of the present invention shown in FIG. Q ₈
Is connected to the source or drain, and the MOS transistors of Q ₅ , Q ₆ , Q ₇ , and Q ₈ are controlled by clock pulses φ ₁ and φ ₂ .

The operation of the circuit shown in FIG. 6 (a) will be described below with reference to the timing chart shown in FIG. 6 (b).

TGT at the timing when the clock pulse φ ₁ is at “high” level
(Transfer Gate Transistor) is turned on,
The input signal Vin, in is applied to the buffer circuits Q _{1 to} Q ₄ only when φ ₁ is at the “high” level.

As buffer circuit Q ₁ to Q ₄ in FIG. 6 (a) is mentioned above, on, off level switch MOS, since no One Kima in resistance division ratio of the load MOS, the current driving capability of the individual transistors Can be designed to be large. That is, the input signal Vin, in is the output signal Vout, which has a sufficiently large current drive capability.
converted to out. Next, the clock pulse φ ₂ is “high”
Vout and out are output through TGTQ ₇ and Q ₈ at the level timing.

FIG. 7 shows a third embodiment of the present invention, which is a shift register circuit constructed by connecting a plurality of stages of the circuit of FIG. 6 (a), and FIG. 8 shows φ ₁ and φ in FIG. ₂ , Vin, in, Vout,
It shows the timing chart of out. The circuit operation is similar to that of the circuit shown in FIG. The shift register circuit of FIG. 7 is a 2-input 2-output shift register circuit. The shift register circuit shown in FIG. 7 has effects such as high-speed operation and low power consumption because of the large current driving capability and the absence of direct current.

Such a shift register circuit is most effective especially when used in an active matrix crystal display with a built-in peripheral circuit as shown in FIG.

In FIG. 9, 1 is a glass substrate serving as an insulating substrate, 2 is a display unit, 3 is a scanning circuit, 4 is a signal circuit, and 5 is an external control circuit. Here, the display unit 2, the scanning circuit 3, and the signal circuit 4 are made of polycrystalline silicon thin film MOS transistors, and the external control circuit 5 is made of monocrystalline silicon, that is, IC (Integrated Circr).
its).

FIG. 10 shows a circuit configuration of the scanning circuit 3 configured by using the shift register circuit according to the third embodiment of the present invention. 10th
The circuit configuration in the figure is the output of the shift register shown in FIG.
Vout and 2 for each TFT (Thin Film Transista
This is a structure connected to the gates of the MOS transistors Q ₁₀₀ and Q ₂₀₀ of the r) structure. Here, phi _1, the timing of phi ₂ is the same as φ _1, φ ₂ of the timing indicated by FIG. 6 (b).
In addition, C _G is the capacity of one scanning line seen from the scanning side, V ₀₁ , V ₀₂
Is the voltage applied to C _G.

The circuit operation of FIG. 10 will be described below. Input signal Vin, in
The clock pulse φ ₁ is input to the buffer circuit at the timing of “high” level, and the clock pulse φ ₂ becomes “hig”.
Vout, out is output at the timing of h "level. At this time, since each Vout, out is applied to the gate of two TFTs, either V ₀₁ or V ₀₂ is always applied to C _G .

FIG. 11 is a structural example of the scanning circuit 3 using the buffer circuit of FIG. 1 and the shift register of FIG. The timing of the clock pulses φ ₁ and φ ₂ is φ shown in FIG. 6 (b).
It is the same as the timing of ₁ and φ ₂ . The circuit operation of FIG. 11 will be described below. Input signal Vin, in is clock pulse φ
₁ is input to the buffer circuit at the timing of "high" level, and Vout, out is output at the timing of the clock pulse φ ₂ being at "high" level. At this time, each of Vout and out is transmitted to the input section of the 2-input 2-output buffer circuit shown in FIG. Each of the output signals Vout and out passing through the buffer circuit is applied to the gates of the two TFTs. As a result, either V ₀₁ or V ₀₂ is applied to C _G.

FIG. 12 shows an example of the signal circuit 3 constructed by using the shift register shown in FIG. The circuit operation of FIG. 12 will be described below with reference to the timing chart shown in FIG. The input signal Vin, in is loaded into the buffer circuit at the timing when the clock pulse φ ₁ is at the “high” level, and the input signal Vout, at the timing when the clock pulse φ ₂ is at the “high” level. Is output. At this time, Vout is the signal voltage V _D at the drain.
Applied to the gate of TFTQ ₉ to which a is connected. Here, if Vout is “hig
At the h "level, transistor Q ₉ is turned on and V _D
ata is transmitted to the gates of Q ₁₀ and Q ₁₂ , and if Vout is at the “Low” level, V _D ata is not transmitted to the transistors Q ₁₀ and Q ₁₁ . To the gate of the source signal transistor Q ₁₀ of the transistor Q _9, inverts the source of the signal of the transistor Q ₉ in inverter formed by transistors Q _12, Q _13, in order to apply the signal to the gate of the transistor Q ₁₁ , V ₀₁ or V ₀₂ is always applied to the liquid crystal capacitance C _1C for one pixel viewed from the signal side.

FIG. 14 shows a modification of the signal circuit 3 shown in FIG. Vi
n, in, φ _1, the timing of phi _2, and V _D ata is identical to that of the circuit operation of Figure 12.

The circuit operation of FIG. 14 will be described below. Clock pulse φ
_The input signal Vin, in is taken into the buffer circuit at the timing of ₁ being the "high" level, and the output signal Vout, out is outputted at the timing of the clock pulse φ ₂ being the "high" level. At this time, Vout is applied to the gate of the transistor Q ₁₅ , and out is applied to the gate of the transistor Q ₁₄ . Therefore, the gate of transistor Q ₉ has V _D3 and V _D4
Either must be applied. Here, if "high" level to the gate of Q ₉ is only to be applied transistor Q ₉ is turned on, V _D ata is transmitted to the gate of Q _10, Q _12.
Further, if the transistor Q ₉ if "Low" level is applied to the gate of Q ₉ is turned off, V _D ata is not transmitted to the transistors Q _10, Q _11. The source signal of the transistor Q ₉ is applied to the gate of the transistor Q _{10 and} the source signal of the transistor Q ₉ is inverted by the inverter composed of the transistors Q ₁₂ and Q ₁₃ and applied to the gate of the inverted signal transistor Q _11. Liquid crystal capacity Cle for one pixel viewed from the side
Either V ₀₁ or V ₀₂ is always applied to.

By using such a shift register circuit, the configuration of the active matrix liquid crystal display with built-in peripheral circuits is as shown in FIG.

In FIG. 21, 1 is a glass substrate, 2 is a display unit, 5 is an external control circuit, 8 is the shift register described above, 6 is a multiplexer, and 10 is a line memory.

16 is an embodiment of the structure of the active matrix liquid crystal display with built-in peripheral circuits shown in FIG.

A pair of input signals consisting of a positive phase and a negative phase, which are applied to the signal circuit, the scanning circuit, and both shift register circuits, are formed by the external control circuit 5, and are input to both shift registers. This enables high speed operation of the shift register.

FIG. 17 shows an embodiment of a 2-input 2-output shift register formed by using CMOS transistors on a glass substrate.
Incidentally, FIG. 18 shows a sectional view of the CMOS circuit formed on the glass substrate, and FIG. 19 shows a pattern view of the CMOS circuit of FIG. 18 seen from directly above. In FIG. 18, 1 is a glass substrate, 12 is an intrinsic polycrystalline silicon film, 13 is P (phosphorus) -doped polycrystalline silicon film, 14 is B (boron) -doped polycrystalline silicon film, and 15 is Al. (Grounded to ground), 16 is Al (power supply voltage
Connected to V _DD ), 17 is Al (output section), 18 is silicon oxide film, 19
Is a polycrystalline silicon film (gate of transistor) doped with P (phosphorus) or B (boron), and 20 is a silicon nitride film. Further, in FIG. 19, 21 is an input portion (Al) of the CMOS circuit, 22 is an output portion (Al) of the CMOS circuit, and 23 is a polycrystalline silicon film.

High speed driving becomes possible by using the shift register circuit of FIG.

〔The invention's effect〕

According to the present invention, there is an effect that the liquid crystal driving device, particularly the liquid crystal driving device including a shift register can be reduced in power consumption and speed.

[Brief description of drawings]

FIG. 1 is a buffer circuit diagram of the first embodiment of the present invention, and FIG.
FIGS. 5 to 5 are conventional transistor circuit diagrams, FIG. 6 is a buffer circuit diagram which is a second embodiment of the present invention, and FIGS. 7 and 8 are shift registers which are a third embodiment of the present invention. FIG. 9 is a diagram showing a circuit, FIG. 9 is a configuration diagram of an active matrix liquid crystal display with a built-in peripheral circuit, FIG. 10 is a diagram showing a scanning circuit configured by using a shift register circuit according to an embodiment of the present invention, and FIG. The figure which shows the scanning circuit comprised using the shift register circuit and buffer circuit which become the Example of this invention,
12 and 13 are diagrams showing a signal circuit configured by using the shift register circuit according to the embodiment of the present invention, and FIG.
FIG. 15 is a diagram showing a modified example of the circuit in the figure, FIG. 15 is a configuration diagram of an active matrix liquid crystal display with a built-in peripheral circuit when a shift register circuit according to an embodiment of the present invention is used, and FIG. 16 is a modified example of FIG. FIG. 17, FIG. 17 is a shift register circuit diagram of 2-input 2-output when CMOS is used, FIG. 18 is a sectional view of a CMOS circuit formed on a glass substrate, and FIG. 19 is formed on a glass substrate. It is the pattern diagram which looked at the CMOS circuit from directly above. 1 ... Glass substrate, 2 ... Display unit, 3 ... Scanning circuit, 4
...... Signal circuit, 5 …… External control circuit, 6 …… Multiplexer, 7 …… Buffer circuit, 8 …… Shift register circuit, 9 …… 1 line gate-source capacitance C _GS , 10
...... Line memory, 11 …… 1 pixel liquid crystal capacity Clc, 1
2 ... Intrinsic polycrystalline silicon film, 13 ... P (phosphorus) -doped polycrystalline silicon film, 14 ... B (boron) -doped polycrystalline silicon film, 15 ... Al (grounded),
16 ... Al (connected to power supply voltage _VDD ), 17 ... Al (output section), 18 ... silicon oxide film, 19 ... P (phosphorus), or B (boron) -doped polycrystalline silicon Membrane (gate of transistor), 20 …… Silicon nitride film, 21 …… CM
OS circuit input (Al), 22 ... CMOS circuit output (A)
l), 23 ... Polycrystalline silicon film.

Claims (3)

[Claims] 1. A first terminal to which a first input signal having a first or second potential level is applied, and a first terminal which has a complementary second or first potential level. A second terminal to which the second input signal is applied, first and second power supply potential terminals, third and fourth terminals for outputting a signal, and the source / drain path is the first power supply. At least one first MOS transistor connected between the potential terminal and the fourth terminal, the gate of which is connected to the first terminal; and a source / drain path of the fourth terminal and the second terminal. At least one second MOS transistor having a gate connected to the second terminal, and a source / drain path having the first power supply potential terminal and the third terminal. And a gate connected to the fourth terminal. At least one third MOS transistor, at least one source / drain path connected between the third terminal and the second power supply potential terminal, and a gate connected to the first terminal. A unit circuit including a fourth MOS transistor, and a plurality of the unit circuits described above. Each unit circuit has a source / drain path of the first terminal and a third terminal of another adjacent unit circuit. And a second transfer gate transistor connecting the second terminal with the source / drain path connecting the second terminal and the fourth terminal of the adjacent other unit circuit. The first transfer gate transistor and the second transfer gate transistor, which are continuous through the unit circuit, are alternately connected to the first gate. A first clock signal and a second clock signal are applied, and the first terminal and the second terminal of every other unit circuit of the continuous unit circuit are used as a first output terminal and a second output terminal, and A liquid crystal drive device characterized in that a liquid crystal display is driven through the first and second output terminals. 2. The source / drain path according to claim 1, the source / drain path being connected between the third power supply potential terminal and the scan electrode of the liquid crystal display, and the gate being the first electrode.
A fifth MOS transistor connected to the output terminal of the liquid crystal display, a source / drain path connected between the fourth power supply potential terminal and the scan electrode of the liquid crystal display, and a gate connected to the second output terminal. And a sixth MOS transistor, which is a liquid crystal driving device. 3. The device according to claim 1, wherein the first output terminal and the second output terminal are connected to two input terminals of a 2-input 2-output buffer circuit, and a source / drain path is a second path. A fifth MOS transistor connected between the power supply potential terminal 3 and the scan electrode of the liquid crystal display, the gate of which is connected to one terminal of the buffer circuit, and the source / drain path of which is the fourth power supply potential terminal. A liquid crystal driving device comprising: a sixth MOS transistor connected between the scanning electrode of the liquid crystal display and the gate of the liquid crystal display, the gate being connected to the other terminal of the buffer circuit.