JPH0671256B2 - Clock input circuit - Google Patents

Description

The present invention relates to a clock input circuit that receives a clock from another device via a transmission path, and more particularly to an input stage of a system that operates by receiving a master clock from the outside. Is provided in
The present invention relates to a clock input circuit capable of shaping the waveform of the master clock and determining whether the master clock is normal or not.

(Prior Art) FIG. 2 is a diagram showing a configuration of a data processing device 10 including a receiver 1 as a clock input circuit. Since this type of clock input circuit comprises only the receiver 1, when the level of the input clock signal 6 exceeds the threshold voltage of the receiver 1, all the clocks are supplied to the internal circuit 8 as normal clocks.

(Problems to be Solved by the Invention) The above-described conventional clock input circuit does not have a function of determining whether or not the input clock is normal. If such a clock input circuit is used, the input interface line (clock transmission side driver, transmission line and receiver 1)
When the oven is in the oven or short
Since it is not possible to determine that there is no clock on the 10 side, it is not possible to respond appropriately when there is no clock input,
Device 10 ceases to function. Also, the clock signal 6
Even if the frequency fluctuates significantly, the signal cannot be determined to be abnormal, and the entire device 10 malfunctions. The conventional clock input circuit has such a problem.

Therefore, an object of the present invention is to provide a clock input circuit capable of determining the presence or absence of an input clock signal and the correctness of the frequency, and capable of outputting a shaped clock signal by interfacing with a transmission line as in the conventional case. is there.

(Means for Solving Problems) A clock input circuit provided by the present invention in order to solve the above problems is a receiver which receives a clock signal from the transmission line by interfacing with the transmission line. A bandpass filter that receives the output of the bandpass filter, a comparator that receives the output of the bandpass filter, and a rectifier circuit that receives the output of the comparator and that generates a correctness determination signal that indicates whether the clock signal input to the receiver is normal. When the level of the signal received from the transmission line exceeds a predetermined value, the receiver outputs a pulse signal having a width of a period in which the level of the signal exceeds the predetermined value, and the band-pass filter outputs the pulse signal of the clock signal. Pass only signals in the frequency band corresponding to the predetermined repetition period,
The comparator has a hysteresis characteristic, when the level of the output of the bandpass filter exceeds a predetermined threshold value, the output of the bandpass filter is shaped into a clock signal having a duty ratio of about 50%, and the rectifying circuit, If the output of the comparator is a clock signal having a level and a duty ratio within a predetermined range, a signal of a first logic value level is output as the correctness determination signal, and the output of the comparator is a level or a duty outside the predetermined range. If the clock signal is a ratio clock signal or a DC level signal, a signal having a second logic value level is output.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram showing a data processing device 9 provided with an embodiment of a clock input circuit of the present invention. The clock input circuit of this embodiment comprises a receiver 1, an amplifier 2, a bandpass filter 3, a comparator 4 and a rectifier circuit 5.

The clock signal 6 input from the outside via the transmission path is input to the receiver 1 where the signal level is determined. The receiver 1 outputs a clock having the same frequency as the input clock frequency when receiving a signal of a specified level or higher, and when the level of the input signal is a specified value or less, it is an H (high potential) level or an L (low potential) level. ) Output a constant level and do not output the clock. The amplifier 2 at the next stage is a driver for driving the bandpass filter 3. The output of the receiver 1 is sent to the bandpass filter 3 via the amplifier 2.
The band-pass filter 3 allows a prescribed frequency component to pass therethrough, and largely attenuates other frequency components. Clock signal 6
Is within the specified frequency range, the band filter 3
Output level becomes higher than the threshold level of the comparator 4 having the hysteresis characteristic in the next stage, and the waveform-shaped clock is output as the output of the comparator 4, but if not, the output of the comparator 4 becomes H or L
It becomes a constant level output of. The clock 14 shaped by the comparator 4 is a rectangular wave with a duty ratio of about 50%.
It is rectified by the rectifier circuit 5 in the next stage. The rectifier circuit 5 outputs an H level signal if the clock 14 has a level and duty ratio within a predetermined range, and when there is no clock 14 (H or L level) or the level or duty ratio is not within a predetermined range. Sometimes it outputs an L level signal.
Therefore, it is possible to know whether or not the internal circuit 8 which has received the correctness determination signal 15 of the output of the rectifier circuit 5 is receiving the normal clock, and when not receiving the normal clock, the internal circuit 8 itself does the clock. Can be generated and run on its own clock.

In the embodiment shown in FIG. 1 described above, since the band filter 3 is provided, it is possible to know whether the frequency of the clock signal 6 is correct or not. When the input interface line becomes open or becomes short, the output of the band filter 3 becomes a constant level of H or L, and the clock signal does not appear at the output of the comparator 4. At this time, the rectifying circuit 5 outputs the L level. . Therefore, in this embodiment, an open or short circuit of the input interface line can also be determined as an abnormality of the clock signal 6. Further, in the embodiment shown in FIG. 1, since the rectification circuit 5 determines whether the clock 14 is correct or not, it is also possible to determine whether the duty ratio of the clock 14 given to the internal circuit 8 is correct or not. Further, in this embodiment, since the band filter 3 is provided, noise superimposed on the clock signal 6 can be removed.

(Effects of the Invention) As described in detail above, according to the present invention, the presence or absence of the input clock signal and the correctness of the frequency can be determined, and the interface with the transmission line can be removed as in the conventional case, and the shaped clock is shaped. A clock input circuit that can output a signal can be provided.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a data processing device having a clock input circuit according to an embodiment of the present invention, and FIG. 2 is a block circuit diagram showing a data processing device having a conventional clock input circuit. 1 ... Receiver, 2 ... Amplifier, 3 ... Band filter,
4 ... Comparator, 5 ... Rectifier circuit, 8 ... Internal circuit, 9 ... Data processing device for inputting clock.

Claims (1)

[Claims] 1. A receiver that receives a clock signal from the transmission line by interfacing with the transmission line, a bandpass filter that receives the output of the receiver, a comparator that receives the output of the bandpass filter, and an output of the comparator, A rectification circuit that generates a correctness determination signal that indicates whether the clock signal input to the receiver is normal, and the receiver receives the level of the signal when the level of the signal received from the transmission line exceeds a predetermined value. Outputs a pulse signal having a width exceeding a predetermined value, the bandpass filter passes only a signal in a frequency band corresponding to a predetermined repetition period of the clock signal, and the comparator has a hysteresis characteristic. , When the output level of the bandpass filter exceeds a predetermined threshold, Is shaped into a clock signal with a duty ratio of about 50%, and the rectification circuit uses the first logical value as the correctness determination signal if the output of the comparator is a clock signal with a level and duty ratio within a predetermined range. A level signal, and the output of the comparator is a clock signal of a level or duty ratio outside the predetermined range, or DC
A clock input circuit which outputs a signal of a second logical value level if it is a level.