JPH0673103B2 - Floating point multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a floating point multiplication circuit suitable for a computer that processes floating point numbers.

(Prior Art) In the method of processing multiplication of floating-point numbers by addition of multiples, processing of the mantissa part is conventionally performed using the circuit of FIG. That is, in the configuration of FIG. 3, input data X, Y
When the product (mantissa part product) Z is obtained by multiplying (mantissa part of), X is selected by Y by the multiple generation circuit 11.
Multiples of are generated. The selection of the multiple of X is generally performed by shifting the value of X to the left by 1 bit in accordance with the bit weight of the input data Y.
The same number of multiples as that of Y bit widths occur. The product Z is obtained by adding all these multiples,
Carry look ahead adder (below,
With CLA), the carry time propagates up to the upper bits for each multiple addition, so the delay time becomes too large. Therefore, as shown in FIG. 3, a carry save adder (hereinafter referred to as CSA) 12 of a carry saving system is used.

In CSA12, PA (consisting of 2 bits of PA1 and PA2), PB (consisting of 2 bits of PB1 and PB2), and 2 bits of 3 inputs of PC (consisting of 2 bits of PC1 and PC2) in FIG. As shown in the example, carry C of adder 12-1 is the upper adder in the same row.
It does not propagate to the carry input CI of 12-2, but becomes the carry input of the upper adder 12-4 of the next-stage adders 12-3 and 12-4. Therefore, by passing through the number of inputs to be added-1 adder, two partial products, that is, PD, which is the addition result without carry propagation of PA, PB, and PC, and PE, which is a stored carry group, are added. Obtainable. The product is obtained by adding these two partial products by CLA (# 1) 13 shown in FIG.

Now, the product generated by CLA (# 1) 13 is (bit width of data X) + (bit width of data Y) bit width (usually
Since X and Y have the same bit width, they have a bit width twice as long as the input data. However, for floating point multiplications, the resulting bit width must also be the same as the input bit width. Therefore, as shown in FIG. 5, CLA (# 1) 13
Of the product 14 which is the output result of, the data 15 for the number of bits required for the product of the floating point number is taken out from the higher order, and the lower order bit 16 next to this data 15 is used as the carry input of the CLA (# 2) 17. 0 rounding to 1 (that is, rounding operation) is performed, and the final multiplication result (product) Z of the input data X and Y is obtained.
Ask for.

(Problems to be Solved by the Invention) As described above, in the conventional floating-point multiplication circuit, CSA is used to reduce carry propagation and delay time. But to get the product, CLA (#
After carrying the carry according to 1), round off the next round.
Since it is carried out by CLA (# 2), there is a problem in that carry is propagated twice and the mantissa processing of floating-point multiplication cannot be sufficiently speeded up.

Therefore, it is an object of the present invention to prevent double carry propagation from occurring and thus to speed up the mantissa processing of floating-point multiplication.

[Structure of the Invention] (Means for Solving the Problem) The present invention inputs a mantissa part of two floating-point numbers to be multiplied, generates a plurality of multiples, and carries a carry for the plurality of multiples. Is performed to obtain a first partial product that is the addition result and a second partial product that is a saved carry group, and the product of the mantissa part is calculated based on the first partial product and the second partial product. In the floating point multiplication circuit to be generated, a first adder for performing addition with carry propagation of the lower part of the first and second partial products, and no carry propagation for upper part of the first and second partial products A second adder that performs addition, a result of the addition of the second adder, a stored carry group, a carry to the upper part generated by the addition of the first adder, and a bit required by adding a rounding bit Generate the product of the mantissas of numbers 3 is characterized by providing an adder.

(Operation) According to the above configuration, the second and second partial products are divided into the upper part and the lower part, and the lower part is added by the first adder with carry propagation, and the upper part is added. Is added by the second adder without carry propagation. Then, the addition result of the second adder, the stored carry group and the carry and rounding bit to the upper part generated by the addition of the first adder are added in the third adder, and the mantissa product is generated and rounded. And are done at the same time. As is apparent, regarding the above addition of the first and second partial products, carry propagation does not occur in the upper part, and therefore the mantissa processing speed of floating-point multiplication is improved.

(Embodiment) FIG. 1 shows a block configuration of a floating point multiplication circuit according to an embodiment of the present invention. In the figure, 21 is (the mantissa part of) the two multiplication target input data represented by a floating point number.
A multiple generation circuit (corresponding to the multiple generation circuit 11 in FIG. 3) that generates a plurality of multiples (groups of partial products) based on X and Y,
22 is a carry-preserving adder without carry propagation, which adds two or more multiples generated by the multiple generation circuit 21 at high speed to generate two partial products 23, 24 (here, 4 bits);
That is, CSA (carry save adder) (corresponding to CSA12 in FIG. 3). 25 is the two partial products 2 generated by CSA22
An adder with carry propagation that adds the lower half of 3,24 to the carry 26 and round bits 27 to the upper half, i.e.
CLA (Carry Look Ahead Adder), 28 adds the upper half of the two partial products 23,24 generated by CSA22 to generate two partial products 29,30 with a bit position difference of 1 bit
It is SA. In this example, the partial product 29 shows the addition result of the upper half of the partial products 23 and 24 without carry propagation.
30 from each bit position during this addition (not propagated)
5 illustrates a group of stored carry output bits. 31 is CSA28
Carry from two partial products 29,30 and CLA25 generated by
26 is a CLA that adds 26 and rounding bit 27 to produce the mantissa product Z of a floating point number.

Next, the operation of the configuration shown in FIG. 1 will be described.

First, when the mantissa part of X, Y2 pieces of input data is input, the multiple generation circuit 21 generates a plurality of multiples (partial products) of X selected by the input data Y. The multiples generated by the multiple generation circuit 21 are input to CSA22. CSA22 is based on multiple multiples from multiple generation circuit 21
It produces two partial products 23, 24 with a bit width twice that of X, Y. The partial product 24 is the result of addition of multiple multiples without carry propagation, and the partial product 23 is the carry group stored in this addition without carry propagation. The operation up to this point is the same as the operation of the multiple generation circuit 11 and CSA12 in the conventional floating point multiplication circuit shown in FIG.

When two partial products 23 and 24 are generated by the CSA 22, it is common to add the partial products 23 and 24 to generate a product and perform a rounding operation. However, if the rounding operation is performed after the product having the double bit width is generated, the carry propagation is once performed to the highest level, and then the carry propagation is performed to the highest level again in the rounding operation. , Not efficient. Therefore, in this embodiment, the lower half of the partial products 23 and 24 are added by CLA25, and the combination of CSA28 and CLA31 gives
The mantissa part product Z of the floating point number is generated by simultaneously performing the addition of the upper half of the partial products 23 and 24 and the rounding operation. The operation of this addition will be described with reference to FIG. 2 together with FIG. 1 showing an example in which the bit width of the mantissa part is 2 bits.

First, from CSA22 shown in Figure 1, the bit width is the input data X, Y.
Two partial products (4 bits in this case) 23, 24 that are twice the (mantissa) are output. The lower half (lower 2 bits) of each of the partial products 23 and 24 is input to the CLA 25. This C
LA25 is composed of a full adder for 2 bits. In this example, since the input data is only 2 bits long, the carry is connected by ripple carry, but when the bit length is long, the look-ahead carry method is generally applied. The CLA 25 adds the lower 2 bits of each of the partial products 23 and 24 to generate a carry 26 for the lower half and the upper half of the double-width product. Of these, what is needed to generate the mantissa part of the product is the carry 26 to the upper part and the rounding bit 27 which is the most significant bit (MSB) of the lower half of the product, and the others are unnecessary. .

On the other hand, the upper half (upper 2 bits) of each of the partial products 23 and 24 is input to CSA 28. CSA28 is the above-mentioned CLA25
In parallel with the addition of the lower 2 bits of the partial products 23, 24 in, the addition of the upper 2 bits of the partial products 23, 24 is performed. This CSA
In 28, since there is no carry propagation and there is no carry propagation from CLA25 (because of addition of lower 2 bits), addition is completed before addition of CLA25 (addition of lower 2 bits), and carry propagation Partial product 29, which is the result of the addition of the upper 2 bits, and the saved carry 1 bit (generally, if the bit length is n, the carry bit is n).
A partial product 30 which is −1 bit) is generated. Here, since the product never exceeds the double length, there is no carry output from the most significant bit. That is, the partial product 30 is 1 bit less than the partial product 29.

The partial products 29 and 30 generated by CSA28 are input to CLA31.
The carry 26 and rounding bit 27 generated by the CLA 25 are also input to the CLA 31. CLA31 is a partial product from CSA28
29 (that is, the carry result without carry propagation of the upper two bits of the partial products 23 and 24) and the partial product 30 (that is, a carry bit that is not propagated when the higher two bits of the partial products 23 and 24 are added, here, 1 bit), and Carry 26 from CLA 25 and rounding bit 27 are added, that is, the mantissa part of X, Y (2 bits)
2 bits of product (mantissa part product) Z are obtained by simultaneously generating and rounding the upper 2 bits of the product of.

In the floating-point multiplication circuit described above, when the mantissa part of the input data has a 2-bit structure, carry propagation occurs only for 2 bits in CLA25 and 2 bits in CLA31, that is, a total of 4 bits. On the other hand, in the conventional floating point multiplication circuit, carry propagation for 4 bits for product generation and carry for 2 bits for rounding operation for a total of 6 bits. That is, according to this embodiment, when the mantissa part of the input data has a 2-bit structure, the carry of two bits is not required to be propagated as compared with the conventional case, and the processing speed can be increased.

As described above in detail, according to the present invention, the addition of partial products is executed by dividing it into an upper part and a lower part, and an addition without carry propagation is performed on the upper part to correct the addition. Since the addition of is carried out at the same time as the rounding operation by the adder having carry propagation, it is possible to prevent double carry propagation from occurring in the upper part and to speed up the mantissa processing of the floating point multiplication.

[Brief description of drawings]

1 is a block configuration diagram of a floating point multiplication circuit according to an embodiment of the present invention, and FIG. 2 is a block configuration diagram showing a specific configuration of a portion of the circuit of FIG. 1 directly related to the present invention.
FIG. 3 is a block diagram showing a conventional example, FIG. 4 is a diagram showing a specific configuration of a part of the CSA12 shown in FIG. 3, and FIG. 5 is a diagram for explaining a rounding operation in the configuration shown in FIG. Is. 21 …… Multiple generation circuit, 22 …… CSA (Carry save adder), 23,24,29,30 …… Partial product, 25 …… CLA (Carry look ahead adder, first adder), 26 …… Carry,
27 …… Rounding bit, 28 …… CSA (second adder), 31 …… C
LA (third adder).

Claims (1)

[Claims] 1. A mantissa part of two floating-point numbers to be multiplied is input to generate a plurality of multiples, a carry-propagation-free addition is performed on the plurality of multiples, and the result is the addition result. In the floating-point multiplication circuit that obtains the partial product of and the second partial product which is the stored carry group and generates the product of the mantissa part of the required number of bits based on the first partial product and the second partial product, A first adder for performing a carry-propagated addition of the lower part of the first and second partial products to generate a carry and rounding bit to the upper part; and an upper part of the first and second partial products Carry carry-free addition and generates a third partial product which is the result of addition and a fourth partial product which is a stored carry group, and a second adder of a carry saving method, and this second adder. 3rd and 4th partial products from And a third adder for adding the carry and rounding bits from the first adder to generate the product of the mantissa part of the required number of bits.