JPH0673128B2 - Memory control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a storage control system for a computer system, and more specifically, to a plurality of access request control devices operating in parallel in synchronization with each other, and to a storage device. The present invention relates to a storage control method suitable for ensuring the order of access requests issued.

[Conventional technology]

A conventional storage control method in the case where a plurality of access request control devices issue access requests to a storage device composed of a plurality of independently accessible storage units (storage banks) will be described with reference to FIG.

In FIG. 2, 20A to 20D are access request control devices, which are sources for issuing access requests. 21A to 2
1D is an access request stack device, which stacks access requests issued from the access request control devices 20A to 20D, respectively, and issues access requests in the order in which they are stacked.
According to the address information, it is sent to any of the access request priority order determination devices 22A to 22D. The access request priority order determination devices 22A to 22D correspond to the respective storage banks of the storage device 23, and the access request stack device 21A, respectively.
To 21D to determine the priority order among the access requests sent. The storage device 23 comprises storage banks 23A to 23D.

As for the access request control device 20A, the access request issued from the device 20A is stacked on the stack circuit 211 in the access request stack device 21A, and the control unit 21A
Access request priority order determination device 22A corresponding to the storage bank designated by the address of the access request in accordance with the instruction of 0
To 22D. The access request priority order determination devices 22A to 22D determine the priority order among the access requests sent from the access request stack devices 21A to 21D, and select one of them to send it to the corresponding storage bank of the storage device 23. As for the access request priority determination device 22A, the access request stack device 2
The priority order determination logic unit 220 determines the priority order among the access requests sent from 1A to 21D, and one of the access requests is selected and sent to the bank 23A of the storage device 23. Further, the access request selection notifying circuit 221 notifies the access request stacking devices 21A to 21D that the access request has been selected. At this time, the access request not selected is kept waiting at the entrance of the priority order determination logic unit 220.

The access request is sent to the access request control device 20A until the stack 211 of the access request stack device 21A is full.
Sent from. Further, the access request stack device 21A outputs a signal 213 indicating that the access request 212 issued during the previous machine cycle (a periodic constant time interval in which the sequential circuit groups forming the system operate in synchronization) is selected.
However, for example, when the access request priority determination device 22A returns, a subsequent access request 212 is transmitted. This is for guaranteeing the reading and writing of data with respect to the storage device 23 in the order of access requests issued from the access request control device 20A.

Incidentally, as one related to this type of storage control system, for example, in Japanese Patent Laid-Open No. 60-136849, in order to improve the performance of the entire system, a number of access requests issued by the access request control device are issued in the order of request generation. The access request is issued by dividing it into unit groups and adding the access request identifiers of 0 to (a-1) to each of the a access requests.
In the access request priority order determination device directly connected to the storage unit, the access request control device is returned to the access request control device with the minimum a
It is shown that up to individual access requests can be continuously issued without being aware of whether or not they have been selected by the access request priority determination device.

[Problems to be solved by the invention]

A vector processing device for high-speed processing of scientific and technological calculations includes a vector register for holding vector data, an arithmetic unit for operating the data, and a plurality of access request control devices for controlling data transfer between a storage device and the vector register. In many cases, a so-called element parallel processing method is adopted in which the elements in one vector instruction are simultaneously allocated to a plurality of resources of the same type (vector register, arithmetic unit, access request control device, etc.) and processed in parallel. ing.

In this case, generally speaking, it is desirable that resources of the same type operating simultaneously in element parallel processing process elements allocated in perfect synchronization. By operating in synchronization, it becomes possible to share a control circuit between the same type of resources operating in parallel, and the control logic can be simplified. At this time, what becomes a problem is the occurrence of waiting time due to access competition to the storage banks constituting the storage device. Therefore, in order to operate in synchronization between a plurality of resources of the same type, a storage processing method that absorbs the gap between resources due to the waiting time and realizes completely synchronized storage device access is required. is there.

However, the conventional storage control method described above is premised on that one access command is assigned to one access request control device and processed, and the element in one vector access command is divided into multiple access request control devices. However, no consideration has been given to the case of allocating and processing in parallel, and there is a problem that access requests cannot be processed in synchronization among a plurality of access request control devices that operate in parallel.

An object of the present invention is to provide a list vector as well as a load instruction for reading data from a memory in a vector processing device or the like for dividing and allocating elements of one vector access instruction to a plurality of access request control devices. A storage control method that guarantees the order even when the memory access address is a random instruction, such as in the case of a store, synchronizes the access request control devices, and enables high-speed access request issuance. Especially.

[Means for solving problems]

The present invention relates to a plurality of access request control devices for processing one access command by adding a different number of access request identifiers to access requests issued from the access request control device to the access request stack device. Means for detecting that all access requests having the same access request identifier issued by the are selected by the access request priority order determination device and permitting issuance of subsequent access requests by this signal. And

[Work]

When an access operation for a series of data such as vector data is divided into a plurality of access request control devices and assigned and processed, the access request issued by each access request control device is commanded by the information of the access request. It is identified and divided into units of division numbers that differ depending on the type of the instruction. This is executed by the access request stack device. For example, a simple load instruction is a, and a simple store instruction is b.
If the list vector is stored, the list vector is divided into one.
And for each access request, Numb at the time of simple load instruction
er0- (a-1), Number0- (b for simple store instruction
-1), when a list vector store command is issued, an access request identifier such as Number0 is added in the order of access request generation, and the access request is sent to the access request priority order determination device. On the other hand, in the access request priority determining device directly connected to the storage unit, it is confirmed that all access requests having the same access request identifier issued by a plurality of access request control devices dividing one access instruction are selected. The identifier of the indicated access request is returned to the access request stack device.

In the access request stack device, for example, at the time of storing a list vector, if a signal indicating that all access requests have been selected is returned, the next access request is sent to the priority order determination device. Further, in the simple vector load instruction, up to a maximum number of access requests are continuously issued without waiting for a signal indicating that all the access requests issued by the access request control device have been selected by the priority determination device. It becomes possible. Further, in the simple vector store instruction, since the same address on the memory cannot be accessed, a signal indicating that all the access requests issued by the access request control device have been selected by the priority order determination device is waited for. Instead, it becomes possible to issue up to b access requests in succession.

As a result, it becomes possible to send access requests issued by a plurality of access request control devices that divide one instruction in parallel while ensuring the order of the elements.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows an example of the configuration of the main part of a computer system that employs the present invention. Here, the computer system includes a plurality of (four in this embodiment) arithmetic units 30A to 30D and the arithmetic units 30.
Vector register devices 31A to 31D having a role of a data buffer between the storage device 35 and the storage device 35, access request control devices (access request means) 32A to 32D, a storage control device 33 and a storage device 35. The storage device 35 includes a plurality of storage banks (4 in this embodiment) that can be independently accessed.
The storage control device 33 is composed of 35A to 35D, and as a result of decoding the address information accompanying the access request, which storage bank to access is determined. Storage controller
Reference numeral 33 includes access request stack circuits 33A to 33D corresponding to the access request control device, and access request priority order determining circuits (access request priority order determining means) 34A to 34D corresponding to the storage banks.

In the computer system shown in FIG. 3, an outline of operation of operation and writing when the element parallel processing method is applied will be described.

When computing the data already stored in the vector registers 31A to 31D, each element of the vector is assigned to the computing units 30A to 30D as follows, the computation process is performed, and the computation result is stored again in the vector register. .

In this arithmetic operation, the four arithmetic units 30A to 30D perform arithmetic operations in perfect synchronization. For example, the arithmetic results of the 0th, 1st, 2nd and 3rd elements are obtained at the same time, and the vector register 31
Stored in A to 31D. Vector registers 31A thru 3
The allocation of each element stored in 1D is shown below.

Next, when writing the data stored in the vector registers 31A to 31D to the storage device 35, each element is stored in the access request control devices 32A to 32D. 4 elements, for example, the 0th, 1st, 2nd and 3rd elements are sent to the corresponding access request stack circuits 33A to 33D of the storage controller 33. In each of the stack circuits, based on the address information of the access request, it is sent to any of the target priority order determining circuits 34A to 34D. When a plurality of access requests compete with each other, each priority determination circuit selects one access request according to a predetermined priority and sends it to the corresponding storage banks 35A to 35D.

As described above, each of the four arithmetic units 30A to 30D,
Vector registers 31A to 31D, access request control device
32A to 32D process each element in synchronization. Therefore,
In the element parallel processing method of operating in synchronization, four arithmetic units 30A to 30D, vector registers 31A to 31D, and access request control units 32A to 3 are controlled by one control system logic.
It can have a logical configuration that controls 2D.

However, in the storage control device 33, due to the state of the storage bank to be accessed (in use in the preceding access request, etc.) and competition with other accesses, the access request control devices 32A to 32A are connected.
Each of the four access requests sent simultaneously by the 2D synchronously may not be processed at the same time, which may cause a time lag in the access requests to the storage banks 35A to 35D. Therefore, a control method for absorbing and transmitting the time difference is required.

The synchronous control method according to the present invention in the storage controller 33 will be described below with reference to FIGS. 1 and 4. 1 and 4 are block diagrams of an embodiment of the present invention. FIG. 1 shows a configuration example of each access request stack circuit 33A to 33D in the storage controller 33, and FIG. 4 shows an access request stack. The connection relationship between the circuits 33A to 33D and the priority determination circuits 34A to 34D is shown.

The four access requests issued from the access request control devices 32A to 32D arrive at the access request stack circuits 33A to 33D in the storage control devices corresponding to the respective elements. For example, the access request arriving at the access request stack circuit 33A is sent to one of the stacks S0 (10A), S1 (10B), S2 (10C), and S3 (10D) indicated by the stack input control circuit 11, for example, S0 (10A). Set. The stack input control circuit 11 uses the stack position S0 where the access request should be stored.
A circuit for instructing ~ S3 to the stack by the control signal 11a, and every time an access request is stacked, the signal 11a indicating the stack position to be stored next is S0 → S1 → S2 → S3.
→ Send as S0.

On the other hand, the access request stored in the stacks S0 to S3 is sent from the stack position indicated by the stack output control circuit 12, for example, the stack S0 to the access request sending control circuit 15 and at the same time sent to the instruction identifying circuit 13. Here, the stack output control circuit 12 indicates the value of the stack position from which the access request should be taken out from S0 → S3 by the signal 12a, and like the stack input control circuit 11, the stack output control circuit 12 operates like S0 → S1 → S2 → S3 → S0. ,
The value is changed every time the access request transmission control circuit 15 outputs the access request to the priority order determination circuits 34A to 34D.

The instruction identifying circuit 13 identifies whether the instruction is a simple load instruction, a simple store instruction, or a list vector store instruction based on the access request information extracted from the stack circuits 10A to 10D. Send a signal indicating that the load instruction is fetched from the stack circuit to the simple load instruction output control circuit 14A, and if it is a simple store instruction, send a signal indicating that the simple store instruction is fetched from the stack circuit for the simple store instruction. Output control circuit
If it is a list vector store instruction, a signal indicating that the list vector store instruction is fetched from the stack circuit is sent to the list vector store output control circuit 14C.

The output control circuit 14A for a simple load instruction is composed of a counter for values 0 to (a-1) and a flip-flop corresponding to bits 0 to (a-1). The output control circuit 14B for a simple store instruction is composed of a counter having a value from 0 to (b-1) and a flip-flop corresponding to a bit from 0 to (b-1). 14c is composed of a 1-bit flip-flop. The counter value of each control circuit 14A, 14B, 14C is
An access request identifier indicating the access request issuance order of each instruction is given to the access request sending control circuit 15 by the signal line 18, and a signal (sendable signal) based on the state of the flip-flop corresponding to the counter value is a signal line. It is also given to the access request transmission control circuit 15 by 17. The access request transmission control circuit 15 is a circuit for controlling whether or not the access request extracted from the stacks 10A to 10D may be transmitted to the priority order determination circuits 34A to 34D, and the access request signal extracted from the stacks 10A to 10D. , An AND gate with a send enable signal 17 sent from each command output control circuit 14A to 14C. When both signals are logically "1", an access request identifier 18 is added to the access request. It is sent to the priority order determination circuits 34A to 34D.

Explaining the list vector store instruction, an access request for the list vector store instruction is issued from the access request control devices 32A to 32D and is stacked on the stacks 10A to 10D in the access request stack circuits 33A to 33D. Here, it is assumed that FIG. 1 shows the access request stack circuit 33A. Now, assume that the stack input control circuit 11
If the stack position instruction by S0 is S0, the access request of the access request control device 32A is stacked in S0 (10A). The stack input control circuit 11 updates the stack position indication at the same time as being stacked to S1. When the next access request arrives from the access request control device 32A, the stack input control circuit 11 stacks the access request in S1 (10B) and sets the stack position indication to S2. The access request control device 32A issues access requests until the stacks 10A to 10D are full.

On the other hand, the stack position indicated by the stack output control circuit 12
When the instruction identifying circuit 13 recognizes the access request fetched from S0 as a list vector store instruction, it is input to the list vector store instruction output control circuit 14C. In the output control circuit 14C for store instruction of list vector, there is a flip-flop for sending control, and its initial state is "0". The flip-flop is a flip-flop for inhibiting transmission of an access request, and "0" means that transmission is possible. In the initial state, since the flip-flop is "0", the transmission enable signal 17
Set to "1" and send. Access request transmission control circuit 15
AND's the send enable signal 17 with the access request signal fetched from the stack S0 and both are "1", so the access request (added access request identifier is 0) is given priority to the storage bank. Ranking circuit 34A to 34D
Send to. At the time of transmission, the flip-flop in the list vector store instruction output control circuit 14C is set to "1" to suppress the transmission of the subsequent list vector store access request.

The access request arriving at the priority order determination circuits 34A to 34D corresponding to the storage banks is given a predetermined priority order (for example, 33A> 33B).
>33C> 33D), the detection signal 16 is set to "1" when the detection circuit 40A to 40D detects that all the access requests sent from the access request stack circuits 33A to 33D have been selected. . The detection signal 16 is "1"
Then, the flip-flop is reset to "0" in the output control circuit 14C for the store instruction of the list vector.

There are cases where the address is random like a list vector store instruction and a plurality of access requests are sent to the priority order determination circuits 34A to 34D of the same storage bank depending on the address information. The flip-flop is not reset to "0" because the signal for detecting that the access request has been selected does not become "1" until all the access requests have been sent to the storage bank. Not sent from. In this way, the order of the store instructions of the list vector is guaranteed.

Next, processing of simple load and store instructions will be described. In the following description, parentheses correspond to store instructions.

An access request of a simple load (store) instruction is issued from the access request control devices 32A to 32D and is stacked in the access request stack circuits 33A to 33D. Stack control is the same as in the case of storing list vectors. The access request fetched from the stack circuit is an instruction identification circuit
Input to 13 and recognized as a simple load (store) instruction. Simple load (store) sending control circuit 14A (14B)
Has a counter of 0 to a-1 bit (0 to b-1 bit) and a flip-flop corresponding to 0 to a-1 (0 to b-1).

Now, it is assumed that the access request of the simple load (store) instruction is fetched from the stack circuit S0, input to the simple load (store) transmission control circuit 1A (14B), and simultaneously input to the access request control circuit 15. In the simple load (store) transmission control circuit 14A (14B), if the flip-flop is "0", the state can be transmitted, looking at the state of the flip-flop indicated by the counter value when the access request is input to the circuit.
If it is "1", the sending enable signal 17 is controlled so as to suppress sending. Considering the initial state, the counter value in the simple load (store) transmission control circuit is "0", and 0 to a-1 (0
To b-1) all the values of the flip-flops are "0". Therefore, when the access request of the simple load (store) instruction (the access request identifier to be added is 0) is input to the simple load (store) transmission control circuit 14A (14B), the counter value is "0" and becomes 0. Since the corresponding flip-flop is "0", the send enable signal 17 is set to "1". In the access request transmission control circuit 15, the transmission enable signal 17 is "1".
Therefore, the access request is sent to the access request priority determination circuits 34A to 34D according to the address information. When the access request is sent to the priority order determining circuits 34A to 34D, the simple load (store) sending control circuit 14A (14
The counter in B) is incremented and becomes "1". At the same time, the flip-flop corresponding to “0” is set to “1”. Next, when an access request for a simple load (store) is fetched from the stack circuit 10B, the flip-flop corresponding to "1" is "0", so that the access request (the added access request identifier is 1) is Similarly, the address information is sent to any of the access request priority order determination circuits 34A to 34D by address information. Hereinafter, access requests issued from the access request control devices 32A to 32D are sequentially processed in the same manner.

In this way, the access request is sent to the priority determination circuit 34A.
To max. "A-1" without waiting for selection in 34D
("B-1") can be sent. The access request order determination circuits 34A to 34D return that all access requests having the same access request identifier have been selected, and reset the flip-flop corresponding to the value of the access request identifier to "0". For example, it is detected that all the access requests having the above-mentioned access request identifier of "0" have been selected and returned, and the simple load (store) transmission control circuit
The flip-flop corresponding to the counter value of 14A (14B) "0" is reset to "0". As a result, when the counter makes one round and reaches "0", the access request to which the access request identifier "0" is added can be transmitted again.

〔The invention's effect〕

According to the present invention, in an element parallel processing system in which elements of one vector access instruction are divided and assigned to a plurality of access request control apparatuses and processed at the same time, the access request of each access request control apparatus is different for each instruction. By dividing into the number of divisions and processing, it is effective in significantly improving the access request processing capability of the storage control device.

Furthermore, in element parallel processing, it is possible to completely suppress variations in access request processing time due to storage device access, which is the main cause of disturbing the synchronous operation between elements, within the storage controller, and it is easy to implement the element parallel processing method. Has a great effect on the improvement of.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an access request stack circuit in a storage control device of the present invention, FIG. 2 is a diagram for explaining a conventional storage control system, and FIG. 3 is an object of the present invention. FIG. 4 is a diagram showing a configuration example of a computer system, and FIG. 4 is a diagram showing a connection relationship between the access request stack circuit and the priority order determination circuit of FIG. 10A-10D …… Stack circuit, 11 …… Stack input control circuit, 12 …… Stack output control circuit, 13 …… Instruction identification circuit, 14A-14C …… Instruction sending control circuit, 15 …… Access request sending control circuit , 32 ... access request control device, 33 ... storage control device, 33A to 33D ... access request stack circuit, 34A to 34D ... priority determination circuit, 35 ... storage device.

Claims (1)

[Claims] 1. A storage unit composed of a plurality of storage units that can be accessed independently, a plurality of access request units for issuing an access request to the storage unit, and an access issued by the plurality of access request units. In a storage control system of a computer system having an access request priority order determining means for determining a priority order between requests and transmitting the selected access request to a corresponding storage unit, the access request means issues the access request means for each access request means. Stack means for stacking access requests, stack input / output control means for controlling input / output of the stack means, means for identifying an instruction of an access request output from the stack means, and type of the identified instruction The access requests are grouped by and the access request issue order is shown for each access request. The access request identifier is added to the access request priority determining means, and the access request priority determining means receives a signal indicating that all access requests to which the same access request identifier is added from the access request priority determining means are received. A storage control system comprising: a control unit that permits the output of an access request to the stack input / output control unit.