JPH0675091B2 - Method of measuring thermal resistance of MOS FET - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to the thermal resistance of a MOS field effect transistor (hereinafter the field effect transistor may be referred to as FET), in other words, an increase in channel temperature per unit power consumption. A method of measuring the value, particularly the FET or IGT (INSULATED GATE TRANSIS) in a semiconductor device obtained by combining an MOS type FET and another semiconductor element to form an integrated circuit on one semiconductor chip.
TER) with respect to a method capable of easily measuring thermal resistance.

[Prior art and its problems]

First, a conventional method for measuring the thermal resistance of a MOS FET will be described. That is, FIG. 3 is a cross-sectional view showing an example of the structure of an N-channel MOS type FET, but the thermal resistance of such an FET is measured as shown in FIGS. 4 and 5. It is being appreciated. In FIGS. 3 to 5, S, G, and D are source terminals, gate terminals, and drain terminals, respectively, and Sa, Ga, and Da are electrodes provided on the FET so as to draw out the terminals, respectively. In this case, the n ⁺ region and the P region of the FET are connected to the source terminal S by the electrode Sa. Reference numeral 1 is an insulating film provided on this FET. Since the FET shown in FIG. 3 is normally used so that the load current flows from the drain to the source, it is clear from this figure that the P-type region and n
^There is a diode 2 connected between the drain and the source in the opposite direction from the drain to the source in the form of a -shaped region, and the forward voltage drop of the diode 2 in the internal reverse direction depends on the channel temperature of this FET. Changes uniquely. Therefore, the channel temperature can be known by measuring the forward voltage drop, and conventionally, the thermal resistance is measured by obtaining the channel temperature in this way. FIG. 4 is a measuring circuit diagram for explaining the first procedure of such a conventional thermal resistance measuring method. In FIG. 4, 3 is a power supply connection terminal to which a DC voltage of 50 [V] is connected.
Is for calibration of the same structure as the MOS FET that is the target of thermal resistance measurement
MOS type FETs 5 are variable resistors for current adjustment connected between the source terminal S of the FET 4 and the power supply connection terminal 3. In the figure, the FET 4 has a terminal G connected to a terminal S and a terminal D connected to a ground 6. Vsd shown in the figure is a source-drain voltage generated in the FET 4.

In FIG. 4, first, the FET 4 is placed in, for example, a constant temperature bath at a temperature of Tjr ₁ and a voltage of 50 [V] is applied to the terminal 3 to measure a minute predetermined size such that the channel temperature of the FET 4 does not rise. The current Id is caused to flow from the source to the drain by adjusting the resistor 5, and the voltage Vsd between the source and the drain at this time, that is, the forward voltage drop of the diode 2 shown in FIG. 3 is measured. This measured value is Vsd.
Next, the temperature of the constant temperature bath is changed to the temperature of Tjr ₂ , and in this temperature state, the resistor 5 is adjusted so that the same test current Id as the previous time flows between the source and drain of the FET 4, and the voltage Vsd is measured. When this measured value is Vsdr ₂ , the equation (1) is established, and therefore the coefficient Kd can be obtained from the equation (1) as in the equation (2). The coefficient Kd is a constant.

FIG. 5 is a measurement circuit diagram for explaining the procedure after the second procedure of the conventional thermal resistance measuring method. In the figure, 7 is a test MOS type FET for measuring thermal resistance. The FET 7 has the same structure as the calibration FET 4 described above. Reference numeral 8 is a DC voltage source whose output voltage is variable and whose negative electrode is connected to the ground 6, E is its output voltage, and 9 is a DC current source. I is a direct current based on the direct current source 9. In FIG. 5, the drain terminal D of the FET 7 is configured so as to be connected to the earth 6 or the positive electrode of the voltage source 8 by the changeover switch 10. 11 is a changeover switch for connecting the gate terminal G to either the source terminal S or the output terminal of the gate driver 13, and 12 is for connecting the source terminal S to the resistor 5 or the current source 9 by switching. This is a changeover switch. The other output terminal of the gate driver 13 is connected to the terminal S. The switches 10, 11, 12 are configured to work together.

In the conventional thermal resistance measuring method, after performing the operation described with reference to FIG. 4, the test MOS type FET7 is connected to the measuring circuit as shown in FIG. 5, and first, as a second procedure, the terminals are switched by the switches 10, 11 and 12. D is connected to the ground 6, terminal G is connected to terminal S, and terminal S is connected to the resistor 5, respectively, and the resistor 5 is adjusted so that the minute measurement current Id having the same magnitude as the above flows from the source to the drain. Then, the voltage Vsd is measured in this state. This measured value is Vsdm ₁ . Next, as the third procedure, the switch 10,
The gate driver 13 is driven by connecting the terminal D to the voltage source 8, the terminal G to the gate driver 13 and the terminal S to the current source 9 by 11,12. Then, the test current I defined by the current source 9 flows from the drain to the source, and E.
The electric power Pj corresponding to I is consumed in the FET 7, and as a result, the channel temperature in the FET 7 rises. Next, as the fourth procedure,
The switches 10, 11 and 12 are returned to the states of the second procedure described above, and the power Vsd is quickly measured before the channel temperature increased as described above is decreased. Of course, in this case, the power Id is made to flow from the source to the drain. Assuming that the value of the voltage Vsd measured in the fourth procedure is Vsdm ₂ , the above-mentioned increase value ΔTjm of the channel temperature is expressed by the equation (3).

ΔTjm = (Vsdm ₂ −Vsdm ₁ ) / Kd (3) Therefore, when ΔTjm is calculated by the equation (3) using the value of Kd obtained by the first procedure, the thermal resistance Rj of the FET 7 is calculated by the equation (4). Will be calculated.

Rj = ΔTjm / Pj (4) The conventional thermal resistance measuring method for the sample MOS FET 7 is as described above, but such measuring method has the following problems. That is, FIG. 6 shows an N channel MOS.
1 is a circuit configuration diagram of a semiconductor device 16 in which a FET 14 and a bipolar transistor 15 are combined and formed on one semiconductor chip. In this case, a source S of the FET 14 and a base B of the transistor 15 are connected, and a drain D of the FET 14 and a transistor 15 collectors C are connected. Reference numerals 17, 18 and 19 denote terminals connected to the drain D or collector C, the emitter E of the transistor 15 and the gate G of the FET 14, respectively, and 20 denotes a test terminal drawn from a connection point between the source S and the base B. Since the semiconductor device 16 is connected as described above, the signal voltage applied to the terminal 19 causes
The current flowing between 17, 18 is controlled, and since such a semiconductor device 16 has the FET 14, the input impedance is high, and a large current can be made to flow by the transistor 15. For this reason, the semiconductor device 16 is often used in a drive device for an electric motor, etc., but when the thermal resistance of the FET 14 in such a semiconductor device 16 is to be measured by the conventional method as described above, the drain D from the test terminal 20, in other words, For example, when the measurement current Id is made to flow toward the terminal 17, a reverse diode (not shown in the device 16) formed between the drain D and the source S, and between the collector C and the base B are formed. In the reverse bias direction formed on
Since the junction diode and the diode are connected in parallel in series, the measured current Id is shunted to both diodes, resulting in FET1
Before and after the operation of increasing the channel temperature by consuming electric power to 4, the shunt ratio of the measured current Id shunted to both diodes is different due to the temperature rise of the diodes, so there is a problem that the accurate thermal resistance cannot be measured. .

FIG. 7 is a sectional view showing the structure of a transistor called IGT (INSULATED GATE TRANSISTER).
23 is a terminal corresponding to each of the terminals D, S, G in FIG. 3, and 21a, 22a, 23a are electrodes Da,
Although it is an electrode corresponding to each of Sa and Ga, this transistor is greatly different from the FET shown in FIG. 3 in that a P ⁺ region is provided between the electrode 21a and the n ⁻ region. 7th
The IGT shown in the figure has the same configuration as the FET of FIG. 3 except that the P ⁺ region is provided in this way, so that the terminal 2
It is clear that the signal voltage applied to 3 controls the current flowing from terminal 21 to terminal 22,
In this case, since the diode formed by the P ⁺ region and the n ⁻ region in contact with the P ⁺ region has a current multiplication effect, the IGT
Is characterized in that a large output current can be obtained as compared with the FET of FIG. 3 which does not have the diode composed of the P ⁺ region and the n ⁻ region as described above. Therefore, this IGT is also used for an application similar to the application of the semiconductor device 16 shown in FIG. 6, but in this case, even if an attempt is made to measure the thermal resistance of this IGT by the above-mentioned measuring method, the IGT is directed from the terminal 22 to the terminal 21. reverse bias pn comprising the area ^- measured current Id flowing Te is above the P ⁺ region and the n
Since it is blocked by joining, IG
The thermal resistance of T cannot be measured.

That is, in the conventional thermal resistance measuring method using the temperature dependence of the forward voltage drop of the diode in the reverse direction in the MOS type FET described above, the conventional thermal resistance measuring method uses the MO resistance as shown in FIG. 6 and FIG.
There is a problem that the thermal resistance of the FET portion in a semiconductor device formed by combining an S-type FET and another semiconductor element on one semiconductor chip cannot be easily measured.

[Object of the Invention]

The present invention solves the above-mentioned problems in the conventional thermal resistance measuring method for a MOS type FET, so that the MOS type FET and another semiconductor element can be integrated into a single semiconductor chip as well as a single MOS type FET. An object of the present invention is to provide a measuring method that can easily perform thermal resistance measurement for the FET or IGT in the semiconductor device formed by combining the above.

[Main points of the invention]

In order to achieve the above-mentioned object, the present invention provides a method for measuring the thermal resistance of a MOS type FET, in which a gate and a drain of a MOS type FET for calibration are connected to a first and a second DC power source, respectively, and a source of When a resistor is connected and the channel temperature does not rise at the temperature of Tpr _1, a minute measurement current for voltage measurement is passed between the drain and source in the forward direction, and the gate-source voltage Vsgr ₁
Then, at the temperature of Tpr _2, the same current as the minute measurement current for voltage measurement is passed in the forward direction between the drain and source, and the gate-source voltage Vsgr ₂ at this time is measured, and 1 / Kg = The first procedure for obtaining the reciprocal of the constant coefficient Kg from the equation (Tpr ₂ −Tpr ₁ ) / (Vsgr ₂ −Vsgr ₁ ); and then the first and second DC power supplies for the gate and drain of the MOS FET under test. Are connected to each other and a resistor is connected to the source to have the same configuration as the first procedure, and the minute measurement current for voltage measurement is connected to
Gate-source voltage at this time by flowing in the forward direction between the sources
A second procedure for measuring Vsgm ₁ ; and subsequently, in the test MOS type FET, the first to the gate driver whose gate is connected to the source and one end to the direct current source among the connections in the second procedure. And a third procedure for switching from the second DC power supply so that a heating test current capable of increasing the channel temperature flows between the drain and the source in the forward direction to cause the MOS FET under test to consume a predetermined power Pp. And; stopping the application of the heating test current, and immediately thereafter returning to the connection configuration of the second procedure, the minute measurement current for voltage measurement is passed in the forward direction between the drain and source, and between the gate and source at this time. A fourth procedure for measuring the voltage Vsgm ₂ ; the first procedure, the second procedure and the fourth procedure
Using the numerical value obtained by the procedure, ΔTpm is calculated from the equation of ΔTpm = (1 / Kg) · (Vsgm ₂ −Vsgm ₁ ), and Rp = ΔTpm / Pp is calculated using the ΔTpm and the numerical value of the third procedure. The fifth step of calculating the thermal resistance of the MOS type FET according to the equation (1) and the above is adopted. By configuring in this way, the temperature of the forward voltage drop of the diode in the reverse direction inside the MOS type FET is Instead of using the dependency
The temperature dependence of the gate-source voltage of the FET is used to measure the channel temperature rise, and the direction of the measured current and the direction of the heating test current in the MOS FET under test that causes the channel temperature rise are To match
Therefore, it is possible to easily measure not only a single MOS type FET, but also the MOS type FET or IGT in a semiconductor device formed by combining a MOS type FET and another semiconductor element on one semiconductor chip. It is intended to obtain a thermal resistance measuring method that can be performed.

Example of Invention

FIG. 2 is a measurement circuit diagram for explaining the first procedure of the present invention. In the present invention, first, a calibration MOS type FET 4 is connected as shown in the figure, and the gate-source voltage Vsg of the FET 4 and the channel temperature are connected. Measure relationships. That is, 24 is FE in FIG.
A fixed resistor connected between the source terminal S of T4 and the ground 6, 25 is a DC power supply with a variable output voltage, the positive electrode of which is connected to the gate terminal G of the FET 4 and the negative electrode of which is connected to the ground 6. In the first procedure, the FET4 is installed in the measurement circuit as shown in FIG. 2, and the FET4 is put in a constant temperature bath at a temperature Tpr ₁ as shown in FIG. 4, and the output voltage of the power supply 25 is adjusted. By doing so, a measurement current Ig of a minute predetermined magnitude that does not increase the channel temperature in FET4 is made to flow from the drain to the source, and the gate
Measure the source-to-source voltage Vsg. Now, let this measured value be Vsgr ₁ . Next, the temperature of the constant temperature bath is changed to the temperature of Tpr ₂ and the output voltage of the power supply 25 is adjusted so that the same test current Ig as the previous time flows between the drain and source of the FET 4 in this temperature state and the voltage Vsg is taking measurement. Assuming that this measured value is Vsgr ₂ , the equation (5) holds as in the case of FIG. 4, so the reciprocal of the constant coefficient Kg is obtained from the equation (5) as in the equation (6).

FIG. 1 is a measurement circuit diagram for explaining the second and subsequent steps of the present invention. In the figure, 26 is the source terminal S of the MOS FET 7 under test.
Is a changeover switch for switching and connecting to the fixed resistor 24 or the DC power source 9, and 27 is a switch for connecting the gate terminal G of the FET 7 to the positive electrode of the DC power source 25 or to one of the output terminals of the gate driver 13. It is a switch. The changeover switches 26 and 27 are configured to interlock with each other, and the other output terminal of the gate driver 13 is connected to the source terminal S.

As described above, the present invention uses the calibration MO as the first procedure.
S-type FET4 is connected as shown in Fig. 2 and the relationship between the channel temperature of FET4 and the gate-source voltage Vsg is measured.
Immediately after this measurement, or based on this measurement result, after obtaining 1 / Kg by the equation (6), connect the test MOS type FET 7 to the measurement circuit shown in FIG.
Perform each operation of the procedure to the fifth procedure.

Operation of the second procedure Switch the terminal S of FET7 to the fixed resistor 24 by the switches 26 and 27, and
The terminal G of ET7 is connected to the DC power supply 25, and the output voltage of the power supply 25 is adjusted so that the minute measurement current Ig flows from the drain to the source as in the case of FIG. Measure the source-to-source voltage Vsg. The result of this measurement is Vsgm ₁ .

Operation of the third procedure By the switches 26 and 27, the terminal S is connected to the current source 9 for flowing the current I and the terminal G is connected to the gate driver 13
Drive 13 Then, a test current I based on the current source 9 flows from the drain to the source, and as a result, this current I
Since the electric power Pp corresponding to the product of the output voltage of the voltage source 8 is consumed by the FET 7, the channel temperature of the FET rises.

Operation of the 4th procedure Switch 26, 27 is returned to the state of the 2nd procedure, and power is supplied again so that the minute measurement current Ig flows from the drain to the source.
The output voltage of 25 is adjusted, and the voltage Vsg is measured before the channel temperature of the FET under test 7 increased by the operation of the third procedure is decreased. The result of this measurement is Vsgm ₂ .

Operation of the 5th step The increase value of the channel temperature of the FET7 by the operation of the 3rd step is Δ
When Tpm is used, the equation (7) is established. Therefore, ΔTpm obtained by the equation (7) and the power Pp consumed by the FET7 described above are satisfied.
Using and, the thermal resistance Rp of the FET 7 is calculated by the equation (8).

ΔTpm = (1 / Kg) · (Vsgm ₂ −Vsgm ₁ ) …… (7) Rp = ΔTpm / Pp …… (8) In the present invention, the thermal resistance Rp of the test MOS type FET 7 is measured as described above. To do. Therefore, when such a measuring method is applied to the thermal resistance measurement of the FET 14 in the semiconductor device 16 shown in FIG. 6, when the gate-source voltage Vsg is measured, the FET 14 is directed from the drain to the source, that is, the terminal 1
The minute measurement current Ig flowing from 7 to the terminal 20 is blocked by the pn junction (diode) in the direction of reverse bias formed between the base and collector on the bipolar transistor 15 side and does not flow, but flows only on the FET 14 side. , The voltage Vsg is accurately measured before and after the operation of the third procedure in which the FET 14 consumes power to raise the channel temperature, and thus the thermal resistance of the FET 14 is accurately measured.
Further, in the IGT shown in FIG. 7, the minute measurement current Ig is applied to the drain terminal in the above-mentioned second and fourth steps.
Since the energization operation of flowing from 21 to the source terminal 22 is easily performed, the thermal resistance measurement can be performed on the IGT of FIG. 7 according to the measuring method of the present invention.

In the above description of the embodiment, the FET to be measured is an N-channel MOS.
Although the FET is used as the FET, it is obvious that the present invention can be applied to the thermal resistance measurement of the P-channel MOS FET by reversing the polarities of the power sources of the measurement circuits described above.

〔The invention's effect〕

As described above, in the present invention, the thermal resistance measurement method of the MOS type FET is performed by connecting the first and second DC power sources to the gate and drain of the calibration type MOS FET, and connecting the source to the resistor. Connected, the channel temperature does not rise at the temperature of Tpr _1, a minute measurement current for voltage measurement is passed between the drain and source in the forward direction, the gate-source voltage Vsgr ₁ at this time is measured, and then the temperature of Tpr ₂ is measured. At the same time, the same current as the minute measurement current for voltage measurement is passed in the forward direction between the drain and source, and the gate-source voltage Vsgr ₂ at this time is measured, and 1 / Kg = (Tpr ₂ −Tpr ₁ ) / (Vsgr The first procedure for obtaining the reciprocal of the constant coefficient Kg from the formula of ( _2- Vsgr ₁ ); and then, in the test MOS FET, connect the first and second DC power supplies to the gate and drain, respectively, and connect the resistor to the source. The same configuration as in the first procedure is established by connecting, and The drain and the
Gate-source voltage at this time by flowing in the forward direction between the sources
A second procedure for measuring Vsgm ₁ ; and subsequently, in the test MOS type FET, the first to the gate driver whose gate is connected to the source and one end to the direct current source among the connections in the second procedure. And a third procedure for switching from the second DC power supply so that a heating test current capable of increasing the channel temperature flows between the drain and the source in the forward direction to cause the MOS FET under test to consume a predetermined power Pp. And; stopping the application of the heating test current, and immediately thereafter returning to the connection configuration of the second procedure, the minute measurement current for voltage measurement is passed in the forward direction between the drain and source, and between the gate and source at this time. A fourth procedure for measuring the voltage Vsgm ₂ ; the first procedure, the second procedure and the fourth procedure
Using the numerical value obtained by the procedure, ΔTpm is calculated from the equation of ΔTpm = (1 / Kg) · (Vsgm ₂ −Vsgm ₁ ), and Rp = ΔTpm / Pp is calculated using the ΔTpm and the numerical value of the third procedure. And the fifth step of calculating the thermal resistance of the MOS type FET according to the equation (4), the temperature dependence of the forward voltage drop of the internal reverse diode of the MOS type FET is not utilized but the FET is used. Channel temperature rise is measured by utilizing the temperature dependence of the gate-source voltage of the
As a result of matching the conduction direction of the heating test current in the MOS type FET, a semiconductor device formed by combining the MOS type FET and another semiconductor element on one semiconductor chip as well as a single MOS type FET. MOS type FET or IGT in
Also, there is an effect that a thermal resistance measuring method that can easily perform the measurement can be obtained.

[Brief description of drawings]

FIG. 1 is a measurement circuit diagram for explaining a procedure after the second procedure of the present invention, and FIG. 2 is a measurement circuit diagram for explaining a first procedure of the present invention.
The figure is a cross-sectional view for explaining the configuration of an N-channel MOS type FET, and FIGS. 4 and 5 are measurement circuit diagrams for explaining the procedure after the first procedure and the second procedure in the conventional thermal resistance measuring method, FIG. 6 and FIG. FIG. 7 is a circuit configuration diagram and a configuration explanatory sectional view of a different semiconductor device formed by combining a MOS type FET and another semiconductor element. 4 …… Calibration MOS FET, 7 …… Test MOS FET, Vsg ……
Gate-source voltage, Ig ... Minute measurement current, I ... Test current.

Claims (1)

[Claims] _1. A voltage for which a channel temperature does not rise at a temperature of Tpr _{1 in which} a gate and a drain are connected to first and second DC power supplies, a source is connected to a resistor, and a calibration MOS type FET is connected to a source. A minute measurement current for measurement is passed between the drain and source in the forward direction to measure the gate-source voltage Vsgr ₁ at this time, and then at the temperature of Tpr ₂ , the same current as the minute measurement current for voltage measurement is drained. Flow between the sources in the forward direction, measure the gate-source voltage Vsgr ₂ at this time, and find the reciprocal of the constant coefficient Kg from the formula 1 / Kg = (Tpr ₂ −Tpr ₁ ) / (Vsgr ₂ −Vsgr ₁ ). The first procedure, then the first and second gate and drain in the sample MOS FET
DC power supplies are connected respectively, and a resistor is connected to the source to have the same configuration as the first procedure, and the minute measurement current for voltage measurement is passed in the forward direction between the drain and the source, and the gate-source voltage at this time The second procedure for measuring Vsgm ₁ , and then the connection to the gate driver whose gate is connected to the source at one end and the source to the direct current source among the connections in the second procedure in the test MOS FET Switching from the second DC power supply so that the heating test current that may increase the channel temperature flows between the drain and the source in the forward direction,
A third procedure for consuming a predetermined power Pp in the MOS FET under test, stopping energization of the heating test current, and immediately thereafter, returning to the connection configuration of the second procedure to set the minute measurement current for voltage measurement. Flow in the forward direction between the drain and source
The fourth procedure for measuring the source-to-source voltage Vsgm ₂ , using the numerical values obtained by the first procedure, the second procedure, and the fourth procedure, from the formula of ΔTpm = (1 / Kg) · (Vsgm ₂ −Vsgm ₁ ). , And a ΔTpm is calculated, and the fifth step of calculating the thermal resistance of the MOS type FET from the equation of Rp = ΔTpm / Pp by using the ΔTpm and the numerical value of the third step, Method for measuring thermal resistance.