JPH0675097B2 - Address sequencer - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an address sequencer suitable for analyzing defects in a pattern generator used in a semiconductor test apparatus or the like.

[Background of the Invention]

 FIG. 1 is a block diagram of a general pattern generator.

In FIG. 1, a pattern memory 30 stores a pattern required for a test and reads a pattern 40 at an address 20 given from an address sequencer 10. Pattern 40
Consists of an input pattern given to the IC under test 50 and an expected pattern which is a response output from a normal IC. The expected pattern is given to the determiner 70. At the same time, the decision output 70 is given the response output 60 from the IC under test 50. The determiner 70 is
A determination is made by comparing these, and if there is a mismatch, it is determined to be defective, and the expected pattern and input pattern at that time are stored for defect analysis.

Here, the object of the present invention is the address sequencer 10 in FIG.

FIG. 2 is a block diagram of an example of a conventional address sequencer.

This address sequencer operates by the clock CK generated by the clock generator 11. The program counter 12 generates an address 20 for the control memory 13.
The control memory 13 reads the control command corresponding to the address 20. The control instruction is composed of an operation code OPC and an operand OPD, and the read operation code OPC is given to the decoder 14. The decoder 14 decodes this and refers to the state signal STS of the counter 15 to give a corresponding control signal CNT to the program counter 12, and also gives the counter 15 a control signal CNT. These control signals are continuously given until the next clock is input, and at the time when the next clock is input, the program counter 12 and the counting section 15 are updated to new states in accordance with the instruction of the control signal.

Here, the address sequencer can repeatedly generate the same address over a plurality of cycles by controlling the counting unit 15 with a repeat instruction or the like. This has the advantage that the capacity of the pattern memory 30 (FIG. 1) can be reduced, but on the other hand, the IC50 under test
When a defect is found in (Fig. 1), there is a drawback that makes the analysis more difficult.

FIG. 3 is an explanatory diagram of defective signal detection during the generation of a repeated pattern. At this time, the defective response output pattern from the IC under test and the expected pattern are stored in the determination unit.However, during the repeated pattern generation, the generation of the repeated pattern is started because the expected pattern is the same in every cycle. After that, it is impossible to distinguish in what cycle the defect occurred.

Therefore, as shown in the relationship diagram between the number of repeated patterns and the number of steps in FIG. 4, it is possible to count the number of steps from the start of the test and store the number of steps together with the expected pattern when a defect occurs.

For example, in FIG. 4, the step number ^# 10 is stored together with the pattern corresponding to the address ^# 3 when a defect occurs.

However, the IC test equipment has a function to wait until the IC under test reaches a specific state, and the number of cycles required to execute this function is not uniquely determined, and it varies depending on the state of the IC under test. There's a problem.

FIG. 5 shows an execution example of this function, and is a relationship diagram between an instruction whose execution cycle number is indefinite and the number of steps. Fifth
In the figure, the instruction corresponding to the address is an instruction that waits until the IC under test enters a specific state. In this example, #
In (N + 2) step, it is detected that the IC under test is in a specific state, and in ^# (N + 3) step, the address is detected.
^Going to ^# 3.

The problem here is that the number of steps until a specific state is detected is not uniquely determined from time to time, and therefore the value of the step counter after execution of such an instruction has no meaning. It will be something that does not exist.

[Object of the Invention]

It is an object of the present invention to solve such a problem and to make the number of steps meaningful even after the execution of an instruction in which the number of steps required for execution is indefinite, and thus to identify the same pattern that is repeatedly generated. The purpose is to provide the address sequencer.

[Outline of Invention]

The address sequencer according to the present invention is an address sequencer configured to generate a read address of a stored control instruction, read the read control instruction, and decode the read control address to generate a next read address. The counting means for counting the number of steps and the detecting means for detecting that the number of steps required for executing the read control command are indefinite are provided, and the counting operation of the counting means is prohibited by the detection output. By uniquely associating the cumulative step count value with the output address, it is possible to identify each output count of the same address output a plurality of times.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 is a block diagram of an embodiment of the address sequencer according to the present invention, and FIG. 7 is a circuit diagram of an embodiment of the essential parts thereof.
FIG. 8 is a time chart for those operations.

Here, 11 is a clock generator, 12 is a program counter, 13 is a control memory, 14 is a decoder, 15 is a counting section, 16 is a detector, 17 is a step counter, and 11 to 15 are shown in FIG. It is equivalent to that of the same sign.

This address sequencer has, in addition to the conventional address sequencer shown in FIG. 2, a step counter 17 for counting the number of steps, and an opcode OPC for an instruction with an indefinite number of execution cycles, read from the control memory 13. A detector 16 for detection is provided, and the counting of the step counter 17 is prohibited by the counting prohibition signal NC which is the output of the detector 16.

FIG. 7 shows the detector 16 and the step counter in FIG.
17 shows a concrete configuration example of 17.

As a simple example, when the instruction with the operation code "10101" has an indefinite number of execution cycles, the signal obtained by decoding this operation code is used as the count inhibit signal NC and the step counter 17
The clock is prohibited by applying a gate to the clock input to.

FIG. 8 shows an example of these operations. In FIG. 8, the operation code "1010" is specified by specifying the address ^# 4.
If "1" is read out, the output of the detector 16 falls to LOW (low level), which becomes the counting prohibition signal NC. The clock of the step counter 17 is gated by the count inhibit signal NC, and its output is inhibited while the address ^# 4 is being executed. As a result, during the execution of address ^{# 4,} not performed the update of the step counter 17, even long address ^# number of execution cycles ^4, short Kakutomo,
When the process proceeds to the next address ^# 5, it means step ^# 9.

Therefore, even after executing an instruction with an indefinite number of steps,
Since the address is uniquely determined with respect to the step value, it is possible to identify the address that is repeatedly generated (excluding the address where the number of execution steps is not fixed) for each cycle.

FIG. 9 is a block diagram of an embodiment of a test apparatus using this address sequence. When a defect is found in the response output 60 from the IC under test 50, the decision unit 70 causes the pattern memory
Address sequencer 10 in addition to expected pattern 40 from 30
It is configured to also store the number of steps from 80 to.

With this configuration, when a test pattern is repeatedly given to the IC under test and a test is performed, even when a defect is detected, it is possible to identify the number of times the defect occurs in the repeated pattern. Therefore, it is possible to easily analyze defects.

〔The invention's effect〕

As described in detail above, according to the present invention, even in a test pattern that is repeatedly generated, it is possible to identify each cycle, and the number of times the detected defective IC is detected is the same pattern. Since it can be pointed out, it is possible to obtain remarkable effects in facilitating the failure analysis of IC tests, improving efficiency, and improving accuracy.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a general pattern generator, FIG. 2 is a configuration diagram of an example of a conventional address sequencer, and FIG. 3 is an explanatory diagram of defective signal detection during repetitive pattern generation,
FIG. 4 is a diagram showing the relationship between the number of repeating patterns and steps, FIG. 5 is a diagram showing the relationship between instructions with an indefinite number of execution cycles and the number of steps, and FIG. 6 is a diagram showing an embodiment of the address sequencer according to the present invention. Configuration diagram, FIG. 7 is a circuit diagram of an embodiment of a main part thereof, FIG. 8 is an operation time chart thereof, and FIG. 9 is a configuration diagram of an embodiment of a test apparatus using the address sequencer. is there. 10 …… address sequencer, 11 …… clock generator, 12 …… program counter, 13 …… control memory, 14 …… decoder, 15 …… counter, 16 …… detector, 17 …… step counter.

Claims (1)

[Claims] 1. An address sequencer which generates a read address of a stored control instruction, reads the read control address, and decodes the read address to generate the next read address. Counting means for counting, detection means for detecting that the number of steps required to execute the read control instruction is indefinite, and a detection signal from the detection means is input, and counting by the detection signal is performed in the counting means. An address sequencer that is provided with means for prohibiting operation and that can identify output steps of the same address that are output over a plurality of steps.