JPH067583B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH067583B2 JPH067583B2 JP57226171A JP22617182A JPH067583B2 JP H067583 B2 JPH067583 B2 JP H067583B2 JP 57226171 A JP57226171 A JP 57226171A JP 22617182 A JP22617182 A JP 22617182A JP H067583 B2 JPH067583 B2 JP H067583B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- fuse
- external lead
- pad
- psg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
- H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
- H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
- H10W20/494—Fuses, i.e. interconnections changeable from conductive to non-conductive changeable by the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 本発明は冗長回路を備えた半導体装置の製造法に関し、
特に冗長用ヒューズと外部導出用パッドの信頼性の向上
を図った半導体装置の製法に関するものである。The present invention relates to a method of manufacturing a semiconductor device having a redundant circuit,
In particular, the present invention relates to a method of manufacturing a semiconductor device in which the reliability of the redundant fuse and the external lead-out pad is improved.
一般にメモリ用の半導体装置では歩留の向上を図るため
に、第１図に示すように、メモリセルアレイ２５と同様
のメモリセルを配置した所謂冗長回路３を設けている。
そして、入出力回路２６とデコーダ２７との間に形成し
たヒューズ５を適宜切断又はそのまま残すことにより冗
長回路を接続し欠陥ビットを救済させるようになってい
る。通常では、第１図に示す半導体装置（素子チップ）
１のように外部導出用パッド２に夫々触針４を接触させ
た上で、選択された触針に高電圧を印加することによ
り、装置１上に形成したヒューズ５の一部を過電流によ
って溶融して切断を行なうようになっている。In general, a semiconductor device for a memory is provided with a so-called redundant circuit 3 in which memory cells similar to the memory cell array 25 are arranged as shown in FIG. 1 in order to improve the yield.
Then, the fuse 5 formed between the input / output circuit 26 and the decoder 27 is appropriately cut or left as it is to connect the redundant circuit and relieve the defective bit. Usually, the semiconductor device (element chip) shown in FIG.
As shown in FIG. 1, the stylus 4 is brought into contact with each of the external lead-out pads 2, and then a high voltage is applied to the selected stylus, whereby a part of the fuse 5 formed on the device 1 is exposed to an overcurrent. It is designed to be melted and cut.
ところで、この種の半導体装置ではポリシリコン等から
形成したヒューズの上側に保護用の酸化膜が存在してい
ると、ヒューズ切断の際に発生するガスを排出すること
ができず、また酸化膜によって切断作用が抑制される等
の不具合が生じる。このため、ヒューズの少なくとも切
断箇所を露呈させておく必要がある。しかしながら一方
では、切断したヒューズをそのまま露呈をさせておく
と、表面で化学変化等が生じて再導通する現象が生じる
ことがあり信頼性の点で好ましくない。By the way, in this type of semiconductor device, if a protective oxide film is present on the upper side of a fuse formed of polysilicon or the like, the gas generated at the time of cutting the fuse cannot be discharged, and the oxide film prevents the gas from being generated. Problems such as suppression of the cutting action occur. Therefore, it is necessary to expose at least the cut portion of the fuse. On the other hand, however, exposing the blown fuse as it is is not preferable from the viewpoint of reliability since a chemical change may occur on the surface of the fuse to cause re-conduction.
このため、切断後のヒューズにはパッシベーションを施
すことが要求されており、従来は下地層と同一のＰＳＧ
層を半導体装置表面に形成している。第２図に示すよう
にパッシベーション７を施したときには外部導出用バッ
ド２はこれを開口してパッド表面を露呈しなければなら
ず、外部導出用パッド上のパッシベーションを第２図の
ようにエッチング除去している。ところが、このとき、
外部導出用パッド２に、前記した触針４との接触や過電
流の通流等が原因とされる傷６が生じていると、エッチ
ング液はこの傷６を通してパッド２の裏側にまで到達
し、図示のようにパッシベーション７のみならず下地層
としてのＰＳＧ層８をもエッチングしてしまう。この結
果、パッド２への外部接続線の接続が不安定ないし不能
となり、またパッド２と他の導電層（例えば半導体基
板）とのリークやショートが生じ、その信頼性の低下を
生じることになる。図中、９はシリコン基板、１０はＳ
ｉＯ2膜である。For this reason, it is required to apply passivation to the fuse after cutting, and conventionally, the same PSG as that of the underlying layer is used.
A layer is formed on the surface of the semiconductor device. When the passivation 7 is applied as shown in FIG. 2, the pad 2 for external lead-out must be opened to expose the pad surface, and the passivation on the pad for external lead-out is removed by etching as shown in FIG. is doing. However, at this time,
When the external lead-out pad 2 has a scratch 6 caused by the contact with the stylus 4 or the flow of an overcurrent, the etching solution reaches the back side of the pad 2 through the scratch 6. As shown, not only the passivation 7 but also the PSG layer 8 as an underlayer is etched. As a result, the connection of the external connection line to the pad 2 becomes unstable or impossible, and a leak or short circuit between the pad 2 and another conductive layer (for example, a semiconductor substrate) occurs, which lowers the reliability thereof. . In the figure, 9 is a silicon substrate, 10 is S
This is an iO 2 film.
したがって、本発明の目的はヒューズのパッシベーショ
ンを行なってヒューズの信頼性を確保する一方で、外部
導出用パッドにおけるパッシベーションのエッチングを
好適に行なってこのパッドの信頼性の向上をも図ること
ができる半導体装置の製法を提供することにある。Therefore, the object of the present invention is to perform the passivation of the fuse to ensure the reliability of the fuse, while at the same time, to improve the reliability of the pad by suitably performing the passivation etching on the pad for external lead-out. It is to provide a manufacturing method of the device.
この目的を達成するために本発明の一実施例はヒューズ
のパッシベーションの材質をプラズマナイトライドと
し、下地層の材質とでエッチングに選択性のある素材を
使用し、パッシベーションのエッチングを行なっても下
地層がエッチングされないように構成したものである。In order to achieve this object, an embodiment of the present invention uses plasma nitride as the material of the passivation of the fuse, uses a material that has selectivity for etching with the material of the underlayer, and even if the passivation is etched, It is configured so that the formation is not etched.
以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be described with reference to the illustrated embodiments.
第３図は本発明をダイナミックＲＡＭに適用した例であ
る。シリコン半導体基板１１上にはフィールド絶縁膜１
２にて素子形成領域を画成し、この領域にはゲート絶縁
膜１３を形成している。このゲート絶縁膜１３上にはポ
リシリコン膜にてゲート電極１４を形成しかつこれにセ
ルフアラインしてシリコン基板１１にソース領域１５と
ドレイン領域１６を夫々形成して絶縁ゲート型電界効果
トランジスタＱを構成している。また、ドレイン領域１
６より右側のゲート絶縁膜１３上にはポリシリコン膜１
７を形成し、前記シリコン基板１１とでキャパシタＣを
構成している。これにより、前記トランジスタＱとキャ
パシタＣとで第４図に示すダイミックメモリ回路を構成
する。FIG. 3 shows an example in which the present invention is applied to a dynamic RAM. The field insulating film 1 is formed on the silicon semiconductor substrate 11.
2, an element forming region is defined, and a gate insulating film 13 is formed in this region. A gate electrode 14 made of a polysilicon film is formed on the gate insulating film 13, and a source region 15 and a drain region 16 are formed on the silicon substrate 11 by self-aligning the gate electrode 14 to form an insulated gate field effect transistor Q. I am configuring. In addition, the drain region 1
A polysilicon film 1 is formed on the gate insulating film 13 on the right side of 6
7 is formed, and a capacitor C is formed with the silicon substrate 11. As a result, the transistor Q and the capacitor C form the dimic memory circuit shown in FIG.
一方、ゲート電極１４あるいはポリシリコン膜１７と同
時に形成されたポリシリコンのヒューズ２０がフィール
ド絶縁膜１２上に形成されている。また、前記ゲート電
極１４やポリシリコン膜１７上には層間絶縁層としてＳ
ｉＯ2膜18およびPSG膜19を形成する。そして、このPSG膜1
9上にはこれを下地層とするAl配線層を完成する。このAl
配線層はその一部21は前記ソ-ス領域15に直接接続されるデ
-タ線Dとして構成され、また他の一部は外部導出用パッド22
として構成される。そして、これらAl配線層21,22やヒュ-ズ2
0上には保護膜としてのSiO2膜２３を形成しているが、
前記外部導出用パッド２２部位、ヒューズ２０の切断部
位においては開口してこれらを露呈させている。On the other hand, a polysilicon fuse 20 formed at the same time as the gate electrode 14 or the polysilicon film 17 is formed on the field insulating film 12. In addition, as an interlayer insulating layer, S is formed on the gate electrode 14 and the polysilicon film 17.
An iO 2 film 18 and a PSG film 19 are formed. And this PSG film 1
An Al wiring layer using this as a base layer is completed on 9. This Al
A part 21 of the wiring layer is directly connected to the source region 15.
-Configured as wire D, and part of the other is external lead-out pad 22
Configured as. And these Al wiring layers 21 and 22 and fuse 2
A SiO 2 film 23 as a protective film is formed on 0,
The external lead-out pad 22 portion and the fuse 20 cut portion are opened to expose them.
したがってこの状態で第一次の完成品として所定の検査
を行なう。そして、冗長回路を必要とするためにヒュー
ズ２０を切断する場合には外部導出用パッド２２を触針
（第１図参照）を接触させ、選択的にこれに高電流を印
加することによりヒューズ２０の所要箇所を切断する。Therefore, in this state, a predetermined inspection is performed as the first completed product. When the fuse 20 is blown because a redundant circuit is required, the external lead-out pad 22 is brought into contact with a stylus (see FIG. 1) and a high current is selectively applied to the external lead-out pad 22 to fuse the fuse 20. Cut the required part of.
このようにしてヒューズ２０が切断された半導体装置を
最終の完成品とするために、第５図に示すように、全面
にパッシベーション２４を施し、その上で外部導出用パ
ッド２２部位のみにエッチングを施してここを開口す
る。この場合、パッシベーション２４の材質には前記下
地層としてのＰＳＧ層１９と異なる材質でしかもエッチ
ングに選択性のあるものを使用する。本例ではパッシベ
ーション２４にプラズマＣＶＤ法によって形成した窒化
シリコン膜（以下Ｐ−ＳｉＮという）を使用し、エッチ
ングはＣＦ4ガスを用いたプラズマエッチングを行な
う。In order to make the semiconductor device in which the fuse 20 is cut in this way a final finished product, as shown in FIG. 5, passivation 24 is applied to the entire surface, and only the external lead-out pad 22 portion is etched. Apply and open here. In this case, the passivation 24 is made of a material different from that of the PSG layer 19 as the underlayer and having etching selectivity. In this example, a silicon nitride film (hereinafter referred to as P-SiN) formed by a plasma CVD method is used for the passivation 24, and etching is performed by plasma etching using CF 4 gas.
したがって以上のようにして構成した半導体装置によれ
ば、ヒューズ２０はパッシベーション２４により保護さ
れるので、切断箇所が露呈されることはなく、したがっ
て切断箇所が再導通することもなく信頼性の高いヒュー
ズを得ることができる。一方、外部導出用パッド２２に
おけるパッシベーション２４のエッチングに際しては、
パッシベーション２４とＰＳＧ層１９とでエッチングに
選択性があるため、仮にパッド２２に傷が生じていても
ＰＳＧ層がエッチングされることはない。これにより、
パッド２２におけるＰＳＧ層１９を安定に保持し、外部
接続線等の接続を安定化して信頼性の向上を達成するこ
とができる。さらに、プラズマＣＶＤ法によって形成さ
れる窒化シリコン膜は耐湿性にすぐれており、本願発明
で対象としている半導体装置において有益である。Therefore, according to the semiconductor device configured as described above, since the fuse 20 is protected by the passivation 24, the cut portion is not exposed, and therefore, the cut portion is not re-conducted and the fuse is highly reliable. Can be obtained. On the other hand, when etching the passivation 24 in the pad 22 for external lead-out,
Since the passivation 24 and the PSG layer 19 have etching selectivity, the PSG layer is not etched even if the pad 22 is scratched. This allows
It is possible to stably hold the PSG layer 19 in the pad 22 and stabilize the connection of the external connection line or the like to achieve the improvement in reliability. Further, the silicon nitride film formed by the plasma CVD method has excellent moisture resistance and is useful in the semiconductor device targeted by the present invention.
以上のように本発明の半導体装置はヒューズや外部導出
用パッドの下地層と、パッシベーションとでエッチング
に選択性のある材質のものを使用しているので、ヒュー
ズの切断を安定に保持する一方でパッドにおける外部接
続線の接続を安定なものにでき、これによりヒューズが
およびパッドの信頼性を向上させることができるという
効果を奏する。As described above, since the semiconductor device of the present invention uses a material having a selective etching property for the underlying layer of the fuse or the pad for external lead-out and the passivation, it is possible to stably hold the blow of the fuse. There is an effect that the connection of the external connection line in the pad can be made stable, and thereby the reliability of the fuse and the pad can be improved.
すなわち、本発明においては、ＳｉＯ2膜及びＰＳＧ膜
を開口させて外部導出用パッド及びヒューズを露呈させ
た状態で所定の検査を行った後、その開口状態で触針を
前記外部導出用パッドに接触させて前記ヒューズの所定
箇所を切断し、その後に前記ＰＳＧ膜とは異なる材質で
エッチングに選択性のあるプラズマＣＶＤ法により形成
される窒化シリコン膜を全面に形成し、さらにその後で
前記窒化シリコン膜を選択的に除去して前記外部導出用
パッド上を開口させるので、ヒューズはパッシベーショ
ンである窒化シリコン膜で物理的に隔離されて保護され
ることになり、再導通することを確実に阻止することが
できる。That is, in the present invention, after performing a predetermined inspection in a state where the SiO 2 film and the PSG film are opened and the external lead-out pad and the fuse are exposed, the stylus is attached to the external lead-out pad in the opened state. The fuse is contacted to cut a predetermined portion of the fuse, and thereafter, a silicon nitride film made of a material different from that of the PSG film and formed by a plasma CVD method having etching selectivity is formed on the entire surface, and then the silicon nitride film is formed. Since the film is selectively removed to open on the pad for external lead-out, the fuse is physically isolated and protected by the silicon nitride film which is the passivation, and surely prevents re-conduction. be able to.
しかも、本発明においては、パッシベーションがプラズ
マＣＶＤ法により形成される窒化シリコン膜であり、か
つ窒化シリコン膜がＰＳＧ膜とは異なる材質でエッチン
グに選択性のあるものであるので、プラズマＣＶＤ法に
よる窒化シリコン膜は耐湿性にすぐれているという利点
が得られる上に、該窒化シリコン膜がＰＳＧ膜とは異な
る材質でエッチングに選択性があることにより、仮に外
部導出用パッドに傷が付いていたとしてもＰＳＧ膜がエ
ッチングされることはなく、外部導出用パッドにおける
ＰＳＧ膜がエッチングされることを阻止できる。その結
果、本発明によれば、窒化シリコン膜による耐湿性の向
上と、外部導出用パッドにおける外部接続線の安定化が
図られ、ヒューズと外部導出用パッドの信頼性を向上さ
せることができる。Moreover, in the present invention, since the passivation is the silicon nitride film formed by the plasma CVD method, and the silicon nitride film is made of a material different from the PSG film and has selectivity for etching, the nitridation by the plasma CVD method is performed. In addition to the advantage that the silicon film has excellent moisture resistance, the silicon nitride film is different in material from the PSG film and has etching selectivity, so that the external lead-out pad may be scratched. However, the PSG film is not etched, and the PSG film in the external lead-out pad can be prevented from being etched. As a result, according to the present invention, it is possible to improve the moisture resistance of the silicon nitride film and stabilize the external connection line in the external lead-out pad, thereby improving the reliability of the fuse and the external lead-out pad.
第１図は冗長回路を有する半導体装置を説明する平面
図、 第２図は従来の不具合を説明する断面図、 第３図は本発明装置の第１次完成品の断面図、 第４図は回路図、 第５図は最終完成品の要部の断面図である。 １１…半導体基板、１２…フィールド絶縁膜、１３…ゲ
ート絶縁膜、１４…ゲート電極、１５…ソース領域、１
６…ドレイン領域、１７…ポリシリコン膜、１９…ＰＳ
Ｇ層（下地層）、２０…ヒューズ、２２…外部導出用パ
ッド、２３…ＳｉＯ2膜、２４…パッシベーション、Ｑ
…トランジスタ（ＭＯＳＦＥＴ）、Ｃ…キャパシタ。FIG. 1 is a plan view illustrating a semiconductor device having a redundant circuit, FIG. 2 is a cross-sectional view illustrating a conventional defect, FIG. 3 is a cross-sectional view of a first completed product of the device of the present invention, and FIG. A circuit diagram and FIG. 5 are cross-sectional views of the essential parts of the final finished product. 11 ... Semiconductor substrate, 12 ... Field insulating film, 13 ... Gate insulating film, 14 ... Gate electrode, 15 ... Source region, 1
6 ... Drain region, 17 ... Polysilicon film, 19 ... PS
G layer (base layer), 20 ... Fuse, 22 ... External lead-out pad, 23 ... SiO 2 film, 24 ... Passivation, Q
... transistor (MOSFET), C ... capacitor.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/66 Ｗ 7352−4Ｍ 21/82 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 21/66 W 7352-4M 21/82
Claims (1)
を備える半導体装置の製法において、フィールド絶縁膜
上に形成されたヒューズ上に層間絶縁膜としてのＰＳＧ
膜を形成する工程、前記ＰＳＧ膜上にＡ１層からなる外
部導出用パッドを形成する工程、前記外部導出用パッド
及びＰＳＧ膜上に保護膜としてのＳｉＯ２膜を形成する
工程、前記外部導出用パッドおよびヒューズを露呈させ
るために前記ＳｉＯ２膜及びＰＳＧ膜を開口する工程、
前記開口状態で所定の検査を行う工程、前記開口状態で
触針を前記外部導出用パッドに接触させて前記ヒューズ
の所定箇所を切断する工程、前記ヒューズ切断工程の
後、前記ＰＳＧ膜とは異なる材質でエッチングに選択性
のあるプラズマＣＶＤ法により形成される窒化シリコン
膜を全面に形成する工程、この窒化シリコン膜形成工程
の後で前記窒化シリコン膜を選択的に除去して前記外部
導出用パッド上を開口する工程、を有する半導体装置の
製法。1. A method of manufacturing a semiconductor device including a redundant circuit and a fuse connected to the redundant circuit, wherein PSG as an interlayer insulating film is formed on a fuse formed on a field insulating film.
A step of forming a film, a step of forming an external lead pad made of an A1 layer on the PSG film, a step of forming a SiO 2 film as a protective film on the external lead pad and the PSG film, the external lead Opening the SiO 2 film and the PSG film to expose pads and fuses;
Different from the PSG film after the step of performing a predetermined inspection in the open state, the step of contacting the stylus with the external lead-out pad in the open state to cut a predetermined portion of the fuse, and the step of cutting the fuse The step of forming a silicon nitride film formed by a plasma CVD method, which is selective in etching by a material, on the entire surface, and after the step of forming the silicon nitride film, the silicon nitride film is selectively removed to form the pad for external lead-out. A method of manufacturing a semiconductor device, the method including the step of opening the top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226171A JPH067583B2 (en) | 1982-12-24 | 1982-12-24 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226171A JPH067583B2 (en) | 1982-12-24 | 1982-12-24 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59117157A JPS59117157A (en) | 1984-07-06 |
| JPH067583B2 true JPH067583B2 (en) | 1994-01-26 |
Family
ID=16840985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226171A Expired - Lifetime JPH067583B2 (en) | 1982-12-24 | 1982-12-24 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067583B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0738413B2 (en) * | 1984-10-31 | 1995-04-26 | 富士通株式会社 | Semiconductor device |
| US5241212A (en) * | 1990-05-01 | 1993-08-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a redundant circuit portion and a manufacturing method of the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513135A (en) * | 1978-07-17 | 1980-01-30 | Hitachi Ltd | Measuring device for nitrogen content of waste water |
| JPS5847596Y2 (en) * | 1979-09-05 | 1983-10-29 | 富士通株式会社 | semiconductor equipment |
| JPS56146268A (en) * | 1980-04-15 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor memory unit |
-
1982
- 1982-12-24 JP JP57226171A patent/JPH067583B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59117157A (en) | 1984-07-06 |
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