JPH067586B2 - Logic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor bulk including a plurality of drive transistors and load transistors each having a predetermined gate width and formed in an array. Alternatively, a predetermined number of driving transistors connected in parallel and a plurality of load transistors connected in series are provided, and the number of gate electrodes of the load transistors is equal to the number of driving transistors connected in series. The load impedance can be changed by connecting to the output terminal and the gate electrode of the remaining load transistor to the power supply line of a predetermined potential, enhancing the logic function per gate and improving the circuit operation performance. Is to improve.

[Industrial application field]

The present invention relates to a logic circuit device, and more specifically, to a predetermined number of a plurality of drive field effect transistors (drive FETs) and load field effect transistors (load FETs) formed in an array on a semiconductor bulk. Drive FET and load FET
The present invention relates to an inverting logic type logic circuit device composed of and.

[Conventional technology]

FIG. 8 occupies a configuration example of the above-mentioned inverting logic circuit. The example of FIG. 8 shows a case of a DCFL circuit (Diect Coupled FET Logic circuit) used as a basic gate of an IC. The DCFL circuit is basically composed of an enhanced mode (E) mode transistor as a drive FET 81D (or 82D) and a depletion (D) mode transistor as a load FET 81L (or 82L). This is the inverter gate INV ₁ (or INV ₂ ), and in an actual usage pattern, it has a circuit configuration in which inverter gates are connected in multiple stages as shown in FIG.

FIG. 9 shows an example of transfer characteristics of the DCFL circuit shown in FIG. In the figure, the curve indicated by the solid line is the inverter gate INV ₁
Input / output transfer characteristics of the inverter gate INV ₂ , the curves shown by broken lines are the input / output transfer characteristics of
ΔV is a logic voltage amplitude, Vtho is a logic threshold voltage, NM ₀ is a noise margin at a low output level, and NM ₁ is a noise margin at a high output level.

Input / output transfer characteristics are drive FETs that form an inverter gate
And the saturation drain current Id of the load FET. This saturation drain current Id is expressed as Id = β (Vgs-Vth) ² , where Vgs is the gate-source voltage and Vth is
FET threshold voltage, β represents a proportional constant. And
It is known that the proportionality constant β is proportional to the ratio of the gate width W and the gate length L of the FET (hereinafter referred to as W / L ratio). Therefore, when the values of Vgs and Vth are kept constant, the saturation drain current Id, and hence the input / output transfer characteristics of each inverter gate, are determined depending on the W / L ratio of the drive FET and the load FET. .

If the W / L ratio is not properly selected, the value of the logic threshold voltage of the inverter gate is set to the operation stable point P.
From the middle point of Q and Q, and the influence thereof causes the fluctuation of the logic threshold voltage of the inverter gate of the next stage, which causes a shortage of the noise margin on the high level side or the low level side, and the entire circuit. As a result, there is an inconvenience that stable operation cannot be obtained. Therefore, when designing a circuit, a straight line with the same logical threshold voltage value of each inverter gate (a straight line with a slope of 1 in FIG. 9)
Set the input / output transfer characteristics, that is, W / L
Appropriate selection of ratio is made.

In other words, the ratio of the gate width Wgl of the load FET to the gate length Lgl (Wgl / Lgl) of the inverter gate and the ratio of the gate width Wgd of the drive FET to the gate length Lgd (Wgd / Lgd) (hereinafter referred to as impedance ratio The stable operation of the circuit can be obtained by keeping (referred to) constant. Drive FET and load F
In the case of an inverter gate using a GaAs (gallium / arsenic) MESFET (metal / semiconductor FET) as the ET, it is common to keep the gate length Lg constant from the viewpoint of increasing the operating speed. Therefore, the impedance ratio is negative FE
It is defined by the ratio of T and the gate width of each drive FET (Wgl / Wgd). In any case, in order to equalize the noise margins on the high level side and the low level side of the output and stabilize the circuit operation, it is necessary to set the impedance ratio to a predetermined value.

The DCFL circuit shown in FIG. 8 is a basic circuit of an inverting logic type circuit, but in the case of actually configuring the circuit on a semiconductor bulk such as a gate array, it is a negative circuit composed of 3 to 4 FETs. In many cases, AND gates (NAND gates) or NOR gates (NOR gates) are connected in multiple stages as a unit basic cell (BC).

[Problems to be solved by the invention]

For example, suppose that a load FET (Lgl = 1 μm; Wgl = 6 μm) and a drive FET (Lgl = 1 μm; Wgd = 10 μm) are semiconductor bulks formed in an array, and two drive FETs and one load are used. It is assumed that the NOR gate made of FET is integrated on the semiconductor bulk as 1B.C. In this case, two drives
Although the FETs are connected in parallel, one of them is in the cut-off state in operation, so the W / L ratio on the drive FET side is the same as the W / L ratio of one drive FET. Is 10 (10
μm / 1 μm). On the other hand, the W / L ratio on the load FET side is 6 (6 μm / 1 μm). Therefore, the impedance ratio is 0.6.

On the other hand, if a NAND gate is composed of the same two drive FETs and one load FET, the two drive FETs connected in series are both in the ON state in the inverting logic operation, so the drive FET side , The gate length is equivalently doubled, so the W / L ratio on the drive FET side is 5 (10 μm /
2 μm). On the other hand, the W / L ratio on the load FET side is 6 (6 μm / 1 μm). Therefore, the impedance ratio becomes 1.2, and the NOR gate impedance ratio 0.
It will be different from 6.

This is a multi-stage configuration in which two types of inverting logic type gates having different impedance ratios, that is, a NAND gate and a NOR gate, are mixed on a semiconductor bulk prepared in advance with a predetermined gate width for a drive FET and a load FET. When connected, the logic threshold voltage at each gate fluctuates and a sufficient noise margin cannot be secured, which means that the circuit operation may become unstable. To deal with this, make sure that the load impedances of the NAND gate and NOR gate are the same, for example, for the load FET of the NAND gate,
A gate width different from that of the NOR gate load FET must be set for each BC.

For example, in the above example, the gate width wgl of the NOR gate load FET is 6 μm, whereas the gate width wgl of the NAND gate needs to be about 3 μm. That is, it is necessary to prepare two types of gate widths for the load FET.

However, in a logic IC of a type in which basic cells having a predetermined function, such as a gate array, are arranged in advance and a predetermined logic is formed in accordance with a user's wish at a later stage, which portion on the bulk is That is, it is difficult to know in advance which cell is configured as a NOR gate or a NAND gate. Moreover, in a logic IC such as a gate array, it is conceivable that some cells will be wasted when logic is formed at a later stage. Under these conditions, it is not preferable to provide two types of gate widths for the load FET on the substrate because it narrows the effective space of the logic circuit. Therefore, there is no merit in preparing two types of gate widths for the load FET on the same bulk, and therefore, in terms of manufacturing efficiency and effective use of the FET, in general, the gate width for the load FET is It is designed with one type.

That is, in the conventional inverting logic type logic circuit, only one of the NOR gate and the NAND gate can be used as a function, and there is a problem that the logic function as a gate is weak.

Further, if a NOR gate and a NAND gate are configured using load FETs having a single gate width, the saturated drain current inevitably falls below the appropriate value at any of the gates. FE
It is conceivable that the operating speed of T will be sacrificed and eventually the performance in circuit operation will be reduced.

The present invention has been made in view of the above-mentioned problems in the prior art, and makes it possible to change the load impedance despite the fact that there is only one type of gate width for the load FET, and enhance the logic function per gate. At the same time, it is an object of the present invention to provide a logic circuit device capable of improving the performance in circuit operation.

[Means for Solving Problems] A problem in the above-described conventional technique is that a plurality of driving transistors and load transistors formed in an array with a predetermined gate width on a semiconductor bulk are provided. A drive transistor connected in series or in parallel, and a plurality of load transistors connected in series, wherein at least one source electrode of the drive transistor is connected to a low-potential power line. Connected, at least one drain electrode of the driving transistor is connected to an output terminal, one drain electrode of the load transistor is connected to a high-potential power line, and one source electrode of the load transistor is The number of the load transistors connected to the output terminal is equal to the number of the drive transistors connected in series. The gate electrodes of a large number of load transistors are connected to the output terminal, the gate electrodes of the remaining load transistors are connected to the high-potential power line, and an input signal is applied to each gate electrode of the drive transistor. It is solved by providing a logic circuit device characterized in that an output signal is obtained from the output terminal.

[Work]

Suppose now that the load transistor and drive transistor have gate lengths of Lgl and Lgd, respectively, and gate widths of Wg.
l and Wgd. Further, the number of load transistors connected in series is N, and the number of drive transistors connected in series is M (≦ N).

According to the above configuration, the gate electrodes of the M load transistors are connected to the output terminal, and the remaining gate electrodes, that is, (N
The gate electrodes of the (-M) load transistors are connected to the high-potential power supply line. Therefore, this (NM)
The individual load transistors do not participate in the current / voltage characteristics on the load transistor side. Therefore, the impedance ratio (W / L ratio on the load transistor side / W / L ratio on the drive transistor side) is {Wgl / (Lgl ・ M)} / {Wgl / (Lgl ・ M)} = (Wgl / Lgl)) / (Wgd / Lgd) …………… (1).

If the value of M is 1 (that is, it functions as a NOR gate), or if it is multiple (that is, it functions as a NAND gate)
In any of the cases, the impedance ratio has one value as shown in the equation (1). This means that the load impedance is changed equivalently even though the gate width of the load transistor is one type.

That is, the impedance ratio is kept constant regardless of whether it is composed of a NOR gate or a NAND gate, so that the logic threshold voltage for each gate can be maintained unchanged. This is to secure a sufficient noise margin and contribute to the stabilization of the turning operation when the multi-stage connection is performed for integration.

[Embodiment] FIG. 1 shows a circuit pattern for constituting a main part of a logic circuit device as an embodiment of the present invention. The example of FIG. 1 shows a circuit pattern for forming an inverter unit of a BEL circuit (Buffered FET Logic circuit).

In FIG. 1, reference numeral 10 denotes a semiconductor bulk made of GaAs (gallium arsenide), and a plurality of E-mode drive FETs having a predetermined gate width Wad (10 μm in this embodiment) are provided on the semiconductor bulk. 11D, 12D, 13D, ... Are formed in an array and have a predetermined gate width Wgl (6 μm in this embodiment).
With a plurality of negative D-mode FETs 11L, 12L, 13L, ...,
Are formed in an array.

On the drive FET side, a low-potential power supply line V _SS (-2V) is pattern-formed along the array direction of the load FET.
On the T side, a high potential power supply line V is provided along the array direction.
_DD (0V) is patterned. The hatched area in each FET indicates the source or drain region (S / D region), and the channel region is formed across this S / D region, and the gate electrode is patterned on this channel region. ing. Further, the threshold voltage of each drive FET is -0.3 V, and the threshold voltage of each load FET is -0.7 V.
The gate length Lg of each gate is
Both d and Lgl are formed to 1 μm. In this embodiment, one drive cell (1B.C.) is composed of two drive FETs and two load FETs.

FIGS. 2A and 2B show an example of the configuration of the logic circuit based on the circuit pattern of FIG. The illustration in Fig. 2 is 1B.
The case of a BFL circuit having a 2-input NOR gate configured by C. as an inverter unit is shown.

In the figure, the squares indicated by S / D indicate contact regions, which represent source electrodes or drain electrodes. The source electrodes of the drive FETs 11D and 12D are connected to the power supply line V _SS , and the drain electrodes thereof are both connected to the output terminal X. On the other hand, the gate electrode of the load FET 11L is connected to the output terminal X, and the drain side is shared with the source of the load FET 12L. The drain electrode of the load FET 12L is connected to the power supply line V _DD together with the gate electrode.

In addition, the power supply line V _DD and another power supply line V _EE (-3.6
V), an E-mode FET 21 having a gate electrode connected to the output terminal X, a diode 22 connected in the forward direction, and D
A source follower circuit consisting of mode FET 23 is connected. Although not shown in the pattern diagram, FET 21
Is formed so that the gate width is 12 μm, the gate length is 1 μm, and the threshold voltage is −0.3 V.
Has a gate width of 10 μm, a gate length of 1 μm, and a threshold voltage of −0.7V. The diode 22 is formed so that the width and the length of the element region are both 5 μm.

In the BFL circuit configured as shown in FIG. 2, first, it is driven by the nogate.
An input signal is applied to the gate electrodes A and B of the FETs 11D and 12D to obtain an inverted logic signal from the output terminal X, and the inverted logic signal is level-shifted by the source follower circuit and output from the terminal X '. ing.

According to the configuration of FIG. 2, in particular, the configuration of the NOR gate, the two drive FETs 11D and 12D are connected in parallel, and one of the drive FETs is in the cut-off state in operation.
The W / L ratio on the side is the same as in the case of one drive FET, and its value is 10. On the other hand, on the load FET side,
Since the gate electrode of the load FET 12L is connected to the power supply line V _DD , the element that affects the current / voltage characteristics is the load.
Only FET 11L is available. Therefore, the W / L ratio on the load FET side is 6, and the impedance ratio is 0.6.

3 (a) and 3 (b) show another configuration example of the logic circuit based on the circuit pattern of FIG. The example of FIG. 3 shows a case of a BFL circuit having a 2-input NAND gate configured by the same 1B.C. as an inverter unit.

The source electrode of the drive FET 11D is connected to the power supply line V _SS , the drain side is shared with the source of the drive FET 12D, and the drain electrode of the drive FET 12D is connected to the output terminal X. On the other hand, the source electrode of the load FET 11L is connected to the output terminal X, the drain side is shared with the source of the load FET 12L, and the drain electrode of the load FET 12L is connected to the power supply line V _DD . The gate electrodes of the load FETs 11L and 12L are both connected to the output terminal X. Further, a source follower circuit having the same configuration as in FIG. 2 is connected between the power supply line V _DD and another power supply line V _EE (−3.6V).

In the BFL circuit having the configuration shown in FIG. 3, first, an input signal is applied to the drive FETs 11D and 12D and the gate electrodes A and B by a NAND gate to obtain an inverted logic signal from the output terminal X, and the inverted logic signal is supplied to the source follower. The circuit is level-shifted and output from the terminal X '.

According to the configuration of FIG. 3, particularly the NAND gate configuration, the two drive FETs 11D and 12D are connected in series and both are in the ON state in the inverting logic operation, so the gate length is equivalent on the drive FET side. It is doubled, so the W / L ratio on the drive FET side is 5. On the other hand, on the load FET side, since the gate electrodes of the load FETs 11L and 12L are both connected to the output terminal X, both influence the current / voltage characteristics. Therefore, the gate length is equivalently doubled on the load FET side, and the W / L ratio on the load FET side is 3. Therefore, the impedance ratio becomes 0.6, which is the same value as in the case of the NOR gate in FIG.

That is, as shown in FIG. 1, the drive FET is different from the bulk in which only one type is formed as the gate width of the load FET.
By connecting the gate electrodes of the load FE, the number of which is equal to the number of connected in series, to the output terminal X, and connecting the gate electrodes of the remaining load FETs to the power supply line V _DD , the inverter section is constituted by a NOR gate. In any case, since the load impedance is changed according to the configuration on the drive FET side regardless of the NAND gate configuration, the impedance ratio for each gate can be made constant. This makes the logic threshold voltage of each gate invariable and ensures a sufficient noise margin.

Next, referring to FIGS. 4 (a) to 4 (d), the impedance change of the load in the configuration example of FIGS. 2 and 3 will be further described.

(1) When two load FETs are connected as shown in (a) (configuration example of FIG. 2); Since the gate electrode of the load FET 12L is connected to the power supply line V _DD , its current -The voltage characteristics are linear as shown by the one-dot chain line in (b). In contrast, the load FET 11
Since the gate electrode of L is connected to the output terminal X, the drain current is saturated when the source-drain voltage rises to some extent (see the broken line portion in (b)). Therefore, the characteristic of the load QL ₁ obtained by combining the two load FETs draws a curve according to the characteristic of the load FET 11L, as shown by the solid line in (b).
This means that even if a plurality of load FETs are connected in series, it is only the FET whose gate electrode is connected to the output terminal X that substantially affects the current / voltage characteristics as a load. It is meant.

Therefore, since the negative electrode FET 12L can be ignored in operation, only the load FET 11L should be focused on when considering the W / L ratio. Therefore, the W / L ratio is 6 (6 μm / 1) as described above.
μm).

(2) When two load FETs are connected as shown in (c) (configuration example of FIG. 3): Since the gate electrodes of the load FETs 11L and 12L are both connected to the output terminal X, The gate length becomes equivalent to double the FET, therefore the overall source-drain resistance increases and the drain current decreases, and its current-voltage characteristic is
Draw a curve as shown by the solid line in (d). The value of the saturated drain current at this time (about 0.2 mA) is smaller than that of the configuration example shown in (a) (about 0.3 mA).

In this configuration example, when considering the W / L ratio, load FET 11L
It is necessary to pay attention to both 12L and 12L. Therefore, the W / L ratio is 3 (6 μm / 2 μm) as described above.

That is, the impedance of the load can be changed even if the loads are load FETs having the same gate width. Then, by connecting each gate electrode of the plurality of load FETs to the power supply line V _DD or the output terminal X under the above-mentioned predetermined conditions, it is possible to realize the same impedance ratio for each configuration of the NOR gate and the NAND gate. Become.

In the above-described embodiments, a structure in which a plurality of FETs are connected in series as a load is adopted, but this may be a transistor having a structure including a plurality of gate electrodes.

For example, FIGS. 5 (a) and (b) and FIGS. 6 (a) and (b) show modified examples of the load in the configuration example of FIG. 2 and the configuration example of FIG. 3, respectively. The example of both figures shows the case of a dual gate type FET, in which G ₁ is the gate electrode of the load FET 11L,
G ₂ corresponds to the gate electrode of the load FET 12L.

Furthermore, in the above-described embodiment, the case where the number of load FETs connected is two has been described, but this may be any number as is apparent from the gist of the present invention.

For example, FIGS. 7 (a) to 7 (f) show a configuration example in which three load FETs are connected in series. (a) shows a configuration example of a 3-input NOR gate, (b) shows a configuration example of a combination gate in which one FET is connected in parallel to the driving side of a 2-input NAND gate, and (c) shows a configuration example of a 3-input NAND gate. Also, (d) to (f) are respectively
The modification of the load in the structural example of (a), (b), (c) is shown, and the gate connection aspect of a trigate type or a triple gate type transistor is shown. Further, in the configuration example shown in (a), the number of drive FETs connected in parallel is three,
It is needless to say that this may be any number, as is clear from the gist of the present invention. As shown in the respective configuration examples of (a) to (c), as many gate electrodes of the load FETs as the number of drive FETs connected in series are connected to the output terminal X, and the gates of the remaining load FETs are connected. Of course, the electrodes are connected to the high potential power supply line V _DD .

In each of the above-described embodiments, the case where the GaA MESFET is used as the transistor has been described, but the present invention is not limited to this, and the case where the n-type MOSFET formed on the semiconductor bulk of Si (silicon) is also used. A similar effect is expected.

〔The invention's effect〕

As described above, according to the present invention, the load impedance can be changed even though the gate width for the load FET is only one type, the logic function per gate can be enhanced, and the circuit operation can be improved. Performance can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit pattern for constituting a main part of a logic circuit device as an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are logic circuits based on the circuit pattern of FIG. 1A is a circuit diagram, FIG. 3B is a main part pattern diagram including a wiring pattern, and FIGS. 3A and 3B are logic diagrams based on the circuit pattern of FIG. It is a figure which shows the other structural example of a circuit, (a) is a circuit diagram, (b) is a principal part pattern diagram including a wiring pattern, FIGS. 4 (a)-(d) is FIG. 2 and FIG. For explaining the impedance change of the load in the configuration example of FIG. 5, FIGS. 5 (a) and 5 (b) are diagrams showing a modified example of the load in the configuration example of FIG. 2, (a) is an equivalent circuit diagram, b) is a pattern diagram, FIGS. 6 (a) and 6 (b) are diagrams showing a modification of the load in the configuration example of FIG. 3, (a) is an equivalent circuit diagram, (b) is a pattern diagram, and FIG. Figures (a) to (f) are other examples of the present invention. Circuit diagram depicting a configuration example of a logic circuit device as an example, FIG. 8 is a diagram showing an example of the configuration of a DCFL circuit, FIG. 9 is a a diagram showing an example of the transfer characteristic of Figure 8 circuit. (Explanation of symbols) 10 ... Semiconductor bulk, 11D, 12D, 13D ... Drive FET, 11L, 12L, 13L ... Load FET, Wgd ... Gate width of drive FET, Wgl ... Gate width of load FET, V _SS ... low-potential power line, V _DD ... high-potential power line, A, B, C ... gate electrode (input terminal), X ... output terminal.

Claims (2)

[Claims] 1. A plurality of drive transistors (11D, 12D, ...) And load transistors (11D, 12D, ...) Formed in an array on a semiconductor bulk (10) each having a predetermined gate width (Wgd, Wgl). 11L, 12L, ...) with a predetermined number of drive transistors (11D, 12D, 13D) connected in series or in parallel, and a plurality of load transistors (11L, 12L, 1
3L), the source electrode of at least one (11D) of the driving transistors is connected to a low-potential power supply line (V _SS ), and the drain of at least one (12D; 13D) of the driving transistors. The electrode is connected to the output terminal (X), the drain electrode of one of the load transistors (12L; 13L) is connected to the high-potential power supply line (V _DD ), and one of the load transistors (11L) Of the load transistors (11L; 11L, 12L; 11L, 12L, 13L) are connected to the output terminal (X) and the number of load transistors is equal to the number of the drive transistors connected in series. Has a gate electrode connected to the output terminal (X), and the gate electrodes of the remaining load transistors (12L; 12L, 13L; 13L) are connected to the high-potential power supply line (V _DD ). Transistor gate electrodes (A, B, C)
An input signal is applied to the output terminal (X) to obtain an output signal. 2. The plurality of load transistors (11L, 12L, 13L) connected in series are composed of a set of source and drain electrodes and at least two gate electrodes (G ₁ , G ₂ ). The logic circuit device according to claim 1, which is configured.