JPH067678B2 - Balanced modulation circuit with clamp - Google Patents

Description

TECHNICAL FIELD The present invention relates to a balanced modulation circuit with a clamp, in which a clamp circuit is added to the front stage.

(Prior Art) As a balanced modulation circuit for performing carrier wave suppression modulation, for example, a color encoder (encoding circuit) uses a chroma signal composed of a RY signal and a BY signal at a frequency of 3.58M.
It is a circuit that modulates with a subcarrier of Hz (color carrier) and uses the obtained modulated wave output signal as a part of a composite signal (composite signal). In such a balanced modulation circuit,
Since the applied chroma signal is different from the input DC bias point of the modulation circuit, capacitor coupling is usually used to connect the chroma signal to the modulation circuit. At this time, since the chroma signal itself contains a DC component, a large capacity coupling capacitor is used. However, when a large-capacity coupling capacitor is used, the input DC bias point of the modulation circuit is moved due to the DC component corresponding to the DC average value (APL). I am taking it.

Conventionally, as such a balanced modulation circuit with a clamp, for example, there is one as shown in FIG. The configuration will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a configuration of a conventional balanced modulation circuit with a clamp.

In FIG. 2, 1 is a clamp circuit, and 2 is a balanced modulation circuit. The clamp circuit 1 includes an input terminal 3 to which an input signal Vi such as a chroma signal is applied and a clamp pulse Vcp.
And a terminal 4 for inputting the input signal, and is connected to the balanced modulation circuit 2 through output terminals 5 and 6. The balanced modulation circuit 2 has terminals 7 and 8 for inputting a carrier wave Vs such as a subcarrier and an output terminal 9 for outputting a modulated wave Vo.

Then, in the clamp circuit 1, the input signal Vi is clamped by the clamp pulse Vcp, and its output is sent to the balanced modulation circuit 2 via the output terminals 5 and 6. Then the balanced modulation circuit 2
Then, the output signal of the clamp circuit 1 is used as a modulation signal, the modulation signal is modulated by the carrier wave Vs, the carrier wave component is removed, and the modulated wave Vo is output from the terminal 9.

FIG. 3 shows an example of the circuit configuration of FIG. Third
In the figure, 10 is a power supply terminal to which a power supply voltage Vcc is applied,
Reference numerals 11 and 11 are ground terminals that are held at the ground potential Vg.
The input signal generated by the input signal generator 12 is input to the input terminal 3.
Vi is given through the capacitor C1. In addition, terminal 7,
The carrier wave Vs generated by the carrier wave oscillator 13 is given to 8.

The clamp circuit 1 has current mirror connection lines 14 and 15, a power supply line 16 connected to the power supply terminal 10, and a ground wire 17 connected to the ground terminal 11. The input terminal 3 has a switching element, for example, an NPN type switching transistor Q1.
The collector of this switching transistor is connected
The base of Q1 is connected to the terminal 4 through the resistor R1, and the emitter is connected to the reference voltage point 18 having the reference voltage Vr.

The collector of the switching transistor Q1 is connected to the base of a PNP type transistor Q2, the emitter of this transistor Q2 is connected to the power supply line 16 via the constant current load transistor Q3, and the collector is connected to the ground line 17 respectively. . Here, the transistor Q2 constitutes an emitter follower stage (emitter follower amplifier circuit) in which the transistor Q3 serves as a constant current load.

On the other hand, the base of the PNP transistor Q4 is connected to the reference voltage point 18 to which the emitter of the switching transistor Q1 is connected. Further, the power supply line 16 is connected to the emitter of the transistor Q4 via the constant current load transistor Q5.
A ground wire 17 is connected to each collector.
Here, the transistor Q4 constitutes an emitter follower stage in which the transistor Q5 serves as a constant current source load. And
The base of the transistor Q5 is connected to the base of the transistor Q3 by a current mirror connection line 15, and the transistors Q5 and Q3 form a current mirror circuit.

On the left side of the transistor Q3 that constitutes the current mirror circuit,
A series circuit of a transistor Q6 and a constant current load transistor Q7 is provided. The collector of the transistor Q6 is connected to the power supply line 16, the emitter is connected to the collector of the transistor Q7, and the base is connected to the emitter of the switching transistor Q2. The emitter of the transistor Q7 is connected to the ground line 17, and the base is connected to the current mirror connection line 14. And transistor Q6 is transistor Q7
Constitutes a follower stage having a constant current source load, and the emitter of the transistor Q6 is connected to the output terminal 6.

On the right side of the transistor Q5 that constitutes the current mirror circuit,
A series circuit of a transistor Q8 and a constant current load transistor Q9 is provided. The collector of the transistor Q8 is connected to the power supply line 16, the emitter is connected to the collector of the transistor Q9, and the base is connected to the emitter of the transistor Q4. The emitter of the transistor Q9 is connected to the ground line 17, and the base thereof is connected to the current mirror connection line 14.
The transistor Q8 constitutes an emitter follower stage using the transistor Q9 as a constant current source load.
Is connected to the output terminal 5. Here, the transistor Q9 is connected to the transistor Q7 via the current mirror connection line 14.
Are connected to each other to form a current mirror circuit.

Further, a reference voltage source composed of a series circuit of transistors Q10 and Q11 for constant current load and resistors R2 and R3 is provided between the transistors 7 and 9. The transistor Q10 has an emitter connected to the power supply line 16, a base connected to the current mirror connection line 15, and a collector connected to its own base and one end of the resistor R2. The other end of the resistor R2 is connected to the reference voltage point 18, and the reference voltage Vr is applied to this reference voltage point 18. The collector of the transistor Q11 is connected to the reference voltage point 18 via the resistor R3,
The base of the transistor Q11 is connected to its own collector and the current mirror connection line 14, and the emitter thereof is connected to the ground line 17. Then, it is determined by the transistors Q10 and Q11 and the resistors R2 and R3. A current equal to the current 11 becomes the collector current of each of the transistors Q3, Q5, Q7, Q9 provided on both sides.

Balanced modulation circuit 2 provided on the output side of the clamp circuit 1
Are transistors Q12 and Q13 forming a differential amplifier, a pair of constant current load transistors Q14 and Q15, a pair of transistors Q16 and Q17 and transistors Q18 and Q19 forming a switching circuit, and resistors R4, R5 and R6. It is equipped with and is also called the Gilbird circuit.

Here, one transistor Q12 that constitutes the differential amplifier
Has its base at the output terminal 5, its collector at the emitter of each transistor Q16, Q17, and its emitter at the transistor Q14.
Connected to each collector. The other transistor Q13 has its base element connected to the output terminal 6, its collector connected to the emitters of the transistors Q18 and Q19, and its emitter connected to the collector of the transistor Q15. Furthermore, the emitter of each transistor Q12, Q13 is
Connected to each other through 4.

The emitters of the constant current load transistors Q14 and Q15 are connected to the power supply line 17, and the bases thereof are connected to the current mirror connection line 14. Then, a current equal to the current I1 in the clamp circuit 1 flows through the collectors of the transistors Q14 and Q15.

One of the transistors Q16 and Q1 that make up the switching circuit
Of the seven, the base of the transistor Q16 is connected to the terminal 7, the collector is connected to the power supply line 16 via the resistor R5, the base of the transistor Q17 is connected to the terminal 8 and the collector is connected to the power supply line 16 via the resistor R6. , Respectively.
Of the other transistors Q18 and Q19, the base of the transistor Q18 is the terminal 8 and the collector is the power supply line 16 via the resistor R5.
Further, the base of the transistor Q19 is connected to the terminal 7 and the collector is connected to the power supply line 16 via the resistor R6. Further, the collector of the transistor Q19 is connected to the output terminal 9.

The operation of the parallel modulation circuit with the clamp configured as described above will be described with reference to FIG. Note that FIG. 4 is a waveform diagram of the input signal Vi, the clamp pulse Vcp, the voltage of the output end 6, and the modulated wave Vo that is the output.

The input signal Vi generated by the input signal generator 12 is the capacitor C1.
And the clamp pulse Vcp is applied to the terminal 4.

When the clamp pulse Vcp is at the high level of the potential Vcc (hereinafter referred to as H level), the current I2 flows and the switching transistor Q1 is turned on. From this transistor Q
The base DC bias of 2 is clamped to the reference voltage Vr. Then, even if the potential Vg becomes low level (hereinafter referred to as L level) by the clamp pulse Vcp and the switching transistor Q1 is turned off, the base DC bias of the transistor Q2 is held at the voltage Vr by the capacitor C1.

After the base DC bias of the transistor Q2 is set in this way, the input signal Vi is superimposed on this voltage Vr. Then, the superimposed signal is subjected to impedance conversion by the transistors Q2 and Q6 forming a so-called level shift stage, and is applied to the output terminal 6 as a stabilized voltage (Vr + Vi). Therefore, the base of the transistor Q13 in the parallel modulation circuit 2 connected to the output terminal 6 is
A constant voltage (Vr + Vi) is applied.

On the other hand, the reference voltage Vr at the reference voltage point 18 is impedance-converted by the transistors Q4 and Q8 forming a so-called level shift stage to become a stabilized bias voltage Vr, and this bias voltage Vr is balanced through the output terminal 5. It is given to the base of the transistor Q12 in the modulation circuit 2.

In the balanced modulation circuit 2, the voltage Vr is input to the base of the transistor Q12, the voltage (Vr + Vi) is input to the base of the transistor Q13, and the carrier Vs generated by the carrier oscillator 13 is input via the terminals 7 and 8. It is provided to the bases of the transistors Q16 to Q19. Transistors Q12 and Q13 that form the differential amplifier amplify the difference Vi between both input voltages with a gain R6 / R4 to form transistors Q16 to Q that form a switching circuit.
Give to 19 emitters. Each of the transistors Q16 to 19 turns on and off to invert the phase of the carrier wave Vs. Therefore, the balanced modulation circuit 2 works to multiply the input signal Vi and the carrier wave Vs, and sends out the modulated wave Vo having the envelope as shown in FIG. 4 from the output terminal 9.

In order to correct the movement of the input DC bias point of the modulator 2 during operation, the clamp pulse Vcp becomes L level (ground potential Vg) at a constant cycle. Then, during this L level period, the voltage at the output end 6 is clamped to the reference voltage, whereby the output ends 5 and 6 become the same voltage Vr, and the modulated wave Vo that is the output becomes zero.

In the above-described clamped balanced modulation circuit, if the circuit is not balanced, the carrier leaks to the output (this is called carrier leak), which causes adverse effects such as noise generation on the output side. Here, the circuit equilibrium conditions for minimizing the carrier leak are as follows: (1) Between the output terminals 5 and 6 connected to the input side of the transistors Q12 and Q13 forming the differential amplifier, a DC bias is applied. It is important that there is no difference (this is called offset) and that (2) there is no difference in DC bias between the terminals 7 and 8 connected to the input side of the transistors Q16 to Q19 that form the switching circuit. Is an element.

(Problems to be Solved by the Invention) However, in the balanced modulation circuit with a clamp having the above configuration, although the offset between the terminals 7 and 8 can be removed, an offset occurs between the terminals 5 and 6. That is, in the clamp circuit 1, the collector-emitter voltage Vcesat generated by the resistance when the switching transistor Q1 is on.
Therefore, the voltage at the output terminal 6 of the transistor Q6 becomes higher than the voltage Vr at the output terminal 5 of the transistor Q8, so that the balance modulation circuit 2 loses its balance, which causes carrier leakage. there were.

The present invention provides a balanced modulation circuit with a clamp, which solves the problem that the above-mentioned prior art has, that an offset occurs between two outputs of the clamp circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a reference voltage source that generates a reference voltage, a switching element that superimposes an input signal input via a capacitor and the reference voltage. And a balanced modulation circuit that inputs the reference voltage and the output of the switching element as a modulation signal, modulates this with a carrier wave, and outputs a modulated wave signal in which a carrier wave component is suppressed. In the balanced modulation circuit with a clamp, a switch means for dropping the voltage by the same value as the voltage drop value when the switching element is turned on is provided, and the reference voltage is input to the balanced modulation circuit via the switch means. It was done.

(Operation) According to the present invention, since the balanced modulation circuit with a clamp is configured as described above, the switching means lowers the reference voltage applied from the reference voltage source by the same voltage value as when the switching element is turned on. Apply to balanced modulation circuit. As a result, the DC bias difference (offset) between the two inputs applied to the balanced modulation circuit from the clamp circuit becomes zero. Therefore, the problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a balanced modulation circuit with a clamp showing an embodiment of the present invention. In FIG. 1, the same elements as those in FIG. 3 are designated by the same reference numerals.

The difference of this balanced modulation circuit with clamp from that of FIG. 3 is as follows. The NPN type switching transistor Q1 in Fig. 3 is a PNP type switching transistor (switching element) Q21 with a small saturation voltage. A resistor R21 is inserted between the base and emitter of this transistor Q21 to turn off the transistor Q21. Is making faster. The PNP transistor Q2 in FIG. 3 is replaced by an NPN transistor Q22, the constant current load transistor Q3 in FIG. 3 is replaced by a resistor R23, and this resistor R23 is replaced by a transistor Q6 in the transistors Q22, Q6 connected in Darlington. It is connected between the base and emitter. Similarly, the PNP transistor Q4 in FIG. 3 is replaced by the NPN transistor Q24, and the constant current load transistor Q5 in FIG. 3 is replaced by the resistor R2.
5 and the resistor R25 is connected between the base and emitter of the transistor Q8 in the transistors Q24 and Q8 connected in Darlington. Furthermore, in this embodiment, the reference voltage point
Switch means, that is, a switch circuit 30, is connected between 18 and the base of the transistor Q24. Switch circuit
30 includes a PNP type switching transistor Q30 having the same characteristics as the switching transistor Q21 and the resistors R1 and R21 and a small saturation voltage, and resistors R30 and R31. PNP
The emitter of the switching transistor Q30 is connected to the reference voltage point 18, the collector is connected to the base of the transistor Q24, and the base is connected to the earth line 17 via the resistor R31. R30 is connected between the emitter and base of transistor Q30.

In FIG. 1, I3 is a current flowing through the resistor R1 and I4 is a current flowing through the resistor R31. Further, in the circuit of FIG. 1, the carrier offset between the terminals 7 and 8 in the balanced modulation circuit 2 is zero, and moreover, the element characteristics of the transistors, resistors and the like which form the clamp circuit 1 and the balanced modulation circuit 2 are matched. It is assumed that

In the clamped balanced modulation circuit configured as described above, assuming that the voltage Vbe is between the base and the emitter of the switching transistor Q21, when the clamp pulse Vcp applied to the terminal 4 is at the L level, the current I3 flowing through the resistor R1.
Is And the transistor Q21 is turned on. Then, (reference voltage Vr-saturation voltage Vcesa of transistor Q21
voltage t) is applied to the collector of transistor Q21,
This voltage is impedance-converted by the transistors Q22 and Q6 and given to the output terminal 6.

However, in this embodiment, the switch circuit 30 is provided, and one end of the resistor 31 in the switch circuit 30 is grounded. Therefore, assuming that the base-emitter voltage of the transistor Q30 is equal to Q21, Vbe is the resistance. Current I4 flowing through R31
Is Becomes Here, the resistors R1 = R31 and R21 = R30 are selected, so the current I3 = I4, the collector current and base current of each transistor Q21, Q30 become equal, and the saturation voltage of both transistors Q21, Q30 becomes equal. Become. Therefore, the collector of the transistor Q30 is connected to the transistor Q21.
The same voltage as the collector voltage is applied, and this voltage is impedance-converted by the transistors Q24 and Q8 and given to the output terminal 5.

Since the switch circuit 30 is provided in this way, the base DC bias points of the transistors Q22 and Q24 become the same potential,
As a result, the bias voltage of the same potential is applied to the clamp circuit output terminals 5 and 6, and the offset becomes zero. Therefore, the balance degree of the balanced modulation circuit 2 is kept uniform, and the occurrence of carrier leak can be prevented. Further, since the switch circuit 30, especially the transistor Q30 which is a switch element, has the same characteristics as the switching transistor Q21,
Both transistors Q21 and Q30 can be easily matched.

Although the balanced modulation circuit 2 is configured by a so-called Gilbert circuit in the above embodiment, the present invention is not limited to this, and a carrier suppression double sideband modulation circuit (DSB-SC),
It can also be applied to carrier suppression single sideband modulation circuits (SSD). Also, in the above embodiment, the PNP type transistor Q30 having the same characteristics as the PNP switching transistor Q21 which is the switching element is provided.
The transistor 30 may be composed of another transistor having the same characteristics, such as an NPN transistor or a MOS transistor. Further, other circuit elements (that is, transistors and resistors) in the clamp circuit 1 and the balanced modulation circuit 2 other than the above can be configured by other matched circuit elements. For example, transistors other than the transistors Q21 and Q30 may be PNP type transistors, MOS type transistors, etc., or each resistor may be a load transistor.

(Effect of the Invention) As described in detail above, according to the present invention, the switch means for dropping the voltage by the same value as the potential drop value when the switching element is turned on is provided, and the reference voltage is supplied via this switch means. Since it was input to the balanced modulation circuit,
When the function of the switching element is imperfect, for example, even if there is a voltage drop when the switching element is on, this is canceled by another switch means provided and the clamp circuit 2
The offset generated between the outputs can be reduced to zero, and the carrier leak at the output of the balanced modulation circuit can be eliminated.

[Brief description of drawings]

1 is a circuit diagram of a balanced modulation circuit with a clamp showing an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a conventional balanced modulation circuit with a clamp, FIG. 3 is a circuit diagram of FIG. 2, and FIG. Is the third
It is a signal waveform diagram of each part of the circuit in the figure. 1 ... Clamp circuit, 2 ... Balanced modulation circuit, 5, 6 ...
Output terminal, 18 ... reference voltage point, 30 ... switch circuit (switch means), Vcc ... power supply voltage, Vi ... input signal, Vo ...
… Modulated signal, Vs …… Carrier, C1 …… Capacitor, R2, R
3, Q11 …… Reference voltage source, Q21 …… Switching transistor (switch element), Q30 …… Transistor.

Claims (1)

[Claims] 1. A reference voltage source for generating a reference voltage from an applied power supply voltage, an input signal input via a capacitor and the reference voltage are applied to turn on a clamp pulse,
A clamp circuit having a switching element that is turned off and superimposes the input signal on the reference voltage, and the reference voltage and the output of the switching element are input as a modulation signal, and the modulation signal is modulated by a carrier to generate a carrier component. In a balanced modulation circuit with a clamp that suppresses the output of a modulated wave signal and outputs a modulated wave signal, switch means for dropping the voltage by the same value as the voltage drop value when the switching element is turned on is provided, A balanced modulation circuit with a clamp, wherein a reference voltage supplied from a reference voltage source is input to the balanced modulation circuit via the switch means.