JPH0677187B2 - Color liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a liquid crystal display composed of color dots (hereinafter referred to as “pixels”) of three primary colors of red (R), green (G) and blue (B). It is related to the color liquid crystal display device of the "mosaic type multi-color liquid crystal display" consisting of elements, and in particular, 3 rows of R, G, and B (3 columns) with adjacent columns have 3 rows that are also adjacent to this column. The present invention relates to a color liquid crystal display device including one minimum drawing unit (hereinafter, referred to as one pixel) formed of, for example, a square formed by (3 rows, 3 columns, 9 pixels). At this time, if one pixel is a row and the beginning of a column is R, for example, R, G, B /
9 pixels of B, R, G / G, B, R)
The present invention relates to a color liquid crystal display device in which a large number of pixels are arranged for high quality display.

<Prior Art> Examples of conventional color liquid crystal display device technologies include Nikkei Electronics "Product development of a controller dedicated to lively LCD" (issued on July 30, 1984) and the same "Commercialized liquid crystal pocket color TV" ( (Published September 10, 1984) etc. are publicly known. The outline of the conventional technique will be described below with reference to the drawings.

FIG. 3 is a color arrangement diagram of a mosaic type multi-color liquid crystal display element, and FIG. 4 is a block system diagram for explaining an outline of a conventional color liquid crystal display device. Incidentally, the attached numbers are added for convenience of explanation of the present invention and are not essentially necessary (the same applies hereinafter).

In FIG. 3 and FIG. 4, the liquid crystal display element 1 is a mosaic type color in which one pixel (α) is formed by each pixel P of R, G and B, and the apparent resolution is highest with the same number of pixels. It has a layout structure. The liquid crystal display element 1 includes a display data memory 3 for holding serial data Sd input in the display unit 2 in a one-to-one correspondence with pixels in a horizontal row, and a selected row. The color liquid crystal display is driven by the column driver 4 which outputs a control signal in synchronization with the serial data Sd for driving the. Here, one pixel is almost square, for example, the first column and "R ₁
^One pixel of " ¹ , G ₂ ¹ , B ₃ ¹ " is driven collectively.
5 R, G, parallel data H _P and the horizontal synchronizing signal H _S of B, generally CRT controller on the market for outputting a vertical synchronizing signal V _S and the shift clock S _C, etc. (hereinafter referred to as "CRTC circuit"), color sequential selection circuit sequentially outputs the selection to the select signal the beginning of a different pixel color line each time there is the horizontal synchronizing signal H _S to input horizontal synchronizing signal H _S 6, 7 shift clock S _C a color-by-color is a parallel / serial conversion circuit for outputting the parallel data H display _P a is converted into serial data Sd of pixel data memory 3 input selection signal and on the basis of the sequential selection circuit 6.

In such a configuration, the selection signal is guided to the parallel / serial conversion circuit 7 each time there is a horizontal synchronization signal H _S from the color-by-color sequential selection circuit 6. Parallel / serial conversion circuit 7
May convert the parallel data H _P from CRTC circuit 5 R formed by horizontal row in accordance with the color arrangement of the liquid crystal display device 1, G, B1 pixel shift clock S _C sequential serial data Sd in synchronization with the Then, the data is transferred to the display data memory 3. When the transfer of all the rows is completed and there is a selection signal from the color-by-color sequential selection circuit 6, the parallel / serial conversion circuit 7 performs the conversion of the next row. On the other hand, one line of the transferred serial data Sd is written in the display data memory 3. Column driver 4 is initialized by the vertical synchronizing signal V _S, and outputs a signal indicating the upper-left corner of the initial position of the liquid crystal display device 1, the switching operation of the line in synchronism with the serial data Sd by the horizontal synchronizing signal H _Y To do. Therefore, the memory contents of the display data memory 3 and the color display of the row selected by the column driver 4 are formed on the liquid crystal element display 1.

<Problems to be Solved by the Invention> By the way, in this conventional color liquid crystal display device, each pixel is formed in a horizontal row in one pixel unit such as “R ₁ ¹ , G ₂ ¹ , B ₃ ¹ ” ,. Since it is driven, pixels α _{1 to} α ₃₅ (for example, "1" as shown in the display diagram for explaining the problem of the conventional technique in FIG.
When the characters are driven by 15 pixels in the horizontal direction and 5 pixels are turned on and 7 lines in the vertical direction are turned on), the aspect ratio of 1 pixel is 1: 3. Therefore, the display type becomes unnatural, and there is a problem in the liquid crystal display quality.

To solve this problem, for example, as shown in Japanese Patent Laid-Open No. 59-204878, the shape of the display electrode of the liquid crystal pixel is changed to a polygon, or each line is shifted by 1/2 pixel to form two lines. It is conceivable to allocate a substantially equilateral triangle extending over 1 to one pixel, or to create and display the shape to be displayed by software in accordance with the color arrangement of each pixel.

However, doing so makes the shape of the liquid crystal element special, so it lacks general versatility, and there are many disadvantages in terms of manufacturing cost. In addition, the burden on the software increases, drawing speed and software productivity However, there are many problems to be solved, and even if it is put into practical use, it will be an expensive product, so it is not common.

The present invention has been made in view of the problems of this conventional technique, and does not change the liquid crystal display array in which the conventional pixel array has a mosaic pattern, and uses a commercially available inexpensive CRTC circuit. Then, the parallel data from the CRTC circuit is used as it is, and the configuration of one pixel on the liquid crystal display element is adjoined on a pixel-by-pixel basis in three columns by the hardware configuration of the display data processing unit without special software.
By displaying color liquid crystal by lines (9 pixels),
An object of the present invention is to provide a color liquid crystal display device capable of improving display quality and high-speed drawing.

<Means for Solving Problems> In order to achieve such an object, according to the present invention, a mosaic liquid crystal display element in which the arrangement of RGB is repeated every three rows in the same arrangement is provided in a CRT control circuit. In a color liquid crystal display device driven based on output pixel data, a data latch circuit for temporarily latching parallel data for several pixels output by the CRT control circuit, and pixels for several pixels held in this data latch circuit A group of registers for holding data in three registers, which are arranged such that their interconnections are changed so as to become RGB corresponding to the row arrangement of the liquid crystal display element, and the data held in the registers is based on a shift clock. , A register control circuit for continuously reading from the register, and a selected register from the pixel data read from the three registers of the register group. The output control unit that outputs the star data to the display data memory of the liquid crystal display element as serial display data, and the pixel data register corresponding to the row that outputs the count value of the horizontal synchronization signal of the CRT control circuit. A row counter circuit for outputting a row count signal to the output control section, and pixel data output by the row unit from the CRT control circuit is repeatedly supplied three times to the liquid crystal display element through a data latch circuit. A color liquid crystal display device characterized in that three pixels are arranged in three rows.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings.
In the following drawings, the same parts as those in FIGS. 3 to 5 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a block diagram of a color liquid crystal display device showing a specific embodiment of the present invention, and FIG. 2 is a pixel configuration diagram in the present invention.

In FIGS. 1 and 2, reference numeral 20 denotes a display unit including a liquid crystal display element 100, a display data memory 3 provided to drive each pixel of the liquid crystal display element 100, and a column driver 4. . Here, the liquid crystal display device 100 is composed of 9 pixels arranged in 3 columns and 3 rows in which a large number of RGB pixels are arranged and 1 pixel β (suffix indicates a pixel No.) is arranged. Is formed. For example, in the first pixel β ₁ , the first row and the horizontal three columns
R ₁ ¹ , G ₂ ¹ , B ₃ ¹ / _3rd horizontal row of 2nd row B ₁ ² , R ₂ ² , G ₃ ² / 3rd horizontal row of 3rd row G ₁ ³ , B ₂ ³ , R ₃ It becomes ³ . Reference numeral 50 is a CRTC circuit including a frame memory 50a for storing ON / OFF information of each pixel, a controller 50b for managing / controlling display information, horizontal / vertical synchronizing signals and the like. This CRTC circuit 50 is RGB 3
As described above, one pixel β of the primary color is formed in a square shape over three adjacent columns and three rows on the liquid crystal display, and at least a plurality of identical pixel data are overlapped three times, for example, five pixels.
Parallel data H _P (R a 15bit (but not limited to a description will be given of a case where using the following in the present invention),
G, B, R, ...) and a horizontal synchronizing signal H _S , a vertical synchronizing signal V _S , a latch pulse L _P, and a shift clock S _C. Since the latch pulse L _P is obtained by dividing the shift clock S _C ,
Such a function may be provided outside the CRTC circuit 50. However, in the present application, even in such a case, the technology is substantially equivalent to the case where the latch pulse L _P is output from the CRTC circuit 50. In other words, this CRTC circuit 50 uses a generally commercially available type similar to the conventional circuit configuration.
Reference numeral 70 denotes a display data processing unit including a data latch circuit 8, a register control circuit 9, a row number counter circuit 10, and a data selector circuit 11. Data latch circuit 8 is made for example to latch a plurality of parallel data H _P by the latch pulse L _P a (8BitD-F / F) of two using the 15Bit configuration. The register control circuit 9 is composed of, for example, a 4-bit binary counter which inputs the shift clock S _C and the horizontal synchronizing signal H _S and outputs a register control signal for driving and controlling the register group 11a described later. The row counter circuit 10 uses a horizontal sync signal.
It consists of, for example, a 4-bit binary counter that inputs H _S and the vertical synchronization signal V _S , counts the number of rows, and outputs a row number count signal. The data selector circuit 11 includes a register group 11a and an output control circuit 11b. Here, the register group 11a has three shift registers (for example, 8 bit parallel input / serial output) arranged by changing the mutual connection so that the data latch signal from the data clutch circuit 8 becomes RGB corresponding to each row. Shift register) consists of SR ₀ ~ SR ₂ , shift clock
Operated by S _C and register control signals. On the other hand, the output control circuit 11b is composed of, for example, a 4-input / 1-output multiplexer, each output terminal of the register group 11a is connected, and the output of the register group 11a (SR ₀ is 1, 4,
.. line, SR ₁ is 2, 5, ..., Line ₂ and SR ₂ is 3, 6, ..., Output), and serial data Sd is transferred to the display data memory 3. It should be noted that three shift registers SR _{0 to} SR ₂ are provided as the register group 11a in the pixel arrangement of the liquid crystal display screen in three ways of RGBR ..., BRGB ... and GBRG ... (the same arrangement is repeated every three rows). It is because there is. By configuring the display data processing unit 70 in this way, it is described below that the parallel data Hp of 15 bits for 5 pixels supplied from the CRTC circuit 50 at one time via the data latch circuit 8 is periodically selected. The operation will be described while describing the details.

Data latch circuit 8 transfers the 15Bit parallel data H _P of the register group 11a are immediately latched After you output all data in the output control circuit 11b in the register group 11a,
The new parallel data H _P input from CRTC circuit 50. In the register group 11a, there are three types of color arrangements of color pixels for every three rows, so three shift registers are arranged corresponding to each row, and color data of 5 pixels are rearranged by connection lines, same parallel data H _P simultaneously from the data latch circuit 8 with respect to the three shift registers is parallel transfer. Parallel data H _P transferred at this time, at the time of input, for example Shifutoreshisuta SR ₀ The example 1,4,7, ... row R, G, B, R, ... is controlled so as to enter , The shift register SR ₁ receives, for example, the B, R, G, B, ... Of the _2nd , 5th, 8th, ... Rows, and the shift register SR 2 receives, for example, the 3,6,9, ... row. G, B,
R, G, ... are input. This input is controlled by the register control signal from the register control circuit 9 initialized by the vertical synchronizing signal V _S. Parallel data input to each shift register SR _{0 to} SR ₂
H _P, based on a signal for controlling the shift operation / load operation from the register control circuit 9, a parallel - serial data conversion is outputted to the output control circuit 11b is performed (three shift registers are both operated ing). Output control circuit 11
In b, it operates so as to select only one of the three inputs based on the row counter signal from the row counter circuit 10. That is, the row number counter circuit 10 uses the horizontal synchronization signal H _S
The output control circuit 11b is connected to the shift register SR ₀ when 1 is counted by the row count signal. At this time,
The other two shift registers SR ₁ and SR ₂ have the data corresponding to the second and third rows and are ignored. As soon as the last B ₁₅ ¹ of the 5 pixels in the first row is output from the shift register SR ₀ to the output control circuit 11b, the next 5 pixels (R ₁₆ ^{1 to} B ₃₁
¹ ) is input from the data latch circuit 8. When the scanning of the first row is completed in this way, the register control circuit 9 is initialized by the horizontal synchronizing signal H _S. Row counter circuit 10
Counts the horizontal synchronizing signal H _S , and connects the output control circuit 11b and the shift register SR ₁ when 2 is counted. As a result, only the shift register SR ₁ is valid in the register group 11a. Parallel data H _P from CRTC circuit 50 is exactly the same as the first row of the same column (in pixels), and than rearranged at the point of input of the shift register SR ₁ is performed, the subsequent operation first The same scanning as in the row is performed. When the scanning of the second row is completed, the register control circuit 9 is initialized by the horizontal synchronizing signal H _S. When the third row is further scanned, the row counter circuit 10 counts the horizontal synchronizing signal H _S , and when 3 is counted, connects the output control circuit 11b and the shift register SR ₂ . As a result, only the shift register SR ₂ is valid in the register group 11a. CRTC circuit 5
Parallel data H _P from 0 is exactly the same as the first row of the same column (in pixels), and than rearranged at the point of input of the shift register SR ₂ is performed, the subsequent operation the first and second The same scanning as in the row is performed. In the same manner, the fourth line (SR ₀ is connected) and the subsequent lines are scanned.

As a result, according to the pixel information transferred from the output control circuit 11b to the display unit 20 as the serial data Sd, in FIG. 2 corresponding to FIG. 5, the first pixel β ₁ becomes “R ₁ ^1. G ₂ ¹ / B ₃ ¹ "," B ₁ ² / R ₂ ² / G ₃ ² "," G ₁ ³ / B ₂ ³ / R ₃ ³ "The second pixel β2 is" R ₄ ¹ / G ₅ ¹・ B ₆ ¹ "," B ₄ ²・ R ₅ ²・ G ₆ ² "," G ₄ ³・ B ₅ ³・ R ₆ ³ "... the 35th pixel β ₃₅ is" R ₁₃ ¹⁹・ G ₁₄ ¹⁹・"B ₁₅ ¹⁹ ", "B ₁₃ ²⁰ / R ₁₄ ²⁰ / G ₁₅ ²⁰ ", "G ₁₃ ²¹ / B ₁₄ ²¹ / R ₁₅ ²¹ " are displayed. By comparing FIG. 2 and FIG. 5, it can be seen that the display quality is obviously improved.

In this way, by arranging the order of the color pixels and selecting the pixel in such a manner that the hardware scans three times to determine one pixel, it becomes unnecessary to process the drawing data by software, and as a result, in the CRTC circuit. Drawing memory is also CRT
The same capacity as that for driving is required. That is,
It is not necessary to use a large capacity memory for the color liquid crystal display device.

<Effects of the Invention> As described above in detail with reference to the embodiments of the present invention,
According to the color liquid crystal display device of the present invention in which one pixel of a liquid crystal display element is displayed by hardware in three adjacent columns and three rows by using a conventional CRTC circuit and a display unit, a commercially available CRTC circuit is used as it is. It can be used to draw on a liquid crystal display device (as if by software CR
You can see it like what you see in T).
Further, the CRTC circuit requires only one row of memory capacity to scan three lines, and has the feature that the screen can be rewritten faster than the technique of drawing only by software. In addition, it is possible to easily display a vertically long shape as compared with the conventional horizontally long shape, so that the equal pixel shape becomes natural and the display quality can be improved. That is, there is an effect that it is possible to provide a color liquid crystal display device that performs high-quality display easily and relatively inexpensively using a conventional color liquid crystal display element having a mosaic type pixel arrangement.

[Brief description of drawings]

FIG. 1 is a block diagram of a color liquid crystal display device showing a specific embodiment of the invention, FIG. 2 is a pixel configuration diagram in the invention, and FIG. 3 is a color arrangement diagram of a mosaic type multicolor liquid crystal display element. FIG. 4 is a block system diagram for explaining an outline of a conventional color liquid crystal display device, and FIG. 5 is a display diagram for explaining problems of the conventional technique. 1 ... Liquid crystal display element, 2,20 ... Display section, 5,50 ... CRT controller circuit, 7 ... Parallel / serial conversion circuit,
8: data latch circuit, 9: register control circuit, 10
...... Line count circuit, 11 …… Data selector circuit.

Claims (1)

[Claims] 1. A color liquid crystal display device for driving a mosaic liquid crystal display element in which RGB is repeated every three rows in the same arrangement based on pixel data output from a CRT control circuit. And a data latch circuit for temporarily latching parallel data for several pixels output from each other, and pixel data for several pixels held in this data latch circuit are mutually converted so as to become RGB corresponding to the row arrangement of the liquid crystal display elements. A register group that holds three registers whose wirings are changed, a register control circuit that continuously reads the data held in the register from the register based on a shift clock, and three of the register groups. From the pixel data read from each register, the data in the selected register is serially displayed in the display data memory of the liquid crystal display device. An output control unit for outputting as a display data, and a row counter for outputting a row count signal to the output control unit for selecting a register of pixel data corresponding to a row to be output with a count value obtained by counting the horizontal synchronizing signal of the CRT control circuit. And a circuit is provided, and pixel data in units of rows output from the CRT control circuit is repeatedly supplied to the liquid crystal display element through a data latch circuit three times, and three rows and three columns are configured as one pixel. Color liquid crystal display device.