JPH0677234B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to a branch instruction exception interrupt processing method.

[Conventional technology]

Conventionally, it was sufficient if one branching instruction exception interrupt processing method was realized in one information processing apparatus.

[Problems to be solved by the invention]

However, in recent years, the idea of a virtual machine or a complex machine has been demanded even at the device level, and it has become necessary to realize a plurality of branch instruction exception interrupt processing methods on one information processing device.

Also, exception detection related to instruction fetch address calculation is
It is sufficient to expand an effective address to a real address and detect an exception such as a missing page at the time of first fetching a series of soft instructions and when an instruction tries to cross a page boundary.

Although a branch instruction always expands the effective address of the branch address to the real address, it does not use the exception related to the branch address of the branch instruction as the exception of the branch instruction itself, but the exception related to the instruction fetch of the branch destination instruction of the branch instruction. This method has a drawback in that it cannot detect an exception relating to the instruction fetch of a branch destination instruction of a general instruction including a branch instruction.

In view of the above points, an object of the present invention is to provide an exception interrupt processing method for generating an interrupt as an exception of a branch address of a branch instruction itself when an exception related to a branch address of a branch instruction is detected, and an instruction fetch of a branch destination instruction of the branch instruction. It is an object of the present invention to provide an information processing apparatus capable of realizing two types of branch instruction exception interrupt processing methods, one of which is an exception interrupt processing method of generating an interrupt as an exception of No.

[Means for solving problems]

An information processing apparatus of the present invention is an information processing apparatus for processing a soft instruction corresponding to a series of microinstruction groups, and a branch indicating whether or not the soft instruction is a branch instruction when the soft instruction is executed. A branch instruction identifying means for generating an instruction identification signal; and a branch determination signal for generating a branch determination signal indicating whether the execution result of the branch instruction is a branch instruction or a branch instruction when the soft instruction is a branch instruction. Means, exception detection means for generating an exception detection signal indicating whether or not an exception has occurred at the time of generating the instruction address of the soft instruction, and execution of the soft instruction when processing the exception detected by the exception detection means. Mask signal holding means for holding a mask signal indicating whether or not to suppress the branch instruction, a branch instruction identification signal from the branch instruction identification means, and the branch determination means. By referring to the branch determination signal, the exception detection signal from the exception detection means, and the mask signal from the mask signal holding means, Exception control means for generating an address of a microinstruction, wherein the soft instruction is a branch instruction,
A series of micro-instructions that inhibit the execution of the branch instruction and perform exception interrupt processing to perform the exception interrupt processing of the branch instruction, or a series of exception interrupt processing after the execution of the branch instruction is completed Whether the micro-instruction is activated to perform the exception interrupt processing of the branch destination instruction of the branch instruction is performed based on the control signal from the exception control means and the address of the micro instruction.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the outline of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus according to the present embodiment is composed of an instruction unit 1, a control storage unit 2, an execution unit 3 and an exception control circuit 4 as a main part thereof.

The instruction unit 1 fetches a target instruction from a main memory (not shown) that stores a series of soft instructions and their operands, decodes the instruction, and fetches the operand. This instruction unit 1 is also called a preceding control unit that performs an instruction prefetching operation, and an exception detection unit 11 that detects an exception relating to instruction fetching or an operand fetching of this instruction, and a branch determination that determines a branch success or branch failure regarding a branch instruction. And part 12.

The control storage unit 2 can store a plurality of microinstruction words and sequentially execute a series of microprograms. The control storage unit 2 is also given the address of the first step of the microprogram corresponding to the soft instruction from the instruction unit 1 and can control the sequential arithmetic processing.

The execution unit 3 is a pipelined arithmetic unit having a plurality of arithmetic stages, and its arithmetic operation is controlled by the control storage unit 2. The arithmetic operation in the execution unit 3 is completed by the end of the last arithmetic stage of the arithmetic pipeline. That is, if it is canceled in the middle of the arithmetic pipeline, the execution operation is suppressed.

The exception control circuit 4 includes an exception detection signal ex detected by the exception detection unit 11 of the instruction unit 1 and a branch determination unit of the instruction unit 1.
Branch instruction identification signal br and branch determination signal go determined in 12
And the execution of the instruction in which an exception has been detected (hereinafter abbreviated as an exception detection instruction) in the execution unit 3 from the mask signal mk as a flag that determines the exception interruption method of the branch instruction held by the exception control circuit 4. By limiting and activating a specific microprogram stored in the control storage unit 2, the execution unit 3 is controlled and two exception interrupt processing methods are realized.

In FIG. 1, a plurality of lines connecting the instruction unit 1, the control storage unit 2, the execution unit 3, and the exception control circuit 4 represent the flow of control signals or control data, respectively.

FIG. 2 shows the information processing apparatus shown in FIG. 1 in more detail, and particularly shows the exception control circuit 4 in FIG. 1 in detail. Instruction unit 1 in FIG.
It goes without saying that the control memory unit 2, the arithmetic unit 3, and the exception control circuit 4 correspond to those shown in FIG. 1, respectively.

In FIG. 2, the exception detection unit included in the instruction unit 1
Reference numeral 11 detects an exception relating to the first instruction fetch of a series of software instructions and branch address calculation of a branch instruction, and supplies the exception detection signal ex to the exception control circuit 4 via a signal line 111. Further, the instruction unit 1 has a branch judging section 12, and the branch judging section 12 outputs a branch instruction identification signal br and a branch judging signal go for judging whether the branch succeeded or failed, respectively.
It is given to the exception control circuit 4 via 2 and 113. Here, it is assumed that the branch determination signal go indicates a successful branch. The exception detection signal ex, the branch instruction identification signal br, and the branch determination signal go
Shall be generated in pulses in synchronization with the respective instructions.

The control memory unit 2 includes a control memory 21 for storing a plurality of microinstruction words, an address register 22 for giving an address to the control memory 21 via a signal line 206, and an address given by the address register 22 from the control memory 21. It is composed of a control storage register 23 that receives and holds the read microinstruction word via a signal line 207, and an address circuit 24 that modifies and selects a signal that is an input to the address register 22.

The start address ia of the microprogram corresponding to the soft instruction is given from the instruction unit 1 to the address circuit 24 via the signal line 201, and is selected by the instruction start signal st given from the instruction unit 1 via the signal line 204. .

When the start address ia of the microprogram corresponding to the soft instruction is given to the address register 22, if the microprogram is composed of a plurality of microinstruction words,
Next, the address designated by the microinstruction word corresponding to the address held by the address register 22 is given to the address circuit 24 via the signal line 202 and supplied to the address register 22.

If the address circuit 24 of the control storage unit 2 is shown by a truth table, it will be as shown in the table below. Note that s0 = c0 + c1 and s1 = st
-V, c0 is a control signal held by the register 42, c1 is a control signal held by the register 43, and v is a flip-flop
The signal held by 45 is a valid state signal indicating the valid states of the A stage, B stage and C stage. Also na
Is the next address of the microinstruction word stored in the control memory 21 corresponding to the address held by the address register 22.

Further, the input data and the hold condition of the address register 22 and the control storage register 23 of the control storage unit 2 are as follows.

(1) Address register 22 input data = ca (2) Control memory register 23 input data = part of the microinstruction word held by the control memory 21 corresponding to the address held by the address register 22 The execution unit 3 is composed of a plurality of pipelined arithmetic stages and is controlled by the control storage unit 2 to perform arithmetic operations for instruction execution. Here, the number of operation stages of the execution unit 3 is 3. The address register 22 of the control storage unit 2 is set to the A stage, and the control storage register 23
Is a B stage, and the three stages of the execution unit 3 are called a C stage, a D stage, and an E stage, respectively.

The hold condition and the cancel condition regarding the operation stage of the execution unit 3 are as follows.

(3) C stage hold condition = cancel condition = c2 (4) D stage and E stage hold condition = 0 cancel condition = 0 The control memory 21 of the control memory unit 2 stores the register 41 of the exception control circuit 4. The register 41 is a 1-bit register that holds the value indicated by the micro instruction word, and the register 41 is used as a flag that holds the mask signal mk that determines the branch instruction exception interrupt processing method.

The exception control circuit 4 holds the exception detection signal ex detected by the exception detection unit 11 of the instruction unit 1, the branch instruction identification signal br and the branch determination signal go generated by the branch determination unit 12 of the instruction unit 1, and the register 41. The operation is determined by the state of the mask signal mk.

Exception detection signal ex, branch instruction identification signal br, branch determination signal go
The mask signal mk and the mask signal mk are signals generated corresponding to the soft instructions, respectively, and are signals existing on the B stage in synchronization with the control signal held by the control storage register 23 of the control storage unit 2.

The registers 42, 43 and 44 of the exception control circuit 4 are each 1
In the bit control register, the input data is determined by the states of the exception detection signal ex, the branch instruction identification signal br, the branch determination signal go and the mask signal mk, and the output signal selectively inhibits the exception detection instruction, and Execution of all the instructions subsequent to the exception detection instruction is suppressed, and the control storage unit 2 is controlled to start a series of microprograms that perform exception interrupt processing. The 1-bit control signal held in the register 44 is c2.

The flip-flop 45 is for indicating the valid states of the signals on the A stage, B stage and C stage, and outputs a valid state signal v.

The input data and the hold conditions of the registers 41, 42, 43 and 44 of the exception control circuit 2 and the reset condition and the set condition of the flip-flop 45 can be represented by logical expressions as follows.

(5) Register 41 input data = instruction data by program command word stored in control memory 21 (6) Input data of register 42 = v ・ ex ・ (▲ ▼ ＋ br ・ go ・ ▲
▼) Hold condition = 0 (7) Register 43 input data ＝ v ・ ex ・ br ・ go ・ mk Hold condition = 0 (8) Register 44 input data ＝ c0 ＋ c1 Hold condition = 0 (9) Flip-flop 45 Reset condition ＝ v・ Ex ・ (▲ ▼ ＋ br ・ go ・ ▲
▼) + c1 set condition = c2 The initial values of the registers 41, 42, 43 and 44 are "0", and the initial value of the flip-flop 45 is "1".

The address register generator 46 of the exception control circuit 4 can be represented by the truth table as shown in the table below.

The abbreviations given to the condition signals of the registers and flip-flops in FIG. 2 have the following meanings.

HLD: Hold RST: Reset SET: Set CSL: Cancel Next, the operation of the information processing apparatus of the present embodiment configured as described above will be described with reference to the time charts of FIGS. 3, 4, and 5. explain. Incidentally, FIG. 3, FIG. 4 and FIG.
In the figure, a, b, c, d and f are micro steps corresponding to a series of software instructions, and one instruction corresponds to one micro step.

FIG. 3 shows the operation when the exception detected by the branch instruction is treated as the exception of the branch instruction itself and the exception interrupt processing is performed.

In FIG. 3, the instruction a advances through the pipeline in stages from the A stage in every clock cycle, and completes execution at clock cycle t ₅ . The instruction b is a branch instruction following the instruction a, and an exception is detected at the branch address of the branch instruction on the B stage of the clock cycle t ₃ , and the exception detection signal ex, the branch instruction identification signal br, and the branch determination signal go are turned on. And the mask signal mk is not turned on.

The exception control circuit 4 judges that this state is to be used as the exception of the branch instruction itself to perform the exception interrupt processing, and the clock cycle t ₄
Then, the flip-flop 45 is reset and the A stage, the B stage and the C stage are made invalid, and at the same time, the register 42 is set to "1".

At clock cycle t ₄ , branch instruction b is held on the C stage. At this time, the instruction a preceding the branch instruction b
Exists on the D stage, but advances through the arithmetic stage without being held, and completes the execution of the instruction.

The control signal c0 held by the register 42 is a clock cycle.
At the same time at t ₄ is set to the register 44 "1", the start address e ₀ of a series of microprogram for performing exception interrupt processing
Is generated by the address generator 46, supplied to the address circuit 24 via the signal lines 406 and 203 and supplied to the address register 22, thereby preparing to start a series of microprograms for performing exception interrupt processing.

Control signal register 44 at the clock cycle t ₅ holds c2
Sets the microinstruction word corresponding to the start address e ₀ of the series of microprograms for canceling the branch instruction b held on the C stage and performing the exception interrupt processing in the control storage register 23, and The second step address e ₁ is set in the address register 22. At this time, control number c2 held by register 44
Simultaneously sets flip-flop 45.

Clock flip-flop 45 at cycle t ₆ becomes a set state is activated a series of micro-program for subsequent exception interrupt processing, exception interrupt processing of the branch instruction b has a series of microprogram detects an exception of performing the exception interrupt processing To do. As a result of this operation, the execution of the branch instruction b and the instructions c and d subsequent thereto are suppressed.

FIG. 4 and FIG. 5 show the operation when an exception detected by a branch instruction is treated as an exception of a branch destination instruction of a branch instruction to perform exception interrupt processing.

In FIG. 4, the instruction a advances through the pipeline in stages from the A stage in each clock cycle, and completes execution at clock cycle t ₅ . The instruction b is a branch instruction following the instruction a, and an exception is detected at the branch address of the branch instruction on the B stage of the clock cycle t ₃ , and the exception detection signal ex, the branch instruction identification signal br, and the branch determination signal go are turned on. And the mask signal mk is also turned on.

Exception control circuit 4 determines the state and performs exception interrupt processing exception of instruction fetch of the branch destination instruction of the branch instruction, and a register 43 at the clock cycle t ₄ "1".

At clock cycle t ₄ , the branch instruction b is not held on the C stage and advances through the operation stage together with the instruction a preceding the branch instruction b to complete the execution of the instruction.

The exception signal c1 held by the register 43 sets the register 44 to “1” at the clock cycle t ₄ and at the same time, activates the branch destination instruction of the branch instruction as the first instruction of the series of soft instructions. The start address p ₀ is generated by the address generator 46 and supplied to the address register 22 to prepare for starting a series of microprograms for starting the branch destination instruction of the branch instruction as the first instruction of the series of soft instructions. Further, the flip-flop 45 is reset to make the A stage, the B stage and the C stage invalid.

The instruction c following the branch instruction b held on the C stage at the clock cycle t ₅ is canceled by the control signal c 2 held by the register 44, and the branch destination instruction of the branch instruction is the first instruction of the series of soft instructions. The microinstruction word corresponding to the start address p ₀ of the series of microprograms activated as is set in the control storage register 23, and the second step address p ₁ of the microprogram is set in the address register 22. At this time, the control signal c2 held by the register 44 simultaneously sets the flip-flop 45.

Flip-flop 45 at clock cycle t ₆ becomes a set state is activated a series of micro-program that starts a branch target instruction of the subsequent branch instruction as the first instruction of a series of software instructions, the branch target instruction of the microprogram branch instruction Is restarted from the instruction fetch as the first instruction of the series of soft instructions.

In FIG. 5, the instruction x existing on the A stage of the clock cycle t ₁ is the last step of the series of microprograms which starts the branch destination instruction of the branch instruction with the series of soft instructions as the first instruction. The instruction C ′ existing on the A stage at the clock cycle t ₂ is the branch destination instruction of the branch instruction b which has been executed at the clock cycle t ₆ in FIG. 4, and is fetched as the first instruction of the series of soft instructions. It is an instruction started from.

It is assumed that when the instruction c'exists on the B stage at the clock cycle t ₃ , an exception relating to the instruction fetch of the instruction c'is detected and only the exception detection signal ex is turned on. At this time, even if the instruction name C'is a branch instruction, the branch instruction identification signal br and the mask signal are detected at the time of detecting an exception related to the instruction fetch.
The mk is not turned on. In addition, the register 42 is set to “1” by the exception detection signal ex and the flip-flop
45 is reset.

At clock cycle t ₄ , instruction c'is held on the C stage. At this time, the control signal c0 held by the register 42
For 0, the register 44 is set to "1" and at the same time, the start address e ₀
Is generated by the address generator 46 and supplied to the address register 22, thereby preparing to start a series of microprograms for performing exception interrupt processing.

Control signal register 44 at the clock cycle t ₅ holds c2
Is the branch destination instruction c ′ held on the C stage.
And a microinstruction word corresponding to the start address e ₀ of a series of microprograms that perform exception interrupt processing is set in the control storage register 23, and the second step address e ₁ of this microprogram is set in the address register 22. To do. At this time, the control signal c2 held by the register 44 simultaneously sets the flip-flop 45.

Flip-flop 45 at clock cycle t ₆ becomes a set state, subsequent series of microprogram for performing exception interrupt processing is started, the branch destination instruction c of the branch instruction b has a series of microprogram detects an exception of performing the exception interrupt processing Exception handling related to the instruction fetch of 'is performed.

Exception control circuit 4 performed through FIG. 4 and FIG.
As a result, the branch instruction b is completed and the execution of the branch destination instruction c'and all the instructions following it is suppressed.

It should be noted that FIG. 6 is a flow chart showing the operation of the hardware and the microprogram described with reference to FIGS. 2, 3, 4, and 5. In FIG. 6, the pseudo exception corresponds to the case where the mask signal mk is on. Therefore, in the process flow of FIGS. 3 and 5, the determination of the pseudo exception is omitted with no, and in the process flow of FIG. 4, the determination of the pseudo exception is rejected with yes. This 6th
The processing shown in the figure is clear from the time charts shown in FIGS. 3, 4, and 5, and thus detailed description thereof will be omitted.

〔The invention's effect〕

As described above, the present invention provides a flag that determines whether an interrupt is generated as an exception of the branch address of the branch instruction itself or an exception of the instruction fetch of the branch destination instruction of this branch instruction. There is an effect that one exception detecting means can realize two types of branch instruction exception interrupt processing methods.

[Brief description of drawings]

1 is a schematic block diagram of an information processing apparatus showing an embodiment of the present invention, FIG. 2 is a block diagram showing the information processing apparatus shown in FIG. 1 in more detail, FIG. 3, FIG. 4 and FIG. FIG. 5 is a time chart showing the operation timing of the information processing apparatus shown in FIG. 2, and FIG. 6 is a flowchart showing the overall processing in the information processing apparatus of the present invention. In the figure, 1 ... Instruction unit, 2 ... Control storage unit, 3 ... Execution unit, 4 ... Exception control circuit, 11 ... Exception detection section, 12 ... Branch determination section, 21 ... Control storage, 22 ...... Address register, 23 ...... Control storage register, 24 ...... Address circuit, 41,42,43,44 ...... Register, 45 ...... Flip-flop, 46 ...... Address generator, 111 to 113,201 to 208,406 ...... Signal It is a line.

Claims (1)

[Claims] 1. An information processing apparatus for processing a soft instruction corresponding to a series of microinstruction groups, wherein a branch instruction identification signal indicating whether or not the soft instruction is a branch instruction when the soft instruction is executed. A branch instruction identifying means for generating a branch instruction identifying means for generating a branch determination signal indicating whether the execution result of the branch instruction is a branch instruction or a non-branch instruction when the soft instruction is a branch instruction, Exception detection means for generating an exception detection signal indicating whether or not an exception has occurred at the time of generating the instruction address of the soft instruction, and execution of the soft instruction during the processing of the exception detected by the exception detection means. Mask signal holding means for holding a mask signal indicating whether to inhibit, branch instruction identification signal from the branch instruction identification means, and branch from the branch determination means By referring to the constant signal, the exception detection signal from the exception detection means, and the mask signal from the mask signal holding means, a control signal and a microinstruction for processing the exception generated at the generation of the branch destination address of the branch instruction. And an exception control unit for generating an address of the branch instruction. When the soft instruction is a branch instruction, a series of micro instructions for suppressing execution of the branch instruction and performing exception interrupt processing are activated to execute the branch instruction. Whether to perform exception interrupt processing or to start a series of micro-instructions that perform exception interrupt processing after the execution of the branch instruction is completed and perform exception interrupt processing of the branch destination instruction of the branch instruction, the exception control An information processing device, characterized in that it is performed based on a control signal from a means and an address of a micro instruction.