JPH0680487B2 - Processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device, and more specifically, it performs N-ary operation on two pieces of variable length data and stores the effective data portion of the obtained result in the variable length. The present invention relates to an N-ary overflow detecting means for detecting that an effective data length is longer than the length of a storage area in an arithmetic processing unit for outputting to an area. Less than,
The case of a general decimal operation instruction will be described.

[Background of the Invention]

Decimal operation instructions are addition, subtraction between a variable-length first operand of the number expressed in the binary coded decimal format and a variable-length second operand also expressed in the binary coded decimal format, Multiplication and division are performed, and the result is stored in the first operand area. The instruction format includes an operation code that specifies the type of operation, start addresses of the first and second operands, and a value that indicates the length of the first and second operands. For example, the processing of a decimal addition instruction ends when the second operand is added to the first operand and the result is stored in the first operand area. At this time, the first
The value of the length of the operand also represents the length of the area in which the result is to be stored, and the operation result cannot be stored in the area of the first operand, and a part of the valid result may be lost. For example, data loss may occur in the addition result when the length of the first operand is longer than that of the first operand. However, it is not always possible to lose valid data only by the length of the operand, and even if the second operand length is relatively long, data will always be lost if there are consecutive 0s in the upper digits. Not necessarily.

When the decimal operation result overflows and data is lost, whether to programmatically generate an interrupt depends on
Although it is controlled by the interrupt control mask, the overflow detection method depends on the hardware circuit.

Conventionally, Japanese Patent Publication No. 57-46574 "Oversize data detector" has been known as a method for rapidly detecting that an operation result has overflowed. This is to generate a status signal for every digit of all digits of the operation result whether or not it is valid data, and then use a decode signal of the first operand area length to generate a status signal in the result storage area (first operand area) of the status signal. ), Take out only the status signal that exists outside
This is designed so that overflow detection can be performed at high speed.

However, the above conventional method has a drawback that a large number of dedicated hardware circuits must be arranged only for detecting overflow. That is, a circuit, a signal selector, and a non-destination status generator for detecting the status (all 0 or all 1) of each byte of the operation result as shown in FIGS. Moreover, it is necessary to prepare an all-byte status generator etc. as dedicated hardware used only for overflow detection. As described above, the increase in the hardware specified by the overflow detection raises the cost of the computer and causes the decrease in reliability due to the increase in the number of gates.

Also. The above conventional method is applied to zoned binary coded decimal data and coded variable-length pure binary coded format data in addition to packed binary coded decimal data used in ordinary decimal operation instructions. Although it is a mechanism that can detect overflow, the latter two overflow detections are unnecessary in a general computer and are not the most suitable method for normal decimal arithmetic overflow detection. Absent.

Further, when a decimal overflow is detected, the program interrupt is controlled by the interrupt control mask, but the interrupt may occur after the data in which a part of the operation result has been lost is stored in the first operand area. . That is,
It is sufficient to complete the decimal instruction that caused the overflow. Therefore, it suffices if the overflow can be detected in parallel with the operation result storing operation, and it is necessary to provide a large amount of dedicated hardware to detect the overflow almost simultaneously with the operation result as disclosed in Japanese Patent Publication No. 57-46574. There is no.

[Object of the Invention]

An object of the present invention is to provide an arithmetic processing device that does not require a large amount of hardware for detecting an arithmetic overflow in N-ary arithmetic of two variable length data.

[Outline of Invention]

The feature of the arithmetic processing unit of the present invention is that the digit used for normalizing the arithmetic result of the floating point arithmetic
In an information processing device equipped with an encoder, each variable-length data to be operated is divided from the lower digit into a predetermined number of digits of a predetermined length, and the operation of the lower number of digits of a predetermined length is performed. An N-ary adder with a predetermined number of digits for performing N-ary operation by sequentially performing the carry of the operation results for the operation of the upper digit with a predetermined number of digits, and an N-ary adder with the digit encoder. The highest effective digit position output means for retrieving the calculation result of and outputting the value indicating the highest position of effective data, and the value output by this highest effective digit position output means and the value indicating the length of the storage area On the basis of this, the occurrence of overflow is detected because the effective data length of the operation result of the N-ary adder is longer than the storage area, and the operation of the final predetermined number of digits for the N-ary operation from the N-ary adder is performed. Result carry and operation pair Lies in and a overflow detection means codes the N-ary calculation of variable length data to detect the occurrence of the overflow by a bit indicating whether it is the addition or subtraction of.

Example of Invention

 An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing an overflow detection device for a 16-digit decimal operation result. In FIG. 1, reference numeral 2 denotes an 8-byte (64-bit) binary adder, each of which has input compensators 1a and 1b at its input and an output compensator 3 at its output, and binary addition and subtraction It constitutes a general binary / decimal combined adder capable of decimal addition and subtraction. The carry from the most significant bit of the binary adder 2 is input to the carry register (CAR) 4, and its output is again provided to the least significant bit of the binary adder 2 and also supplied to the overflow decision circuit 13. ing. The output of the output corrector 3 is
Binary / decimal combination adder 2 operation result itself is Z bus 5
Sent to the result store (not explicitly shown in the figure) by the overflow detection logic 15
It is supplied to the encoder 6. The structure of the digit encoder 6 is as shown in FIG. 2, and the 64-bit operation result on the Z bus 5 is digitized by the OR circuits 200 to 215 (4 bits).
16 outputs P _{0 to} P _{15 are} obtained every time, and these outputs P _{0 to} P ₁₅ are given to a general 16-bit priority encoder 30 to obtain encoding results E _{0 to} E _4. is there. FIG. 3 shows the logical operation of the encoder 30.

The encoding result of the digit encoder 6 indicates where the leading position of a valid row (non-zero value) of the operation result is, and is used for various processes. For example, when the binary / decimal combination adder 2 performs binary addition with a floating point addition instruction, unnecessary upper digit zero of the operation result is removed, and the removed digit equivalent value is output from the intermediate exponent part. Although there is a normalization process of subtraction, the encoder 6 is used when detecting the upper unnecessary digit zero of the operation result at this time. Further, if the encoding results E _{0 to} E ₄ are all 1, it indicates that the operation result is all 0, so it is used as a condition of the condition code to be set in the operation result state, or the operation result is zero. It is also used as a test condition for microinstructions that proceed while testing whether or not they exist. Thus, although the encoder 6 resides within the overflow detection logic 15, its hardware is not necessarily used only for overflow detection.

Of the outputs E _{0 to} E ₄ of the digit encoder 6, E _{0 to} E ₃
Is fed to the comparator 9 and E ₄ is not connected. That is,
Since the storage area of the first operand is defined in units of bytes for detecting the overflow of the decimal operation, the comparator 9 does not need E ₄ indicating which digit in the byte.

The comparator 9 is a circuit for comparing the outputs E _{0 to} E ₃ of the encoder 6 with the values L1 ₀ , L1 ₁ , L1 ₂ and L1 ₃ indicating the storage area length of the first operand. Value indicated by L1 ₀ ~L1 ₃ is intended to be given as the first operand length decimal instructions, in general decimal instructions, a 1-byte only shorter than the actual number of bytes. For example, L1 ₀ L1 ₁ L1 ₂ L1 ₃ = 0101, and the storage area length is 5 + 1 = 6 bytes.

FIG. 4 shows a configuration example of the comparator 9. In FIG. 4, 30
0 to 307 are AND circuits, 310 to 315 are OR circuits, and 230 to 322 are inverters. The comparator 9 is shown in FIG. 5 (a) (L1 ₀ = 1
When), FIG. 5 (b) (L1 ₀ = carry C ₀ from the respective first bit operation shown in the time) of 0 (when L1 ₀ = 1), when the C ₁ (L1 ₀ = 0) the seeking, when L1 ₀ = 1, when C ₀ = 0 in OV0 and the L1 ₁ = 0, and outputs the OV1 in C ₁ = 0, respectively. OV0 and OV1 indicate that an overflow has occurred under each condition.

The output 10 (OV0, OV1) of the comparator 9 is input to the overflow determination circuit 13. The overflow determination circuit 13 further includes a code S1 of the first operand and a code S of the second operand.
2. A signal A indicating that it is a decimal addition instruction (A = 0 when it is a decimal subtraction instruction) is input. The overflow determination circuit 13 outputs, as an output, a signal OVF indicating that a decimal operation overflow has been detected, to the output line 14.

FIG. 6 shows a configuration example of the overflow decision circuit 13. In FIG. 6, 400 is an exclusive OR circuit, 401 is an AND circuit, and 402 is an OR circuit. That is, the overflow determination circuit 13 performs a logical operation of OVF = OV0 + OV1 + CAR · (S1S2A). Here, (S1S2A) is a condition indicating that the decimal adder performs addition between two pieces of data having the same sign. CAR ・ (S1S2A) is the same code 2
When an addition is made between two data, it indicates that there was a carry CAR from the first bit of the binary adder 2, which means that the operation result exceeds 8 bytes or 16 bytes. At this time, if the first operand length and the second operand length are both 8 bytes or less, an overflow has occurred, and if either the first operand length or the second operand length exceeds 8 bytes, , First, the latter half 8 bytes are calculated, but at that time
The CAR is not given to the overflow decision circuit 13 and is used at the time of the addition of the remaining bytes to be performed next through the path supplied to the least significant bit of the binary adder 2. The CAR generated at this time is decided as the overflow. By being provided to the circuit 13, the overflow can be detected.

<Operation of Embodiment> Two pieces of variable-length binary coded decimal data are given to the binary adder 2 from the X bus and the Y bus through the input correctors 1a and 1b, respectively. To be The output is corrected by the output corrector 3 based on the result of the binary addition by the binary adder 2,
The calculation result is supplied to the Z bus 5. The result of this calculation is sent to the result storage unit, where the storage operation is started. On the other hand, the contents of the Z bus 5 are supplied to the digit encoder 6, and the encoded outputs E _{0 to} E ₄ indicating the position of the most significant digit are obtained on the signal line 7. Of this encoded output, E _{0 to} E ₃
Is given to the comparator 9 to indicate the value L1 ₀ L indicating the first operand length.
Compared to 1 ₁ L1 ₂ L1 ₃ . The mechanism of the comparator 9 is as shown in FIG. 5, and the number of bytes in the storage area (L1 ₀ L1 ₁ L1 ₂ L1 ₃ +
1) From the number of effective bytes of the operation result ( _{0 1 2 3} +
1) is subtracted. At this time, if the storage area exceeds 8 bytes, overflow occurs if there is no carry C ₀ , and if the storage area is 8 bytes or less,
Without carry C ₁ overflows. However, when the storage area exceeds 8 bytes, the first 8 bytes of the latter half are operated. At this time, the digit encoder 6 operates normally, but when the remaining bytes are operated next, the operation is performed. When E ₀ of the digit-encoded output for the result is 0 (there is a significant digit), it is sent to the digit-encoded comparator 9 of the operation result of the remaining bytes, but when E ₀ is 1 (the remaining digit is There is no significant digit in the byte operation), and E _{1 to} E ₄ use the previous digit encoder result. In this way, the digit-encoded output may be divided depending on the size of the storage area.
This is because the 8-byte arithmetic unit is used for the data existing up to 16 bytes, and if the 16-byte arithmetic unit is used, such a thing does not occur. Therefore, switching the output of the digit encoder 6 is not the basis of the present invention. The digit encoder is used only as a means for detecting the leading significant digit.

The outputs OV0, OV1 of the comparator 9 are given to the overflow determination circuit 13 by the signal line 10, and if either of them is turned on, the overflow is detected. However, since there is a case where the comparator 9 cannot detect it, a logic for detecting it is added to the overflow determination circuit 13. For example, the calculation result becomes all 0 (E _{0 to} E ₃
= 1111) This is the case where the carry CAR of the binary adder 2 occurs, that is, the carry from the first bit in the case where two data of the same sign are added. The carry at this time indicates that the operation result does not enter the storage area, and the output of the comparator 9 cannot detect it. Therefore, as shown in FIG.
Overflow is detected by the condition (S1S2A) and the logical sum of the outputs OV0 and OV1 of the comparator 9. However, if the arithmetic unit width is 16 bytes and the output is 17 bytes, and an encoder is provided for the output to detect the significant digit, overflow can be detected in the same manner as the comparator 9.

The above-described decimal operation overflow detection is performed in parallel with the operation result storage operation, and the overflow is detected by the time the storage is completed and the corresponding instruction is completed.

〔The invention's effect〕

According to the present invention, a digit encoder used for normalizing an operation result of a floating-point operation while executing variable N data by dividing variable-length data into a predetermined length and repeating an operation of a predetermined length. Since it is used for overflow detection, overflow can be detected with a small amount of hardware. Therefore, the amount of hardware can be reduced in the computer as a whole.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a detailed configuration diagram of the digit encoder, FIG. 3 is an operation explanatory diagram of the 16-bit priority encoder in the digit encoder, FIG. 4 is a detailed configuration diagram of the comparator in FIG. 1, and FIG. 5 is a comparator. 6 is a detailed configuration diagram of the overflow determination circuit in FIG. 2 ... Binary adder, 4 ... Carry register, 6 ...
Digit encoder, 9 ... comparator, 13 ... overflow decision circuit, 15 ... overflow detection logic section.

Claims (1)

[Claims] 1. An information processing apparatus equipped with a digit encoder used for normalizing the operation result of a floating point operation, performs N-ary operation on two variable length data, and specifies the operation result. An arithmetic processing unit for outputting a portion to a variable-length storage area, wherein each of the variable-length data is divided from a lower digit into a portion having a predetermined number of digits, and the predetermined length is given from the lower digit. An N-ary adder having a predetermined number of digits for performing the N-ary operation by sequentially performing the operation of the number of digits of , The digit encoder determines the operation result of the N-ary adder and outputs the value indicating the highest position of the effective data, and the highest effective digit position output means outputs the value. Value and storage area Based on the value indicating the length, the N
The occurrence of overflow is detected when the effective data length of the operation result of the binary adder is longer than the storage area, and the operation of the last digit part of the predetermined length with respect to the N-ary operation from the N-ary adder is performed. Overflow occurrence detecting means for detecting occurrence of an overflow by a carry of the result, a code of the two pieces of variable-length data, and a bit indicating whether the N-ary operation is addition or subtraction. Processing unit.