JPH0680513B2 - Input / output circuit of microcomputer with built-in EPROM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an input / output circuit of a microcomputer with built-in EPROM.

(B) Conventional technology Conventionally, in a microcomputer having a built-in EPROM capable of writing / reading data, when the input / output circuit of the microcomputer is switched to a pull-up, pull-down, or open-drain state. ,
That is, when selecting the input / output option of the microcomputer, each of the input / output options is selected based on the independent control data of each bit written in a predetermined area of the EPROM.

(C) Problems to be Solved by the Invention However, in the above-mentioned conventional technique, the control data for selecting the input / output option of the microcomputer is independent by one bit depending on each input / output option, which is different. There is a risk that each input / output option corresponding to the control data may be selected at the same time due to some malfunction.

Usually, a microcomputer and an EPROM have an output current of, for example, 200 μA, 4 under a high-level output voltage condition.
It is different from 00 μA, and the output current in EPROM mode is larger. However, if the EPROM is built into the microcomputer, the I / O terminal of the microcomputer and the data terminal of the EPROM will be shared.
The output current in the OM mode cannot be obtained from the input / output terminals of the microcomputer, that is, the normal PR
Even if the OM writer was connected, the data written in the EPROM could not be recognized, and there was a problem that a new PROM writer that met the standard of the output current of the microcomputer had to be used.

(D) Means for Solving the Problems The present invention has been made to solve the above problems, and is characterized in that a first transistor connected between an input / output terminal and a power supply is provided. And a second transistor connected between the input / output terminal and ground, and a third transistor interposed between the input / output terminal and the first transistor and connected in series with the first and second transistors. A fourth transistor connected in parallel with the second transistor, a fifth transistor connected in parallel with the first transistor, an input circuit for fetching input data applied to the input / output terminal into an internal circuit, and a data EPROM in which control data for controlling the third and fourth transistors are written in at least two specific areas, and the EPROM A latch control circuit for latching the control data read from the specific area at different latch timings and outputting the latched control data, and controlling the third and fourth transistors based on the output data, normal data or the EPROM. A first gate circuit for switching and outputting read data, and operating the first and second transistors based on the switching output data, and a second gate circuit for operating the fifth transistor based on the output of the first gate circuit. A gate circuit, and the EPRO
When the data is not read from M, the third and fourth transistors are controlled based on the control data written in the specific area of the EPROM, and the output obtained from the first gate circuit is based on the normal data. By controlling the first and second transistors, the input / output terminal is set to a predetermined input / output state, and when data is read from the EPROM, the first gate circuit is based on the read data of the EPROM. According to the output obtained from the first
And the second transistor are operated in a complementary manner, and the fifth transistor is operated by an output obtained via the first and second gate circuits based on the read data of the EPROM, so that the input / output terminal is The EP
The point is to set the ROM data read state.

(E) Operation The present invention is provided in the EPROM built-in microcomputer and is effective as follows.

That is, it comprises a first transistor connected between the input / output terminal and the power supply, and a second transistor connected between the input / output terminal and the ground. In an input / output circuit of an EPROM built-in microcomputer including an output circuit in which two transistors are controlled, an input circuit for taking in input data applied to an input / output terminal into an internal circuit, and an EPROM capable of writing / reading data A third transistor is connected in series with the first transistor between the input / output terminal and the power supply, a fourth transistor is connected between the input / output terminal and the ground, and a fifth transistor is the first transistor between the input / output terminal and the power supply. It is connected in parallel with.

When the control data is read from the predetermined area of the EPROM, the control circuit based on the control data sets the other of the third and fourth transistors to the exclusive state only when one of the third and fourth transistors is in the predetermined state. To be done. Therefore, the pull-down, CMOS buffer, or open drain state is selected as the input / output option of the microcomputer.

Further, when the first signal is generated at the time of reading the data from the EPROM, the first transistor and the fifth transistor are simultaneously driven by the gate circuit that operates based on the first signal and the control data. At the same time, since the second signal is generated, the control circuit that operates based on the second signal forces the third transistor to be driven and the fourth transistor to be non-driven. Therefore, when the data is read from the EPROM, the EPROM mode in which the output current of the EPROM larger than the output current of the microcomputer is obtained based on the high level output voltage is selected.

(F) Example The details of the present invention will be specifically described with reference to the illustrated example.

1 is a circuit diagram showing an input / output circuit of a microcomputer with built-in EPROM of the present invention. Describing the reference numerals and the configuration of the drawing, (1) is an input / output terminal for inputting / outputting I / O data, and (2) is Data can be written / read
EPROM, (3) is a NAND gate, and in a normal microcomputer data input mode, a "1" microcomputer selection signal CS is applied to one input terminal of the NAND gate (3) to cause the NAND gate to operate. (3) operates, and the data applied to the input / output terminal (1) in a state where the drain of the N-MOS (22), which will be described later, is floated through the NAND gate (3) to the data bus (4). ) Is taken in. Further, (30) is a NAND gate,
In the write mode of M (2), the EPROM selection signal ES of "1" is applied to one input terminal of the NAND gate (30), and the NAND gate (30) operates. In addition, the EPROM
In the predetermined area of (2), 1-bit control data "X"
"Y" is written. (5) is a reset signal to which a ▲ ▼ (reset) signal is applied, and (6) is a latch lock generation circuit, wherein the ▲ ▼ signal is applied via an inverter (7). Here, in the latch clock generation circuit (6), when the power supply voltage V _DD rises to the threshold potential of the latch clock generation circuit (6), the latch clock LCK1 is generated from the latch clock generation circuit (6), and thereafter, When the signal rises to the threshold potential of the latch clock generation circuit (6), that is, immediately before the microcomputer is released from reset, the latch clock LCK2 replaces the latch clock LCK1 and the latch clock generation circuit (6). Arises from. The reason why the latch clocks LCK1 and LCK2 are sequentially generated is to prevent erroneous selection of input / output options of the microcomputer described later. (8) is a latch circuit, which latches the control data “X” applied to the L (latch) terminal at the timing of a latch clock LCK1 applied to the T (trigger) terminal. To latch. Similarly, (9) is also a latch circuit, and the latch circuit (9) has the control data “Y” applied to the L terminal.
Are latched at the timing of the latch clock LCK2 applied to the T terminal. (10) is an AND gate, and one input terminal of the AND gate (10) is connected to the Q (output) terminal of the latch circuit (8) through an inverter (11),
The other input terminal is connected to the Q (output) terminal of the latch circuit (9). The dashed line (12) is the control circuit.

(13) is a booster circuit for boosting the power supply voltage V _DD by the threshold potential of the transistor, (14) (15) is a P-channel type connected in series between the booster circuit (13) and ground
MOS-FET (hereinafter referred to as P-MOS) and N-channel type MOS
-FET (hereinafter referred to as N-MOS) as well as (16) and (17)
P-MO connected in series between the booster circuit (13) and ground
S and N-MOS, the gates of the P-MOS (14) (16) are connected to the drains of the N-MOS (17) (15), respectively, and the gate of the N-MOS (15) is AND gate (1
0), and the gate of the N-MOS (17) is connected to the output terminal of the AND gate (10) via an inverter (18). And the P-MOS (14) (1
6) and the N-MOS (15) (17) form a level shift circuit. (19), (20) and (21) are P-MOS (first transistor), N connected in series between the power source V _DD and ground.
-MOS (third transistor) and N-MOS (second transistor), the connection point of the N-MOS (20) (21) is connected to the input / output terminal (1), The gate of (20) is connected to the drain of the N-MOS (17). (22) is an N-MOS (fourth transistor) connected between the input / output terminal (1) and ground,
The gate of (22) is connected to the Q terminal of the latch circuit (8). (23) is a power supply V _DD and the P-MOS (19)
And a P-MOS (fifth transistor) connected in parallel with the connection point of the N-MOS (20). The reason why the power supply voltage V _DD is boosted by the booster circuit (13) is as follows.
When selecting the CMOS buffer, EPROM read mode, etc. from the microcomputer, the N-MO
This is to ensure that S (20) is turned on.

(31) is an AND gate, and in a normal microcomputer output mode, an OSCSTOP signal of "0" is inverted by an inverter (34) to one input terminal of the AND gate (31). A signal is applied, and the data read from the data bus (4) is output via the AND gate (31) and the OR gate (33). At this time, the AND gate (32) described later is prohibited by the OSCSTOP signal of "0". (32)
In the read mode of the EPROM (2), the OSCSTOP signal of "1" is applied to one input terminal of the AND gate (32),
The data written in (2) will be read out via the AND gate (32) and the OR gate (33). At this time, the AND gate (31) is connected to the inverter (3
The AND gates (31) and (32) are in an exclusive relationship because the AND gates (31) and (32) are forbidden by the signal “0” (4). A multiplexer is composed of the AND gates (31) and (32) and the OR gate (33).
(24) is a NAND gate, one input terminal of which is
The output of the OR gate (33) is applied, the ▲ ▼ (enable) signal is applied to the other input terminal through the inverter (25), and the output terminal is connected to the gate of the P-MOS (19). ing. (26) is a NOR gate,
The output of the OR gate (33) is applied to one input terminal, the signal () is applied to the other input terminal, and the output terminal is connected to the gate of the N-MOS (21). . The signal ▲ ▼ is the inverted output of the output of the OR gate (33) and the NAND gate (24) and
Set to "0" when outputting from the NOR gate (26). (27) is a NAND gate (gate circuit)
The NAND gate (24) is provided at one input terminal of the ND gate (27).
Is applied via an inverter (28), and the output terminal is connected to the gate of the P-MOS (23). Also the above E
In the read mode of the PROM (2), the microcomputer outputs “0” ▲ ▼ signal and “1” OSCSTOP signal as the first signal, and “1” O as the second signal.
SCSTOP signal is generated. Then, the ▲ ▼ signal is applied to one input terminal of the NAND gate (27) through the inverter (29), and the OSCSTOP signal is applied to the NAND gate (27).
The OSCSTOP signal is applied directly to one input terminal of the latch circuit (8) (9) and the R (reset) terminal and S
Applied to the (set) terminal.

Now, the operation of the drawings will be described. Input / output options of microcomputer are open drain state, CMOS
There are buffer status and pull-down status, and EPROM
There are a write mode and a read mode as modes.

First, when the open drain state is selected as the input / output option, the control data “X” = “0” and “Y” = “0” are written in advance in a predetermined area of the EPROM (2), and “0” is input from the microcomputer. , An OSCSTOP signal of "0", a ▲ ▼ signal of "0", a microcomputer selection signal CS of "0", and an EPROM selection signal of "0". When the latch clock LCK1 is generated from the latch clock generation circuit (6), the control data “X” = “0”
Latch circuit at the timing of latch clock LCK1 (8)
, And the output signal PD of "0" is output from the Q terminal. After that, when the latch clock LCK2 is generated from the latch clock generation circuit (6), the control data “Y” = “0”
Latch circuit at the timing of latch clock LCK2 (9)
, And an output signal of "0" is output from the Q terminal. Then, the Q terminal output of the latch circuit (8) and the Q terminal output of the latch circuit (9) via the inverter (11) are applied to both input terminals of the AND gate (10) in this order,
The output signal PU of "0" is output from the AND gate (10). That is, since the values are fixed in the order of the output signals PD and PU,
The malfunction of the N-MOS (20) (22) is prevented. First, the output signal PD of "0" is applied to the gate of the N-MOS (22) to turn off the N-MOS (22). After that, the output signal PU of "0" is inverted by the inverter (18), and the ▲ ▼ of "1" is the N-MOS (1
When applied to the gate of 7), the N-MOS (17) is turned on, so the N-MOS (20) is turned off. From this NM
When the OS (20) (22) is turned off, the N-MOS (21) becomes an open drain state. Then, the data “1” output from the data bus (4) is enabled via the AND gate (31) and the OR gate (33).
When applied to 6), the N-MOS (21) turns off and the data of "0" output from the data bus (4) is AND gate (3).
When applied to the NOR gate (26) via 1) and the OR gate (33), the N-MOS (21) will turn on. As a method of using the open drain state, for example, an LED may be connected to the input / output terminal (1) and the ON / OFF state of the LED may be controlled by the data from the data bus (4).

Next, when selecting the CMOS buffer status as an input / output option, control data “X” =
“0”, “Y” = “1” is written in advance, the OSCSTOP signal of “0” from the microcomputer, ▲ of “0”
▼ Signal, "0" microcomputer selection signal C
S and EPROM selection signal ES of "0" are generated. Then, based on the control data “X” = “0” latched in the latch circuit (8) at the timing of the latch clock LCK1,
The output signal PD of "0" is output from the Q terminal. After that, based on the control data “Y” = “1” latched by the latch circuit (9) at the timing of the latch clock LCK2,
The output signal of "1" is output from the Q terminal, and the output signal PU of "1" is output from the AND gate (10). First, the output signal PD of "0" is applied to the gate of the N-MOS (22) to turn off the N-MOS (22), and then the output signal PU of "1" is changed to the N-MOS in the level shift circuit. When applied to the gate of (15), the N-MOS (15) and the P-MOS (16) are turned on, so that the boosted power supply voltage V _DD passes through the P-MOS (16) to the N-MOS (15). 20) applied to the gate of the N-MOS
(20) turns on. From this, N-MOS (20) is on, N
Since -MOS (22) and P-MOS (23) are turned off, P
A CMOS buffer state is established by the -MOS (19) and N-MOS (20) (21). Therefore, the data of "1" passes through the AND gate (31) and the OR gate (33) to the NAND gate (24).
When applied to the NOR gate (26), the P-MOS (19) is turned on and the power supply voltage V _DD , that is, "1", is input / output terminal (1).
"0" data output from the AND gate (31) and O
When applied to the NAND gate (24) and the NOR gate (26) via the R gate (33), the N-MOS (26) is turned on and "0" is output from the input / output terminal (1). Therefore, the external circuit connected to the input / output terminal (1) is controlled by the output data of "1" or "0".

Next, when selecting the pull-down state as an input / output option, control data “X” =
“1” is written in advance, and at this time, the control data “Y” may be either “1” or “0”. In addition, the OSCSTOP signal of "0" from the microcomputer, ▲ of "1"
▼ signal, "1" microcomputer selection signal CS,
And the EPROM selection signal ES of "0" is generated. Then, based on the control data “X” = “1” latched by the latch circuit (8) at the timing of the latch clock LCK1,
The output signal PD of "1" is output from the Q terminal. At this time,
The output signal PU becomes "0" regardless of the output of the latch circuit (9). First, the output signal PD of "1" is applied to the gate of the N-MOS (22) to turn on the N-MOS (22), and then the output signal PU of "0" is inverted by the inverter (18). When the output signal {circle around (1)} is applied to the gate of the N-MOS (17), the N-MOS (17) is turned on, so that the N-MOS (20) is turned off. Furthermore, "1" ▲ ▼
Since the signal is applied to the NAND gate (24) and the NOR gate (26), the NAND gate (24) and the NOR gate (26)
The P-MOS (1
9) and N-MOS (21) are turned off. From this, N-MOS (2
Only 2) turns on and enters the pull-down state. As a method of using the pull-down state, there is a method such as key scan input which handles the input / output terminal (1) as an input, and the data obtained by the key scan is internally transmitted via the NAND gate (3) and the data bus (4). Taken into the circuit.

Next, when the EPROM writing mode is selected, the ▲ ▼ signal of “1” and the OSCSTO of “1” are output from the microcomputer.
A P signal, a microcomputer selection signal CS of "0", and an EPROM selection signal ES of "1" are generated. At this time, EPROM
The control data “X” and “Y” written in (2) may be set to either “1” or “0”. And "1"
When the latch circuit (8) is reset by the OSC STOP signal of, the output signal PD of "0" is output from the Q terminal and N
Applied to the gate of the -MOS (22), the N-MOS (22) is turned off. When the latch circuit (9) is set by the OSCSTOP signal of "1", the output signal PU of "1" is output from the AND gate (10) and the N-MO in the level shift circuit is output.
It is applied to the gate of S (15), and the N-MOS (15) and P-
Since the MOS (16) turns on, the boosted power supply voltage V _DD
Turns on the N-MOS (22). However, since the P-MOS (19) (23) and the N-MOS (21) are turned off by the signal "1", the input / output terminal (1) is disabled and is in a floating state. When the data to be written to the EPROM (2) is applied to the input / output terminal (1) in this state, the data is NANDed.
It will be written to the EPROM (2) via the gate (30).

Next, when the EPROM read mode is selected, it must be taken into consideration that the output currents in the EPROM read mode and those other than the EPROM read mode differ from each other by a factor of about 2 times, for example, 400 μA and 200 μA based on the high level output voltage condition. Then, when the data is read from the EPROM (2), the "0" signal from the microcomputer and the "0" signal from the microcomputer.
A signal, an OSCSTOP signal of "1", a microcomputer selection signal CS of "0", and an EPROM selection signal ES of "0" are generated. At this time, the control data "X" and "Y" of the EPROM (2) have nothing to do with the EPROM read mode. And like the EPROM writing mode described above, N-M
The OS (22) turns off and the N-MOS (20) turns on. In this state, the data of "1" read from EPROM (2) is AND
When applied to the NAND gate (24) and the NOR gate (26) through the gate (32) and the OR gate (33), the P-MOS
(19) is turned on, the N-MOS (21) is turned off, and the output of the NAND gate (24) of "0" is applied to the NAND gate (27) via the inverter (28). MOS
(19) and (23) are turned on at the same time. Therefore, the voltage 2V _DD is output from the I / O terminal (1), and if a normal PROM writer that recognizes the output current in EPROM read mode is connected to the I / O terminal (1), the power supply voltage will be changed according to the voltage 2V _DD.
An output current twice as high as V _DD is supplied to the PROM writer,
As a result, the data "1" read from the EPROM (2) is recognized by the PROM writer. Also EP
When the data “0” read from the ROM (2) is applied to the NAND gate (24) and the NOR gate (26) through the AND gate (32) and the OR gate (33), the P-MOS ( 19) (2
3) turns off and N-MOS (21) turns on. Therefore, zero potential is output from the input / output terminal (1), and EPROM (2)
The data of "0" read from is recognized by a normal PROM writer. The EPROM read mode has been executed by both parties.

As described above, since the input / output option of the microcomputer is selected by the combination of the control data "X" and "Y" written in the predetermined area of the EPROM (2), each input / output option is simultaneously selected as in the conventional case. The malfunction can be prevented. Even if the input / output terminal (1) of the microcomputer and the data terminal of the EPROM (2) are shared, the output current in EPROM mode can be obtained by providing the P-MOS (27). Simply connect a normal PROM writer to the input / output terminal (1),
The data read from EPROM (2) can be recognized.

(G) Effect of the Invention According to the present invention, in the input / output circuit of the microcomputer with built-in EPROM, the input / output option of the microcomputer is selected by the combination of the control data written in the predetermined area of the EPROM. Therefore, the malfunction of simultaneously selecting the respective input / output options is prevented, and the respective input / output options are surely selected. Furthermore, the input / output terminals of the microcomputer and EPRO
Even if the M data terminal is shared, the output current in the EPROM mode can be obtained by providing the fifth transistor. Therefore, simply connect the normal PROM writer to the input / output terminal of the microcomputer and read from the EPROM. The output data can be recognized, and thus a new PROM writer for the EPROM built-in microcomputer, which meets the standard of the output current of the microcomputer, is not required, and the versatility is expanded.

[Brief description of drawings]

The drawing is a circuit diagram showing an input / output circuit of a microcomputer with an EPROM according to the present invention. (1) …… I / O terminal, (2) …… EPROM, (12) ……
Control circuit, (19) (23) ... P-MOS, (20) (21) (2
2) ... N-MOS, (27) ... NAND gate.

Claims (1)

[Claims] 1. A first device connected between an input / output terminal and a power supply.
A transistor; a second transistor connected between the input / output terminal and ground; and a third transistor inserted between the input / output terminal and the first transistor and connected in series with the first and second transistors. A transistor, a fourth transistor connected in parallel with the second transistor, a fifth transistor connected in parallel with the first transistor, and an input circuit for fetching input data applied to the input / output terminal into an internal circuit, EPROM in which data can be written / read and control data for controlling the third and fourth transistors is written in at least two specific areas; and the control data read from the specific areas of the EPROM. Are output after being latched at different latch timings, and the third and fourth transistors are output based on the output data. Control circuit, a first gate circuit for switching and outputting normal data or read data from the EPROM, and operating the first and second transistors based on the switching output data, and the first gate circuit A second gate circuit which operates the fifth transistor based on the output of the EPROM, and when the data is not read from the EPROM, the third and fourth gate circuits are based on the control data written in the specific area of the EPROM. The input / output terminal is set to a predetermined input / output state by controlling the transistor and controlling the first and second transistors by an output obtained from the first gate circuit based on the normal data. , Said EPRO
When data is read from M, the first and second transistors are complementarily operated by an output obtained from the first gate circuit based on the read data of the EPROM, and the first and second transistors are complementarily operated based on the read data of the EPROM. An input / output circuit of a microcomputer with built-in EPROM, characterized in that the input / output terminal is set to a data read state of the EPROM by operating the fifth transistor with an output obtained through the first and second gate circuits. .