JPH0680559B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to improving the characteristics of a sense amplifier connected to a memory transistor in this semiconductor memory device.

[Conventional technology]

This kind, the sense amplifier connected to the memory transistor is "1", "0" stored in this memory transistor
It is required to detect the contents quickly and clearly distinguish and output the detected contents of "1" and "0" as H level and L level potentials. A device shown in FIG. 2 is known as a device that fulfills such requirements. In FIG. 2, (1) has a source grounded and a gate connected to an X address line (x). N channel type FAMO
It is a memory transistor composed of S (Floating gate Avalanche injection MOS), and when H level voltage is applied to the gate, it becomes conductive if the stored content is "1", and becomes non-conductive if the stored content is "0". is there. (2) is a first Y-address transistor (2a) consisting of an enhancement-type N-channel MOSFET whose gate is connected to the first Y-address line (Y1) and whose drain is connected to the first potential point (3).
An enhancement type N having a gate connected to the second Y address line (Y2), a source connected to the drain of the memory transistor (1) and a drain connected to the source of the first Y address transistor (2a). Channel type
A Y address transistor composed of a second Y address transistor (2b) composed of a MOSFET, which constitutes the memory section (4) together with the memory transistor (1). (5) is an enhancement-type first N-channel MOSFET whose gate is connected to the first potential point (3) and whose source is grounded. (6) is a sense amplifier control signal whose gate is at L level when the sense amplifier operates. The source is connected to (8), the source is connected to the power source Vcc which becomes 5 [V] at the time of memory reading, and the drain is the first N-channel MOSFET (5).
A load element consisting of an enhancement type 1st P-channel MOSFET connected to the drain of
The detection circuit (7) is composed of the MOSFET (5). (7a) and (7b) are input terminals and output terminals of the detection circuit (7), and (9) has a gate connected to the output terminal (7b) of the detection circuit (7) and a source connected to the first potential point ( Enhancement type second N-channel MOSFET connected to 3),
(10) is an enhancement type second P-channel type whose drain is connected to the drain of the second N-channel MOSFET (9), the gate is connected to the sense amplifier control signal (8), and the source is connected to the power supply Vcc. The gate of the MOSFET (11) is connected to the output terminal (7b) of the detection circuit (7),
An output control transistor comprising an enhancement type third N-channel MOSFET having a source connected to the first potential point (3) and a drain connected to the output line (12), (13).
Is an enhancement-type third P-channel MOSFET whose source is connected to the power supply Vcc of 5 [V], whose gate is connected to the sense amplifier control signal (8), and whose drain is connected to the drain of the output control transistor (11). It is a load element consisting of the output control transistor (11) and the output circuit (1
This is what constitutes 4). The detection circuit (7), the output circuit (14), and the second N-channel MOSFET
(9) and the second P-channel MOSFET (10) constitute a sense amplifier. Further, although only one memory section (4) is connected to the first potential point (3) of the sense amplifier (15), a plurality of memory sections are connected.

In the semiconductor memory device configured as described above, when the sense amplifier control signal (8) becomes L level in the memory read state, the first and second P channel type MOSFETs (6) (10) and the load element (13) are first set. Is to be in a conducting state.

In this state, when the memory transistor (1) is selected and the memory written in the memory transistor (1) is read out, an X address line (X) for applying a memory read signal to the memory transistor (1) and When the Y address lines (Y1) and (Y2) are all at the H level and the memory transistor (1) is not selected and the memory written in the memory transistor (1) cannot be read, the X address line ( x) and at least one of the address lines (Y1) and (Y2) are at L level. Therefore, the memory content of the selected memory transistor (1) is "0".
If it is always non-conducting, there is no current flowing from the first potential point (3) to the ground portion through the Y address transistor (2) and the memory transistor (1), and the output control transistor (11) is completely non-conductive. Since it becomes conductive, the potential of the output line (12) is 5 as shown by the slant line (16) in FIG.
The H level is about 4.9 [V], which is close to the power source Vcc of [V]. By the way, when the memory content of the selected memory transistor (1) is "0" and it is always non-conductive, the output control transistor (11) becomes completely non-conductive due to the following operation. Is. For example, assuming that the potential of the first potential point (3) is the L level of the ground potential of 0 [V] in the initial state, the first N-channel MOSFET
(5) is completely non-conductive while the 1st P channel type MO
Since the SFET (6) is in the conductive state, N channel type MO
The H level close to the power source Vcc of 5 [V] is applied to the gates of the SFET (9) and the output control transistor (11), and the second N
Channel type MOSFET (9) and output control transistor (1
1) becomes conductive, which causes the potential at the first potential point (3) to rise. When the potential of the first potential point (3) rises, the first N-channel MOSFET (5) becomes conductive and the current starts to flow, so it is applied to the gates of the second N-channel MOSFET (9) and the output control transistor (11). The potential is 5 [V] power supply Vc
It becomes a potential that is lower than c by the ratio of the current amplification factors of the first P-channel MOSFET (6) and the first N-channel MOSFET (5),
On the other hand, the potential of the first potential point (3) applied to the sources of the second N-channel MOSFET (9) and the output control transistor (11) is higher than the ground potential of 0 [V] as described above. , The potential difference between the gate and the source becomes smaller than the potential difference for making the MOSFET conductive, and the second N-channel MOSFET (9) and the output control transistor (11) become non-conductive.

Next, the reading of the memory content when the memory content of the selected memory transistor is "1" will be described. In this case, since the memory transistor (1) and the Y address transistor (2) are in a conductive state, the potential of the first potential point (3) becomes L level close to the ground potential of 0 [V]. Potential is the 1st N-channel MOSFET
Applied to the gate of (5), the first N-channel MOSFET
Since (5) is non-conducting, the second N-channel MOSFET
An H-level voltage close to the power supply voltage is applied to the gates of (9) and the output control transistor (11), so that the second N-channel MOSFET (9) and the output control transistor (11) become conductive. As a result, the potential at the first potential point (3) is the second N
Channel type MOSFET (9) and second P channel type MOSFET (1
0), load element (13), and output control transistor (1
1) The electric potential is obtained by the ratio of the current amplification factors of the memory transistor (1) and the Y address transistor (2). Due to this potential, the first N-channel MOSFET (5) conducts in a state of low conductivity, and the output potential of the detection circuit (7) decreases, but the output control transistor (11) and the second N-channel MOSFET (9). Since the potential is sufficient to conduct the current, the output control transistor (11) and the first
The 2N channel type MOSFET (9) is maintained in the conductive state. In this conventional example, the potential of the output line in this state was 1.8V.

[Problems to be solved by the invention]

In the conventional semiconductor memory device as described above, the contents of "0" and "1" stored in the selected memory transistor (1) in the memory read state are changed depending on the H level and L level of the potential. The potential at the level of the output line (12) is about 1.
Since it is about 8 [V] and the potential difference with the H level potential of about 4.9 [V] is small, when noise or the like occurs, the H level and the L level are not distinguished and the selected memory transistor (1) is There was a problem that the stored contents of "0" and "1" could not be clearly shown on the output line (12).

The present invention has been made in view of the above problems, and is highly reliable in accurately indicating the contents of "0" and "1" stored in the memory transistor on the output line even if noise or the like occurs. An object is to obtain a semiconductor memory device.

[Means for Solving Problems] A semiconductor memory device according to the present invention includes a memory transistor connected between a ground potential point and a first potential point, and a memory transistor connected between a power supply potential point and an output terminal. A P-channel MOS transistor that receives a sense amplifier control signal having a binary level at its control electrode, becomes non-conductive when receiving one level of this sense amplifier control signal, and becomes conductive when it receives the other level and becomes a load element. And a detection circuit having an N-channel MOS transistor connected between the output end and the ground potential point and having a control electrode connected to the first potential point; and a control electrode connected to the output end of the detection circuit, An output control transistor formed of an N-channel MOS transistor connected between the first potential point and the output line, a load element connected between the output line and the power supply potential point, and the first Is connected between the position point and the ground potential point, N-channel type MO a control electrode connected to the control electrode of the output control transistor
And a sense amplifier having an output circuit having a level shift transistor composed of an S transistor.

[Operation] In the present invention, the level shift transistor provided in parallel with the memory transistor between the first potential point and the ground potential point functions as the first potential point and the ground potential point when the memory transistor is in the conductive state. Conducting so as to reduce the combined resistance value between the two, the L level potential output to the output line is made lower than the L level potential output to the output line when only the memory transistor in the conductive state is used. .

Further, when it is not necessary to perform the sensing operation, that is, when the first potential point and the ground potential point are not electrically connected through the memory transistor, the sense amplifier control signal is set to one level to make this sense operation. The P-channel type MOS transistor in the detection circuit which receives the amplifier control signal at the control electrode becomes non-conductive, and at this time, the potential of the first potential point is at a level at which the N-channel type MOS transistor in the detection circuit becomes conductive. Outputs a signal at approximately the ground potential to the output terminal, and the output control transistor in the output circuit that receives this signal at the control electrode becomes non-conductive, and the load element, output control transistor, and level shift start from the power supply potential point of this output circuit. There is no current flowing through the transistor to the ground potential point. Further, even if the current slightly flows from the first potential point to the ground potential point via the level shift transistor and the potential at the first potential point drops, the output end of the detection circuit and the power supply potential point are not electrically connected. Therefore, the potential of the output terminal does not rise again, and the output control transistor remains non-conductive.
No current flows from the power supply potential point to the ground potential point via the load element, the output control transistor and the level shift transistor.

Further, when the sense amplifier control signal is set to the other level and the sense amplifier is operated, the P-channel type MOS transistor in the detection circuit which receives the sense amplifier control signal at the control electrode becomes conductive and simply functions as a load. The potential output to the output end becomes the potential due to the resistance division between the P-channel MOS transistor in the detection circuit and the N-channel MOS transistor connected between the output end and the ground potential point, and the potential at the first potential point. A full swing does not occur between the ground potential and the power supply potential depending on the level of the memory cell (non-conduction or conduction of the memory cell). In this way, the amplitude of the potential at the output end is limited so that it does not fully swing.Therefore, even if the level shift transistor is added to the output end of the detection circuit and the capacity charged and discharged by the detection circuit increases, the charge and discharge charges are increased. Is smaller than a full swing, the output control transistor is operated at high speed, and when the first potential point and the ground potential point are conducted and non-conducted via the memory transistor output to the output line. The displacement between the corresponding potentials is performed at high speed.

[Embodiment] FIG. 1 is a circuit diagram of a semiconductor memory device showing an embodiment of the present invention. In the figure, (18) shows output control of a gate as a control electrode and a drain as one input / output electrode. The level shift transistor (18) is composed of one enhancement-type N-channel MOSFET connected to the gate and the source of the transistor (11) and the source of which is grounded. The level shift transistor (18) is a selected memory transistor ( When the memory content of 1) is "0" and is always non-conductive, the memory transistor (1) in the above-mentioned conventional example is used.
Is supplied to the first potential point (3) at a predetermined potential V higher than the potential of the first potential point (3) when the memory cell is in the conductive state, and the memory content of the selected memory transistor (1) is "1" and is always conductive. If it is, the memory transistor (1) in the conventional example
Is for supplying to the first potential point (3) a predetermined potential v that is lower than the potential of the first potential point (3) when V is in the conductive state, and thus lower than the predetermined potential V. The output circuit (19) is configured with the (11) and the load element (13).

The semiconductor memory device configured as described above operates as follows in the memory read state.

First, the read operation of the stored content when the stored content of the selected memory transistor (1) is “0” will be described. Now, for example, the potential of the first potential point (3) is 0 in the initial state.
Assuming that the ground potential of [V] is at the L level, this causes the first N-channel MOSFET (5) to be completely non-conductive, while the first P-channel MOSFET (6) is conductive. Therefore, the second N-channel MOSFET (9), the output control transistor (11) and the level shift transistor (18) are turned on by applying an H level close to the power supply Vcc, eg, 5v, to their gates. When conducting, the potential of the first potential point (3) causes the memory transistor (1) to be in non-conducting state.
Second N-channel MOSFET (9) and second P-channel MOSFET
(10), the load element (3), the output control transistor (11), and the potential according to the ratio of the current amplification factors of the level shift transistor (18), that is, the first N-channel MOSFET.
The potential rises to such an extent that (5) is made conductive, and this potential makes the first N-channel MOSFET (5) conductive. As a result, the second N-channel MOSFET (9), the output control transistor (11) and the level shift transistor (18) have their gates at the first N-channel MOSFET (5) and the first P-channel MO.
Potential according to the ratio of current amplification factor with SFET (6), that is, 5
The potential is much lower than the power source Vcc of [V], that is, the potential difference between this potential and the first potential point becomes smaller than the gate-source voltage for conducting the output control transistor (11). Output control transistor (11)
Becomes non-conductive. In this state, the level shift transistor (18) conducts in a state of low conductivity due to a considerably low output potential of the detection circuit (7), and the potential of the first potential point (3) is changed to the second N-channel MOSFET (9). Since the output control transistor (11) and the output control transistor (11) are non-conductive, the voltage is further lowered. Although the first N-channel MOSFET (5) conducts in a state where the conductivity is considerably low based on the decrease in the potential of the first potential point (3), the same operation as described above is repeated again, and finally the first potential is reached. The potential at the point (3) is the first when the memory transistor (1) in the above-mentioned conventional example is in the conductive state.
A predetermined potential V higher than the potential of the potential point (3) is 1.35 [V] in this embodiment, and the potential applied to the gate of the output control transistor (11) is also a predetermined potential, 2.2 [V] in this embodiment. V] and an equilibrium state is reached. As a result, the output control transistor (11) functions substantially in the same non-conducting state, and in this embodiment, the potential of the output line (2) is 5 as shown by the slant line (16) in FIG. This is an H level of about 4.9 [V], which is close to the power supply Vcc of [V].

Next, the reading of the memory content when the memory content of the selected memory transistor is "1" will be described. In this case, since the memory transistor (1) and the Y address transistor (2) are in a conductive state, the potential of the first potential point (3) becomes an L level close to the ground potential of [V], and this potential Is the 1st N-channel MOSFET
Applied to the gate of (5), the first N-channel MOSFET
Since (5) is non-conducting, the second N-channel MOSFET
The gates of (9), the output control transistor (11) and the level shift transistor (18) have an H level close to the power supply voltage.
When the level voltage is applied, the second N-channel MOSFET (9), the output control transistor (11) and the level shift transistor (18) become conductive. As a result, the potential at the first potential point (3) is at the second N-channel MOSFET (9) and the second P-type.
The potential according to the ratio of the current amplification factors of the channel type MOSFET (10), the load element (13), the output control transistor (11), the level shift transistor (18), the memory transistor (1) and the Y address transistor (2), that is, It is about 0.05 V smaller than the potential of the first potential point (3) when the memory content of the selected memory transistor (1) is "0" and is always non-conductive, and further the memory transistor (1 ) Is the conductive state, the first potential point (3)
The predetermined potential v is smaller than the potential of the above, about 1.30 [V] in this embodiment, and there is a difference of the above potential of 0.05 [V].
When the potential of 1.30 [V] is applied to the gate of the first N-channel MOSFET (5), the potential applied to the gate of the output control transistor (11) becomes about 3 [V] and the output control transistor (11). Has a gate-source potential difference of 1.7
It becomes about [V] and remains conductive. In this state, the potential of the output line (12) is the load element for the current amplification factor of the memory transistor (1), the Y address transistor (2), the output control transistor (11) and the level shift transistor (18). It becomes a potential depending on the current amplification factor ratio of (13), and this current amplification factor ratio changes due to the provision of the level shift transistor (18), and the current amplification factor of the load element (13) side is larger than that of the conventional semiconductor memory device. Since the ratio of the ratios is small, that is, the resistance between the output line (12) and the ground potential is small, the potential of the output line (12) is about 0.2 compared with the conventional one as shown by the slant line (21) in FIG.
[V] is low and the L level is about 1.6 [V], whereby the potential difference between the H level and the L level is enlarged, and the noise margin is increased.

In the above embodiment, the memory transistor (1) is FA
Although it is assumed to be a MOS transistor, any other MOS transistor may be used as long as it is in a conductive state or a non-conductive state depending on the stored contents of "0" and "1".

Further, in the above embodiment, only one level shift transistor (18) is provided, but a plurality of level shift transistors (18) may be provided.

In the above description, one memory transistor (1) is connected to one sense amplifier (15), but in a normal semiconductor memory device, one sense amplifier (15) is used. It is general that a plurality of memory transistors (1) are connected to 15), and it goes without saying that the invention described above also has the same effect in such a case.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, by providing the level shift transistor between the first potential point and the ground potential point in the sense amplifier,
When a current flows from the first potential point to the ground potential point through the memory transistor, the level shift transistor also conducts and the current flows from the first potential point to the ground potential point not only through the memory transistor but also through the level shift transistor. , The potential output to the output line becomes lower than that when only the memory transistor conducts, and appears on the output line when the current flows from the first potential point to the ground potential point through the memory transistor and when the current does not flow. Even if noise or the like occurs due to a large potential difference, the potential appearing on the output line should be clearly dealt with when the current flows from the first potential point to the ground potential point via the memory transistor and when it does not flow. Therefore, there is an effect that the reliability of the semiconductor memory device is improved.

Further, the detection circuit in the sense amplifier is connected between the power supply potential point and the output terminal, the control electrode receives the sense amplifier control signal having a binary level, and is non-conductive when receiving one level of the sense amplifier control signal. And a P-channel MOS transistor that is conductive when it receives the other level and receives a sense amplifier control signal that serves as a load element, and is connected between the output end and the ground potential point, and the control electrode is at the first potential point. By having a connected N-channel type MOS transistor, the L level signal is output to the output terminal of the detection circuit by setting the sense amplifier control signal to one level when the sensing operation is not required. , Make the output control transistor in the output circuit non-conductive, and ground from the power supply potential point through the output control transistor and the level shift transistor. An advantageous effect of reducing the current flowing through the position point.

Furthermore, by configuring the detection circuit in the sense amplifier as described above, the amplitude of the potential output from the output end of the detection circuit becomes smaller, so the output control transistor and level shift transistor operate at high speed, and the output line Since the output data changes at high speed, there is an effect that high-speed reading can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an EPROM memory unit and a sense amplifier showing an embodiment of the present invention. FIG. 2 is a circuit diagram of an EPROM memory unit and a sense amplifier showing a conventional semiconductor memory device.
The figure is a characteristic diagram showing the relationship between the potential of the output line and the power supply voltage in the conventional semiconductor memory device and one embodiment of the present invention. In the figure, (1) is a memory transistor, (11) is an output control transistor, (12) is an output line, (13) is a load element, (18) is a level shift transistor, (19) is an output circuit, ( 15) is a sense amplifier. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A memory transistor connected between a ground potential point and a first potential point, a memory transistor connected between a power supply potential point and an output terminal, and having a control electrode receiving a sense amplifier control signal having a binary level. When one of the levels of this sense amplifier control signal is received, it becomes non-conductive, and when it receives the other level, it becomes conductive and becomes a load element, and is connected between the output terminal and the ground potential point. A detection circuit having an N-channel type MOS transistor whose control electrode is connected to the first potential point, and a control electrode connected to the output terminal of the detection circuit, and connected between the first potential point and the output line. An output control transistor formed of an N-channel MOS transistor, a load element connected between the output line and a power supply potential point, and a load element connected between the first potential point and the ground potential point. And a sense amplifier having an output circuit having a level shift transistor whose control electrode is connected to the control electrode of the output control transistor and which is an N-channel MOS transistor. 2. The semiconductor memory device according to claim 1, wherein the load element of the output circuit is an enhancement type P-channel MOS transistor in which a sense amplifier control signal is applied to a control electrode. . 3. An enhancement-type N-channel MOS transistor having a control electrode connected to an output terminal of a detection circuit and one input / output electrode connected to a first potential point, and the N-channel MOS transistor. 3. A P-channel type MOS transistor, which is connected between the other input / output electrode of the transistor and the power supply and has a control electrode to which a sense amplifier control signal is applied. The semiconductor memory device described. 4. A memory transistor is an N-channel FAMO.
4. A semiconductor memory device according to claim 1, wherein the semiconductor memory device is an S transistor.