JPH0680636B2 - Liquid phase epitaxial growth method - Google Patents
Liquid phase epitaxial growth methodInfo
- Publication number
- JPH0680636B2 JPH0680636B2 JP20127383A JP20127383A JPH0680636B2 JP H0680636 B2 JPH0680636 B2 JP H0680636B2 JP 20127383 A JP20127383 A JP 20127383A JP 20127383 A JP20127383 A JP 20127383A JP H0680636 B2 JPH0680636 B2 JP H0680636B2
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial growth
- melt
- liquid phase
- temperature
- growth method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2907—Materials being Group IIIA-VA materials
- H10P14/2911—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/26—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition
- H10P14/263—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition using melted materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
- H10P14/3221—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3442—N-type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3444—P-type
Landscapes
- Led Devices (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Description
【発明の詳細な説明】 イ）産業上の利用分野 本発明は良好な特性のPn接合を有した発光ダイオードを
製造するための液相エピタキシャル成長方法に関する。TECHNICAL FIELD The present invention relates to a liquid phase epitaxial growth method for manufacturing a light emitting diode having a Pn junction with good characteristics.
ロ）従来技術 近年、発光ダイオード用の化合物半導体において、第１
図に示すようにGaAs基板（１）上に同導電型のGaAlAs層
（２）を成長させ、次いで逆導電型のGaAlAs層（３）を
積層することでPn接合（４）近傍の注入効率を高める技
術が開発されている。B) Prior art In recent years, in compound semiconductors for light emitting diodes,
As shown in the figure, by growing a GaAlAs layer (2) of the same conductivity type on the GaAs substrate (1) and then stacking a GaAlAs layer (3) of the opposite conductivity type, the injection efficiency near the Pn junction (4) can be improved. Technology to enhance is being developed.
このような発光ダイオード用の液相エピタキシャル成長
は、第２図の温度特性図に示す如く高温における時点t1
で基板と融液を接触させ、t2からt3の間第１エピタキシ
ャル成長をさせ、時刻t3において融液を逆導電型のもの
に切りかえると共に降温速度を切りかえて、その後第２
のエピタキシャル成長を行なっていた。Liquid phase epitaxial growth for such a light emitting diode is performed at a high temperature t1 as shown in the temperature characteristic diagram of FIG.
The substrate is brought into contact with the melt at, and the first epitaxial growth is performed from t2 to t3. At time t3, the melt is switched to that of the reverse conductivity type and the temperature lowering rate is switched, and then the second
Was being epitaxially grown.
この方法では時刻t3においてPn接合（４）が形成される
事になるが、ウェハは融液に対し面接触しているにもか
かわらず平面状のPn接合が得られない。即ち部分的に早
く導電型転換したり、何度も導電型転換してPnPn構造を
形成する部分が生じたりする。これらは発光効率を低下
させるのみでなく、トランジスタやサイリスタの如くス
イッチング動作を生じることになるので好ましくない。According to this method, a Pn junction (4) is formed at time t3, but a planar Pn junction cannot be obtained although the wafer is in surface contact with the melt. That is, the conductivity type may be partially changed quickly, or the conductivity type may be changed many times to form a PnPn structure. These are not preferable because they not only reduce the luminous efficiency but also cause switching operations like transistors and thyristors.
そこで実験を重ねた結果、融液中に含まれる微量のシリ
コンがGaAsやGaAlAsに対して両性不純物として働き、エ
ピタキシャル成長の際の降温速度によってＰ型不純物に
なるかｎ型不純物になるかが定まるので、融液と温度勾
配を同時に変化させると熱慣性等により部分的にＰ型と
なったりｎ型になったりするので、これが原因となる事
がわかった。一方他の化合物半導体の液相エピタキシャ
ル成長方法で用いられるPn接合付近での定温保持やメル
トバックは、Pn接合（４）前後で３元系化合物の混晶比
が変化しているので、Pn接合における混晶比が発光に最
適な値からずれる恐れがあり、特に発光層であるＰ層へ
の電流注入効率が低下しやすいのでこのましくないこと
がわかった。Therefore, as a result of repeated experiments, a trace amount of silicon contained in the melt acts as an amphoteric impurity on GaAs and GaAlAs, and it is determined whether it becomes a P-type impurity or an n-type impurity depending on the temperature decrease rate during epitaxial growth. It was found that when the melt and the temperature gradient are changed at the same time, they partially become P-type or n-type due to thermal inertia and the like, which is the cause. On the other hand, in the constant temperature maintenance and meltback near the Pn junction used in the liquid phase epitaxial growth method for other compound semiconductors, the mixed crystal ratio of the ternary compound changes before and after the Pn junction (4). It was found that the mixed crystal ratio may be deviated from the optimum value for light emission, and the efficiency of current injection into the P layer, which is the light emitting layer, is likely to decrease, which is not preferable.
ハ）発明の目的 本発明は上述の点を考慮してなされたもので、略平坦で
均一なPn接合を形成する液相エピタキシャル成長方法を
提供するものである。(C) Object of the invention The present invention has been made in consideration of the above points, and provides a liquid phase epitaxial growth method for forming a substantially flat and uniform Pn junction.
ニ）発明の構成 本発明は化合物半導体の第１のエピタキシャル成長後、
降温速度を切換える時点と融液を切換える時点を異なら
せるもので、以下本発明を実施例に基づいて詳細に説明
する。D) Structure of the invention The present invention is characterized in that after the first epitaxial growth of the compound semiconductor,
The present invention will be described in detail below with reference to examples, since the time of switching the temperature lowering rate and the time of switching the melt are different.
ホ）実施例 第３図は本発明実施例の液相エピタキシャル成長方法の
温度特性図である。以下の説明は第１図で説明したGaAs
基板上のGaAlAs発光ダイオードを例にとり、また雰囲気
ガスは特にことわらない限り水素とする。E) Example FIG. 3 is a temperature characteristic diagram of the liquid phase epitaxial growth method of the example of the present invention. The following explanation is GaAs explained in FIG.
Taking the GaAlAs light emitting diode on the substrate as an example, the atmosphere gas is hydrogen unless otherwise specified.
まずＰ型GaAs基板とＰ型融液とｎ型融液をそれぞれ分離
してセットした黒鉛製ボートを850〜900℃の高温で数十
分間定温保持したあと、第３図における時点t1において
ボートのスライド板を摺動させ、基板とＰ型融液を接触
させる。そしてただちに昇温し、基板の表面のぬれ性を
よくすると共に少し溶出させ（メルトバック）、860〜9
50℃になった時点t2において0.1〜0.8℃/minの第１の降
温速度で温度をさげ、第１のエピタキシャル成長を行い
Ｐ型GaAlAs層を形成する。そして820〜900℃に低下した
時点t3で降温速度を早め２〜５℃/minの第２の降温速度
とし、その時の温度より５〜13℃低下した時点t4で融液
をＰ型融液からｎ型融液に切換える。その後必要に応じ
て、電極のオーミック特性向上のため最後の10℃降温を
利用してGaAs表面層（５）を形成してもよい。First, the P-type GaAs substrate, the P-type melt and the n-type melt were set separately, and the graphite boat was kept at a high temperature of 850 to 900 ° C for several tens of minutes. The slide plate of 1 is slid to bring the substrate into contact with the P-type melt. Then, the temperature is raised immediately to improve the wettability of the substrate surface and to elute it a little (meltback).
At the time point t2 when the temperature reaches 50 ° C., the temperature is lowered at the first cooling rate of 0.1 to 0.8 ° C./min to perform the first epitaxial growth to form the P-type GaAlAs layer. Then, at time t3 when the temperature drops to 820 to 900 ° C, the cooling rate is accelerated to a second temperature decrease rate of 2 to 5 ° C / min, and the melt is removed from the P-type melt at time t4 when the temperature drops 5 to 13 ° C. Switch to n-type melt. Then, if necessary, the GaAs surface layer (5) may be formed by utilizing the final temperature decrease of 10 ° C. to improve the ohmic characteristics of the electrode.
このようにして成長された成長層及びPn接合は、各層の
結晶性のマッチングがよいので発光効率が高く、また微
量不純物であるシリコンはドナーかアクセプタかのいず
れか定まった導電作用を呈し、Pn接合近傍においてＰ型
となったりｎ型に反転したりすることはない。The growth layer and the Pn junction grown in this way have high light emission efficiency because the crystallinity of each layer is well matched, and silicon, which is a trace impurity, exhibits a defined conductive action as either a donor or an acceptor. It does not become P-type or invert to n-type near the junction.
この方法で製造した上述のGaAlAs発光ダイオードは例え
ば、基板と第１のエピタキシャル層との間に結晶性のマ
ッチングの悪さによるエッチングラインは見られず、Pn
接合附近におけるＰ型Ga1-xAlxAs層の混晶比ｘはおよそ
0.35で、エポキシ樹脂被覆後の発光効率は４〜５％、発
光波長660nm（赤）であった。In the above GaAlAs light emitting diode manufactured by this method, for example, an etching line due to poor crystallinity matching between the substrate and the first epitaxial layer is not observed, and Pn
The mixed crystal ratio x of the P-type Ga 1-x Al x As layer near the junction is approximately
At 0.35, the luminous efficiency after coating with the epoxy resin was 4 to 5%, and the emission wavelength was 660 nm (red).
ヘ）発明の効果 以上の如く本発明は、第１の融液を基板に接触させ第１
エピタキシャル成長させる途中に於て、第１降温速度か
ら第２降温速度に切替える。故に融液中のシリコンが第
１エピタキシャル層に対して一定の導電型不純物として
作用するので、部分的Pn反転がなくなる。また第１降温
速度より第２降温速度を速くすることにより、残った第
１の融液がPn接合付近を部分的にPn反転する前に速やか
に第２のエピタキシャル層を形成する。故に上述の２つ
の構成により、部分的Pn反転をなくし、スイッチング動
作を防止する。F) Effects of the Invention As described above, the present invention is characterized in that the first melt is brought into contact with the substrate
During the epitaxial growth, the first cooling rate is switched to the second cooling rate. Therefore, since the silicon in the melt acts as a constant conductivity type impurity on the first epitaxial layer, partial Pn inversion disappears. By making the second temperature lowering rate faster than the first temperature lowering rate, the second epitaxial layer is quickly formed before the remaining first melt partially Pn-inverts in the vicinity of the Pn junction. Therefore, the above two configurations eliminate partial Pn inversion and prevent switching operation.
第１図は本発明で対象とする発光ダイオード用の化合物
半導体の模式図、第２図は従来のエピタキシャル成長方
法の温度特性図、第３図は本発明実施例の液相エピタキ
シャル成長方法の温度特性図である。 （１）…GaAs基板、（２）（３）…GaAlAs層、（４）…
Pn接合、（５）…GaAs表面層。FIG. 1 is a schematic diagram of a compound semiconductor for a light emitting diode which is an object of the present invention, FIG. 2 is a temperature characteristic diagram of a conventional epitaxial growth method, and FIG. 3 is a temperature characteristic diagram of a liquid phase epitaxial growth method of an embodiment of the present invention. Is. (1) ... GaAs substrate, (2) (3) ... GaAlAs layer, (4) ...
Pn junction, (5) ... GaAs surface layer.
Claims (1)
保持し第１の融液と基板を接触させて第１降温速度で第
１エピタキシャル成長を行う工程と、その第１降温速度
よりも速い第２の降温速度に切替える工程と、その後に
第２の融液と基板を接触させ第２の降温速度で第２のエ
ピタキシャル成長を行う工程とを具備した事を特徴とす
る液相エピタキシャル成長方法。1. A step of holding a plurality of melts and a substrate of a compound semiconductor at a high temperature to bring the first melt and the substrate into contact with each other to perform a first epitaxial growth at a first cooling rate, and a step of performing the first epitaxial growth at a rate lower than the first cooling rate. A liquid phase epitaxial growth method comprising: a step of switching to a high second temperature lowering rate; and a step of thereafter bringing a second melt and a substrate into contact with each other to perform second epitaxial growth at a second temperature lowering rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20127383A JPH0680636B2 (en) | 1983-10-26 | 1983-10-26 | Liquid phase epitaxial growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20127383A JPH0680636B2 (en) | 1983-10-26 | 1983-10-26 | Liquid phase epitaxial growth method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6092609A JPS6092609A (en) | 1985-05-24 |
| JPH0680636B2 true JPH0680636B2 (en) | 1994-10-12 |
Family
ID=16438221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20127383A Expired - Lifetime JPH0680636B2 (en) | 1983-10-26 | 1983-10-26 | Liquid phase epitaxial growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680636B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS587052B2 (en) * | 1974-10-04 | 1983-02-08 | 三菱電機株式会社 | Liquid phase growth equipment for semiconductor crystals |
-
1983
- 1983-10-26 JP JP20127383A patent/JPH0680636B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6092609A (en) | 1985-05-24 |
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