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JPH0680680B2 - Multi-cell type transistor - Google Patents
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JPH0680680B2 - Multi-cell type transistor - Google Patents

Multi-cell type transistor

Info

Publication number
JPH0680680B2
JPH0680680B2 JP63074103A JP7410388A JPH0680680B2 JP H0680680 B2 JPH0680680 B2 JP H0680680B2 JP 63074103 A JP63074103 A JP 63074103A JP 7410388 A JP7410388 A JP 7410388A JP H0680680 B2 JPH0680680 B2 JP H0680680B2
Authority
JP
Japan
Prior art keywords
emitter
film
electrode
common electrode
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63074103A
Other languages
Japanese (ja)
Other versions
JPH01246872A (en
Inventor
伸一 伊藤
龍 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63074103A priority Critical patent/JPH0680680B2/en
Publication of JPH01246872A publication Critical patent/JPH01246872A/en
Publication of JPH0680680B2 publication Critical patent/JPH0680680B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マルチエミッタ型、メッシュエミッタ型など
のように、多数の小さいトランジスタを集合させ、各ト
ランジスタのエミッタ電極にエミッタ安定抵抗が接続さ
れたマクチセル型トランジスタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention assembles a large number of small transistors such as a multi-emitter type and a mesh emitter type, and an emitter stabilizer resistor is connected to the emitter electrode of each transistor. And a macticel transistor.

〔従来の技術〕[Conventional technology]

トランジスタの大電流化,高速スイッチング化,高周波
化のために、それぞれ微小エミッタをもつトランジスタ
を集合させたマルチセル型トランジスタの各セルのエミ
ッタに安定化抵抗を直列に接続することは公知である。
第2図は従来のマルチセル型トランジスタを示し、NPN
トランジスタのPべース層11中に設けられたN+エミッタ
層12にはシリコン基板上の酸化膜2に明けられた接続孔
3においてエミッタ引出電極4が接触している。このエ
ミッタ引出電極4は基板面上にべース引出電極6と平行
に設けられるエミッタ共通電極5と多結晶Si膜抵抗体7
を介して接続され、この結果、共通電極5と各エミッタ
との間には並列に二つの抵抗体7が安定化抵抗として接
続されることになる。
It is known that a stabilizing resistor is connected in series to the emitter of each cell of a multi-cell type transistor in which transistors each having a minute emitter are assembled in order to increase the current, the switching speed and the frequency of the transistor.
Fig. 2 shows a conventional multi-cell transistor, NPN
The emitter extraction electrode 4 is in contact with the N + emitter layer 12 provided in the P base layer 11 of the transistor in the connection hole 3 formed in the oxide film 2 on the silicon substrate. The emitter extraction electrode 4 is provided on the substrate surface in parallel with the base extraction electrode 6 and an emitter common electrode 5 and a polycrystalline Si film resistor 7 are provided.
As a result, two resistors 7 are connected in parallel as a stabilizing resistor between the common electrode 5 and each emitter.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

第2図に示す多結晶Si膜抵抗体7と電極4,5との接続は
予め絶縁膜2の上に形成した多結晶Si膜のパターンの上
にAl層蒸着して接続部で多結晶Si膜に重ねることによっ
て行われる。その結果、例えば第3図(a)の平面図に
示すように厚さ1μm程度の多結晶Si膜抵抗体7の上に
重ねられるAl共通電極5には、第3図(b)の断面図に
示すように段差部51を生ずる。各セルの小型化が進むに
つれてエミッタ共通電極5の幅Wが狭くなり、次のよう
な問題が生じてきた。
The polycrystalline Si film resistor 7 shown in FIG. 2 is connected to the electrodes 4 and 5 by depositing an Al layer on the pattern of the polycrystalline Si film previously formed on the insulating film 2 to form the polycrystalline Si film at the connection portion. It is done by stacking on a membrane. As a result, for example, as shown in the plan view of FIG. 3A, the Al common electrode 5 overlaid on the polycrystalline Si film resistor 7 having a thickness of about 1 μm has a cross-sectional view of FIG. 3B. As shown in FIG. As the miniaturization of each cell progresses, the width W of the common emitter electrode 5 becomes narrower, causing the following problems.

(1)段差部51で抵抗が発生し、エミッタ共通接続電極
5の先端部までの抵抗が大きくなり、根本部との間に電
位差が生じ、エミッタ電極の外部接続のためのボンディ
ングパットに近いセルにおいて破壊が生ずる。
(1) A resistance is generated in the step portion 51, the resistance up to the tip of the common emitter connecting electrode 5 is increased, and a potential difference is generated between the emitter common electrode 5 and the root portion. Destruction occurs at.

(2)過電流の流れた際に、段差部51が溶断する。(2) When the overcurrent flows, the step portion 51 is melted.

(3)エレクトロマイグレーションによる障害が起こり
やすく、信頼度を低下させる。
(3) Failure due to electromigration is likely to occur and reliability is lowered.

本発明の課題は、上記の問題を解消してエミッタに直列
に接続される抵抗体としての多結晶Si膜と外部接続のた
めの共通電極との接続部に段差が生じないマルチセル型
トランジスタを提供することにある。
An object of the present invention is to solve the above problems and provide a multi-cell transistor in which a step is not generated in a connecting portion between a polycrystalline Si film as a resistor connected in series to an emitter and a common electrode for external connection. To do.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記の課題を解決するために、本発明は、一つの半導体
基板に複数のエミッタ領域を有し、各エミッタ領域にオ
ーム性接触する電極にそれぞれ一端が接触する抵抗膜の
他端を覆って外部接続のためのエミッタ共通電極が設け
られるマルチセル型トランジスタにおいて、各抵抗膜は
共通電極の基板側の面に接する連結部を有する膜の一部
分であるものとする。
In order to solve the above-mentioned problems, the present invention has a plurality of emitter regions on one semiconductor substrate, and covers the other end of a resistance film whose one end is in contact with an electrode in ohmic contact with each emitter region In a multi-cell transistor provided with an emitter common electrode for connection, each resistance film is assumed to be a part of a film having a connecting portion in contact with the surface of the common electrode on the substrate side.

〔作用〕[Action]

エミッタに直列接続される抵抗膜はエミッタ共通電極の
下部で終わっておらず、接続電極の下部にある連結部と
共に形成されているので、抵抗膜と共通電極との接続部
には段差が生じない。
The resistance film connected in series with the emitter does not end below the common electrode of the emitter, but is formed with the connecting part below the connection electrode, so there is no step at the connection between the resistance film and the common electrode. .

〔実施例〕〔Example〕

第1図は本発明の一実施例を示し、第2図,第3図と共
通の部分には同一の符号が付されている。この実施例で
は、絶縁膜2の上に成膜した多結晶Si膜のパターニング
の際、第2図に示したようにエミッタ引出電極3に接続
される抵抗体として働く部分7とそれらを連結する部分
70とを一体に形成する。従ってその上にAlの蒸着パター
ニングで積層される共通電極5には段差が生ずることが
ない。第4図は別の実施例を示すし、第1図では、多結
晶Si膜連結部70を共通電極5が覆っていたのに対し、こ
の実施例では、多結晶Si膜連結部70が共通電極の幅Wよ
り広い幅で形成されているので、その一部分が露出して
いる。
FIG. 1 shows an embodiment of the present invention, in which the same parts as those in FIGS. 2 and 3 are designated by the same reference numerals. In this embodiment, when patterning the polycrystalline Si film formed on the insulating film 2, as shown in FIG. 2, they are connected to the portion 7 acting as a resistor connected to the emitter extraction electrode 3. part
70 and 70 are integrally formed. Therefore, no step is formed on the common electrode 5 laminated thereon by vapor deposition patterning of Al. FIG. 4 shows another embodiment. In FIG. 1, the common electrode 5 covers the polycrystalline Si film connecting portion 70, whereas in this embodiment, the polycrystalline Si film connecting portion 70 is common. Since it is formed with a width wider than the width W of the electrode, a part thereof is exposed.

上記の実施例では抵抗体を、多結晶シリコン膜で形成し
たが、他の材料、例えば金属膜を用いた抵抗体の場合に
も本発明を実施することができる。
Although the resistor is formed of a polycrystalline silicon film in the above-mentioned embodiments, the present invention can be implemented in the case of a resistor using another material, for example, a metal film.

〔発明の効果〕〔The invention's effect〕

本発明によれば、マルチセル型トランジスタの各エミッ
タに直列接続される抵抗体と接続され、大電流が流れる
共通電極の抵抗体との接続部に生ずる段差が、各抵抗体
を形成する膜を共通電極の下面に接する連結部と一体に
することによって解消でき、共通電極のステップカバレ
ージの問題は解決される。これにより、共通電極の断線
あるいは共通電極における電位差の発生が、工程の増
加,複雑化を必要とすることなく防止でき、信頼性の高
いマルチセル型トランジスタを容易に製造できる。
According to the present invention, the step formed at the connection portion of the common electrode, which is connected to the resistor connected in series to each emitter of the multi-cell type transistor and through which a large current flows, is common to the films forming each resistor. This can be solved by being integrated with the connecting portion that contacts the lower surface of the electrode, and the step coverage problem of the common electrode can be solved. As a result, disconnection of the common electrode or occurrence of a potential difference in the common electrode can be prevented without increasing the number of steps and complicating, and a highly reliable multi-cell transistor can be easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例のエミッタ安定抵抗体とエミ
ッタ共通電極の接続部の平面図、第2図は従来のマルチ
セル型トランジスタの一例の斜視図、第3図(a),
(b)は従来のマルチセル型トランジスタの安定化抵抗
とエミッタ共通電極の接続部を示し、(a)が平面図,
(b)が(a)のA-A線断面図、第4図は本発明の別の
一実施例の同様な接続部の平面図である。 4……エミッタ引出電極、5……エミッタ共通電極、7
……多結晶Si膜抵抗体、70……多結晶Si膜連結部。
FIG. 1 is a plan view of a connecting portion between an emitter stabilizing resistor and an emitter common electrode according to an embodiment of the present invention, FIG. 2 is a perspective view of an example of a conventional multi-cell transistor, FIG. 3 (a),
(B) shows a connecting portion between a stabilizing resistor and a common emitter electrode of a conventional multi-cell transistor, (a) is a plan view,
(B) is a cross-sectional view taken along the line AA of (a), and FIG. 4 is a plan view of a similar connection portion of another embodiment of the present invention. 4 ... Emitter extraction electrode, 5 ... Emitter common electrode, 7
...... Polycrystalline Si film resistor, 70 ...... Polycrystalline Si film connection part.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一つの半導体基板に複数のエミッタ領域を
有し、各エミッタ領域にオーム性接触する電極にそれぞ
れ一端が接触する抵抗膜の他端を覆って外部接続のため
の共通電極が設けられるものにおいて、各抵抗膜が共通
電極の基板側の面に接する連結部を有する膜の一部分で
あることを特徴とするマルチセル型トランジスタ。
1. A semiconductor substrate is provided with a plurality of emitter regions, and a common electrode for external connection is provided by covering the other end of a resistive film, one end of which contacts each electrode that makes ohmic contact with each emitter region. A multi-cell transistor, wherein each resistance film is a part of a film having a connecting portion in contact with the surface of the common electrode on the substrate side.
JP63074103A 1988-03-28 1988-03-28 Multi-cell type transistor Expired - Fee Related JPH0680680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63074103A JPH0680680B2 (en) 1988-03-28 1988-03-28 Multi-cell type transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63074103A JPH0680680B2 (en) 1988-03-28 1988-03-28 Multi-cell type transistor

Publications (2)

Publication Number Publication Date
JPH01246872A JPH01246872A (en) 1989-10-02
JPH0680680B2 true JPH0680680B2 (en) 1994-10-12

Family

ID=13537518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63074103A Expired - Fee Related JPH0680680B2 (en) 1988-03-28 1988-03-28 Multi-cell type transistor

Country Status (1)

Country Link
JP (1) JPH0680680B2 (en)

Also Published As

Publication number Publication date
JPH01246872A (en) 1989-10-02

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