JPH0680715B2 - Probe card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention utilizes a part of an IC manufacturing method to inspect an IC chip to be highly densified, and uses the pad of the IC chip. The present invention relates to a probe card in which a bump group corresponding to the group and a connection bump group corresponding to the tester side are formed and an alignment window portion is provided.

<Prior Art> When manufacturing a semiconductor product, for example, an IC chip, when inspecting an IC chip in a wafer state at the final stage of the previous process, a stylus as shown in FIGS. 10 and 11 respectively. A probe card d is used which is composed of an inspection needle group mainly composed of a and a substrate c made of an epoxy resin mainly composed of a transmission line b group connected to the inspection needle group.

The probe card d is connected to a tester g by a board c, a mother board e holding the board c, and a connector f connected thereto.

A plurality of stylus a are provided in the central portion of the substrate c, and the stylus a is protruded below the substrate c and fixed by an insulator h such as epoxy resin. The stylus a is further connected to the mother board e by the electric line b and the pin i group. Through the electric power transmission path of, and is led to the connector f and the tester g.

The IC chip j is placed at a predetermined position on the movable table, and the movable table is moved to sequentially feed the IC chip j, and each stylus a and each pad of the IC chip j are associated with each other for electrical measurement. I do.

<Problems to be Solved by the Invention> In recent years, the trend toward higher density of IC chips has increased, and accordingly, the number of pins (the number of pads) has been increasing. Correspondingly, in order to inspect the IC chip, it is necessary to increase the number of probe needles on the probe card.

At present, we are devising the diameter and arrangement of the stylus, but there is a limit to increasing the number of stylus, which is a bottleneck in the manufacture of IC chips and the like.

Also, the higher the density, the greater the problem of the stylus tip. For example, displacement of the stylus as the diameter of the stylus decreases, wear resistance, deformation of the stylus, shorting between stylus due to adhesion of aluminum dust, maintenance of flatness of the entire stylus, damage to IC pad by stylus, durability However, problems such as stability will arise.

Furthermore, the biggest problem is that all the assembling work of these stylus of the probe card is done by hand, and the X, Y, Z of the stylus tip is
It is an absolute condition that various precisions such as three-dimensional position, overall flatness, wear resistance, maintenance of electric characteristics, etc. are required, and a great deal of effort is required.

In addition, it is very difficult to align the IC chip with the probe card and maintain the card performance at the work site of the IC maker.

In the present invention, in order to solve the above problems, a bump group corresponding to a pad and a bump corresponding to a measurement terminal are formed on a semiconductor chip by utilizing an IC chip manufacturing method without using a stylus. It is an object of the present invention to provide a probe card in which a group is formed, an alignment window portion is provided on a semiconductor chip, and a transmission line and a compensation circuit are wired.

<Means for Solving the Problems> The above object of the present invention can be achieved by the following configurations.
That is, the gist thereof is that a group of bumps corresponding to pads of a wafer chip are projected by etching on a semiconductor substrate made of p-type or n-type silicon or the like in which a taper portion is formed on the peripheral line portion or one end side thereof. Form it, and add valence to the bump group +
3. A probe characterized in that an impurity for reducing the resistance value of 3 or atoms +5 is injected, a transmission path is further arranged in the bump group, and the resistance value is made large on the other surface of the substrate by an oxide film or the like. .A wafer by etching on a card and a semiconductor substrate such as a p-type in which a taper portion is formed on the peripheral line portion or one end side thereof, or a p-type or an n-type silicon portion having a taper portion formed at one end side thereof by etching・ A bump group corresponding to a chip pad and a bump group corresponding to a tester terminal are separately formed in a protruding manner, and an impurity for reducing the resistance value of valence +3 or valence +5 is injected into each bump group. In addition, an appropriate electric transmission path is arranged between the bump group corresponding to the wafer chip and the bump group corresponding to the tester terminal, and the other surface of the semiconductor substrate is covered with an oxide film or the like. 3. The probe card according to claim 1, wherein the resistance value is large, and a compensation circuit for high-frequency countermeasures is further wired on the semiconductor substrate in the transmission path. It's a card.
4. The probe card according to claim 1, 2 or 3, wherein a positioning window portion is provided so as to penetrate substantially in the center of the semiconductor substrate. Further, a polarization prism is provided in the positioning window portion. A probe card according to claim 4, wherein a wide-angle lens such as a fisheye lens is attached. The probe card according to claim 4, wherein an inspection lens using an optical fiber is mounted in the alignment window portion.

<Examples and Functions> The probe card according to the present invention will be described in detail below with reference to the drawings showing the examples.

Example 1 FIGS. 1 (a), (b), (c), and (d) are end face explanatory views showing the manufacturing process of Example 1 of the present invention.

That is, (1) is a p-type impurity-doped single crystal silicon substrate having a tapered portion (2) formed on its peripheral edge, and a wafer chip pad is formed on the single crystal silicon substrate (1). A group of bumps (3) designed to be on the same position is formed by an etching method. This etching method includes a wet etching method and a dry etching method. The wet etching method is mainly performed using hydrofluoric acid. Further, the dry etching method uses an activated gas, and the bump group is formed by the wet etching method in this embodiment, but the dry etching method may be used for forming the bump group.

Next, on the bumps (3) formed by the above etching,
In order to reduce the resistance value, an acceptor impurity having a valence of +3 or a donor impurity having a valence of +5 is introduced. Typical valence +3 impurities used include boron, aluminum, indium, and gallium, and valence +5 impurities include arsenic, antimony, and
Phosphorus is used.

In this embodiment, a p-type silicon substrate (1) is used to implant an n-type impurity (4) having a valence of +5 into the bump (3) group. As a method of introducing the n-type impurity (4), there are a thermal diffusion method and an ion implantation method, and either method can be used.

Then, as shown in (c) and FIG. 2 in FIG. 1, a wiring in which a metal transmission path (5) (for example, aluminum) is vapor-deposited on the silicon substrate (1) from the bump (3) group by vacuum vapor deposition or the like. The pattern is formed up to the end of the tapered portion (2) on the silicon substrate (1).

Further, a compensating circuit (6) as a countermeasure against high frequency (noise) is wired in the metal transmission line (5), and this compensating circuit (6) prevents high frequency influence on other transmission lines (5). It can be resolved. That is, the compensation circuit (6)
As, between transmission lines (5), (5), or transmission line (5)
The equivalent circuit is wired on the silicon substrate (1). The surface of the silicon substrate (1) other than the power transmission path (5) and the compensation circuit (6) is made to have a large resistance value by an oxide film or the like.

Example 2 FIGS. 3 (a), (b), (c) and (d) are end face explanatory views showing the manufacturing process of Example 2 of the present invention.

That is, (1) is a P-type impurity-doped single crystal silicon substrate in which a taper portion (2) is formed on the peripheral green portion, and a wafer chip is formed on the lower surface of the single crystal silicon substrate (1). On the upper surface of the above-mentioned silicon substrate (1) and a group of bumps (3) designed to have the same position at the pad position of
A group of bumps (3) 'designed to be in the same position as the terminals on the tester side is formed by an etching method.

Next, in order to lower the resistance value, the bumps (3) and (3) ′ group have acceptor impurities of valence + 3 or valence +
No. 5 donor impurity is introduced. In the present embodiment, by using the p-type silicon substrate (1), the bumps (3) and (3) 'groups have n-type impurities (valence +5). 4) is introduced.

Then, as shown in FIGS. 3D, 4 and 5, respectively, a group of bumps (3) corresponding to the pads of the wafer chip and a bump corresponding to the connection terminals on the tester side are formed by vacuum deposition or the like. Correspondingly, appropriate transmission lines (5) are formed between the (3) 'group and the silicon substrate (1) on the lower surface.

Further, a compensating circuit (6) for preventing high frequency generation (noise) is wired in the electric transmission line (5), and the compensating circuit (6) prevents a high frequency influence on other electric transmission lines (5). It can be resolved.

Further, on the silicon substrate (1) other than the bumps (3), (3) 'group and the transmission path (5), impurities for increasing the resistance value are introduced to increase the resistance value between the lines. To

In forming the taper portion (2) on the peripheral portion of the silicon substrate (1) in the first and second embodiments, when drawing a wiring circuit on the silicon substrate (1), the circuit is drawn by light. Therefore, it is easier to draw an inclined surface than a flat surface,
Also, since the object to be measured is a flat surface, a certain level difference is required. Further, when the silicon substrate (1) is connected to the mother board side, it is desirable that the terminal side thereof is formed thin.

Therefore, the shapes of the silicon substrate (1) shown in FIGS. 6 (a), (b), (c), and (d) are considered.

Example 3 FIGS. 7 (a) and 7 (b) respectively show a state in which an alignment window portion (7) is installed in the center of the silicon substrate (1) shown in the present Example 1 and Example 2. is there. Therefore, the group of bumps (2) and (2) 'is formed so as to project from the peripheral portion of the alignment window portion (7), and the bump (3) and the IC chip are formed from the alignment window portion (7). The contact state with a pad (not shown) is confirmed.

Next, FIG. 8 (a) shows a state in which the polarizing prism (8) is installed in the alignment window portion (7), and FIG.
The fisheye lens (9) is mounted in the alignment window (7) so that the contact state can be observed in a wider range than in the small alignment window (7). Further, FIG. 9 shows a structure in which an inspection lens (10) using an optical fiber is mounted in the alignment window (7) so that the contact state between the bump (3) and the pad can be enlarged and observed remotely. is there.

In the present invention having the above structure, the silicon substrate (1)
The bumps (3) are held downward and the bumps (3) 'are held upward, indirectly or directly in a state of being electrically connected to the connection terminals on the tester side. And proper positioning of the movable table on which the IC chip is mounted (X, Y and O
By making an angle, the appropriate pressure contact between the pad (not shown) of the IC chip and the bumps (3) group is observed and confirmed from inside the alignment window (7),
It is brought into a conducting state, and is conducted to the connection terminal on the tester side from the bump (3) 'group or directly from the electric transmission path (5) through the electric transmission path (5), and the electric characteristic test of the IC chip is performed. .

<Effects of the Invention> As described above, according to the present invention, by forming a bump group and a transmission path on a silicon substrate, it is possible to achieve a significant miniaturization of the probe card itself, and
With the alignment protrusion, the contact state with the pad can be observed, and reliable and high-density multi-pin can be realized. Also X / Y
-The Z position accuracy is accurate, and the flatness of the bump group is increased by forming the taper part, and it is possible to freely attach an electric circuit to the taper part surface without damaging the IC pad. Become.

Therefore, the possibility of automation is brought about by greatly simplifying the manufacture of the probe card, and not only a single chip but also a large number of chips at the same time may be processed. It is possible to inspect,
It has various effects such as a reduction in manufacturing cost and an increase in inspection efficiency.

[Brief description of drawings]

1 (a), (b), (c), and (d) are explanatory views showing the manufacturing process of the probe card of Example 1 of the present invention, respectively.
2 is a plan explanatory view of Embodiment 1 of the present invention, FIG. 3 (a),
(B), (c), and (d) are explanatory views showing the manufacturing process of the probe card of the second embodiment of the present invention, FIG. 4 is a plan view showing the bump group on the wafer chip side, and FIG. Plane explanatory view showing the bump group on the tester side, FIG.
(B), (c), and (d) are perspective views showing various shapes of the silicon substrate, respectively, and FIGS. 7 (a) and (b) are sectional explanatory views of Embodiment 3 of the present invention and FIG. 8 (a), respectively. ), Example 3
Fig. 8 is an explanatory view when a polarizing prism is attached to the alignment window portion, Fig. 8 (b) is an illustration diagram when a fisheye lens is attached to the alignment window portion, and Fig. 9 is an optical fiber in the alignment window portion. And FIG. 10 and FIG. 11 are explanatory diagrams showing a conventional example when the inspection lens is attached according to FIG. In the figure, (1): Silicon substrate (2): Tapered part (3) ', (3): Bump group (4): Impurity for decreasing resistance value (5): Transmission path (6): Compensation circuit (7): Alignment window (8): Polarizing prism (9): Fisheye lens (10): Optic lens

Claims (6)

[Claims] 1. A bump group corresponding to a pad of a wafer chip is projected by etching on a semiconductor substrate made of p-type or n-type silicon or the like having a taper portion formed on its peripheral line portion or one end side. The bump group has a valence +
3. A probe characterized in that an impurity for reducing the resistance value of 3 or atoms +5 is injected, a transmission path is further arranged in the bump group, and the resistance value is made large on the other surface of the substrate by an oxide film or the like. ·card. 2. A bump group and a tester corresponding to a pad of a wafer chip by etching on a semiconductor substrate made of p-type or n-type silicon or the like having a taper portion formed on a peripheral line portion or one end side thereof. Bump groups corresponding to the terminals are separately formed by projection, and the respective bump groups are implanted with impurities for reducing the resistance value of valence +3 or valence +5, and the bumps corresponding to the above-mentioned wafer chip are further formed. A probe card characterized in that an appropriate electric transmission path is arranged between the group and the bump group corresponding to the tester terminal, and the resistance value on the other surface of the semiconductor substrate is increased by an oxide film or the like. 3. A compensation circuit for high frequency measures is provided in the transmission line,
The probe card according to claim 1 or 2, wherein the probe card is wired on a semiconductor substrate. 4. An alignment window portion is provided so as to extend through substantially the center of the semiconductor substrate.
The listed probe card. 5. The probe card according to claim 4, wherein a polarizing prism or a wide-angle lens such as a fisheye lens is mounted in the alignment window portion. 6. The probe card according to claim 4, wherein an inspection lens made of an optical fiber is mounted in the alignment window portion.