JPH0680796B2 - Internal power supply voltage generation circuit for semiconductor integrated circuits - Google Patents
Internal power supply voltage generation circuit for semiconductor integrated circuitsInfo
- Publication number
- JPH0680796B2 JPH0680796B2 JP60098519A JP9851985A JPH0680796B2 JP H0680796 B2 JPH0680796 B2 JP H0680796B2 JP 60098519 A JP60098519 A JP 60098519A JP 9851985 A JP9851985 A JP 9851985A JP H0680796 B2 JPH0680796 B2 JP H0680796B2
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- Japan
- Prior art keywords
- potential
- circuit
- power supply
- point
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Control Of Electrical Variables (AREA)
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は，半導体集積回路において，この回路に供給
する外部電源に基づいて外部電源電位より低い電位であ
る内部電源電位を発生する内部電源電圧発生回路に関す
るものである。The present invention relates to an internal power supply voltage for generating an internal power supply potential lower than the external power supply potential based on an external power supply supplied to this circuit in a semiconductor integrated circuit. It relates to a generation circuit.
この種の内部電源電圧発生回路としては第３図に示すよ
うに，外部電源が供給される電源電位点（１）と接地電
位点との間に抵抗（２）と抵抗（３）とを直列接続し，
これらの接続点（４）から内部電源電圧V1を得る抵抗分
割が一般的である。As shown in FIG. 3, an internal power supply voltage generating circuit of this type has a resistor (2) and a resistor (3) connected in series between a power supply potential point (1) to which an external power source is supplied and a ground potential point. connection,
A resistance division is generally used to obtain the internal power supply voltage V 1 from these connection points (4).
しかるに，この様に構成された内部電源電圧発生回路に
あつては，電源電位点（１）から接地電位点へ常に抵抗
（２）及び抵抗（３）を介して電流が流れており、常に
電力が消費されているものである。そこで，この消費電
力を少なくすべく，抵抗（２）（３）の抵抗値を高くす
ると，出力端である接続点（４）の出力インピーダンス
が高くなり，接続点（４）から大電流が取り出せないと
いう問題を有するものであつた。つまり，消費電力を少
なくすると，出力インピーダンスが高くなり，出力イン
ピーダンスを低くすると消費電力が大きくなるという相
矛盾する問題点を有するものであつた。However, in the internal power supply voltage generation circuit configured as described above, current always flows from the power supply potential point (1) to the ground potential point through the resistors (2) and (3), and the power is always supplied. Is consumed. Therefore, if the resistance values of the resistors (2) and (3) are increased in order to reduce this power consumption, the output impedance of the connection point (4), which is the output terminal, increases, and a large current can be taken out from the connection point (4). It had the problem of not having it. That is, there is a contradictory problem that the output impedance increases when the power consumption is reduced and the power consumption increases when the output impedance is reduced.
この発明は上記した点に鑑みてなされたものであり，消
費電力が少なく，かつ出力インピーダンスの低い半導体
集積回路の内部電源電圧発生回路を得ることを目的とす
るものである。The present invention has been made in view of the above points, and an object thereof is to obtain an internal power supply voltage generation circuit of a semiconductor integrated circuit that consumes less power and has a lower output impedance.
この発明に係る半導体集積回路の内部電源電圧発生回路
は，基準電位発生回路からの基準電位よりＮチヤンネル
MOSトランジスタの閾値電圧分高い第１電位を出力する
第１レベルシフト回路と，上記基準電位よりＰチヤンネ
ルMOSトランジスタの閾値電圧分低い第２電位を出力す
る第２レベルシフト回路と，第１レベルシフト回路から
の第１電位がゲートに入力されるＮチヤンネルMOSトラ
ンジスタと，第２レベルシフト回路からの第２電位がゲ
ートに入力されるＰチヤンネルMOSトランジスタとを備
え,NチヤンネルMOSトランジスタとＰチヤンネルMOSトラ
ンジスタとの接続点を内部電源出力端としたものであ
る。The internal power supply voltage generating circuit of the semiconductor integrated circuit according to the present invention has an N channel based on the reference potential from the reference potential generating circuit.
A first level shift circuit that outputs a first potential that is higher than the threshold voltage of the MOS transistor, a second level shift circuit that outputs a second potential that is lower than the reference potential by the threshold voltage of the P-channel MOS transistor, and a first level shift The circuit includes an N-channel MOS transistor whose gate receives the first potential from the circuit and a P-channel MOS transistor whose gate receives the second potential from the second level shift circuit. The N-channel MOS transistor and the P-channel MOS transistor are provided. The connection point with the transistor is used as the output terminal of the internal power supply.
この発明においては，第１レベルシフト回路から第１電
位によりＮチヤンネルMOSトランジスタが導通・非導通
状態を制御され，第２レベルシフト回路からの第２電位
によりＰチヤンネルMOSトランジスタが導通・非導通状
態を制御され,NチヤンネルMOSトランジスタとＰチヤン
ネルMOSトランジスタとの接続点に基準電位発生回路か
らの基準電位と同一電位の内部電源電位が出力されるこ
とになるものである。In the present invention, the N-channel MOS transistor is controlled to be conductive / non-conductive by the first potential from the first level shift circuit, and the P-channel MOS transistor is conductive / non-conductive by the second potential from the second level shift circuit. The internal power supply potential of the same potential as the reference potential from the reference potential generation circuit is output to the connection point between the N channel MOS transistor and the P channel MOS transistor.
以下にこの発明の一実施例を第１図に基づいて説明す
る。第１図はCMOS回路からなる半導体集積回路に適用さ
れた内部電源電圧発生回路を示すものであり，図におい
て（５）は電源電位点（１）と第１ノード（７）との間
に接続された高抵抗の第１抵抗，（６）は上記第１ノー
ド（７）と接地電位点との間に接続された高抵抗の第２
抵抗で，上記第１抵抗（５）とで基準電位発生回路
（８）を構成しており，この実施例においては第１抵抗
（５）と第２抵抗（６）の抵抗値を同じにして第１ノー
ド（７）に電源電位VCCの1/2の電位である基準電位を発
生しているものである。（９）は上記電源電位点（１）
と第２ノード（11）との間に接続された上記第1,第２抵
抗（５）（６）よりも高い抵抗値の抵抗，（10）は上記
第２ノード（11）と第１ノード（７）との間に接続さ
れ，ゲートが第２ノード（11）に接続されたＮチヤンネ
ルMOSトランジスタで，上記抵抗（９）とで第１レベル
シフト回路（12）を構成しているものであり，第２ノー
ド（11）に第１ノード（７）の電位にＮチヤンネルMOS
トランジスタ（10）の閾値電圧VTH（Ｎ）分高い電位，
つまり （Ｎ）なる第１電圧を発生しているものである。（13）
は上記第１ノード（７）と第３ノード（15）との間に接
続され，ゲートが第３ノード（15）に接続されたＰチヤ
ンネルMOSトランジスタ，（14）は上記第３ノード（1
5）と接地電位点との間に接続された第１及び第２抵抗
（５）（６）よりも高い抵抗値の抵抗で，上記Ｐチヤン
ネルMOSトランジスタ（13）とで第２レベルシフト回路
（16）を構成しているものであり，第３ノード（15）に
第１ノード（７）の電位にＰチヤンネルMOSトランジス
タ（13）の閾値電圧VTH（Ｐ）分低い電位，つまり なる第２電圧を発生しているものである。（17）は上記
電源電位点（１）と内部電源出力端（19）との間に接続
され，ゲートが上記第１レベルシフト回路（12）の出力
端である第２ノード（11）に接続されたＮチヤンネルMO
Sトランジスタ，（18）は上記内部電源出力端（19）と
接地電位点との間に接続され，ゲートが上記第２レベル
シフト回路（16）の出力端である第３ノード（15）に接
続されたＰチヤンネルMOSトランジスタである。An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows an internal power supply voltage generation circuit applied to a semiconductor integrated circuit composed of a CMOS circuit. In the drawing, (5) is connected between the power supply potential point (1) and the first node (7). The high resistance first resistor (6) is a high resistance second resistor connected between the first node (7) and the ground potential point.
A reference potential generating circuit (8) is constituted by the resistor and the first resistor (5). In this embodiment, the resistance values of the first resistor (5) and the second resistor (6) are made the same. A reference potential which is half the power supply potential V CC is generated at the first node (7). (9) is the power supply potential point (1)
Connected between the second node (11) and the second node (11) and having a resistance value higher than that of the first and second resistors (5) and (6), and (10) is the second node (11) and the first node. An N-channel MOS transistor connected between (7) and the gate of which is connected to the second node (11), which constitutes the first level shift circuit (12) with the resistor (9). Yes, the N-channel MOS is connected to the potential of the first node (7) on the second node (11).
Potential higher by the threshold voltage V TH (N) of the transistor (10),
That is The first voltage of (N) is generated. (13)
Is a P-channel MOS transistor whose gate is connected to the third node (15) and is connected between the first node (7) and the third node (15), and (14) is the third node (1
A resistor having a higher resistance value than the first and second resistors (5) and (6) connected between 5) and the ground potential point, and the second level shift circuit (P-channel MOS transistor (13)). 16), which is lower than the potential of the first node (7) at the third node (15) by the threshold voltage V TH (P) of the P channel MOS transistor (13), that is, The second voltage is generated. (17) is connected between the power supply potential point (1) and the internal power supply output terminal (19), and the gate is connected to the second node (11) which is the output terminal of the first level shift circuit (12). N Channel MO
The S transistor (18) is connected between the internal power output terminal (19) and the ground potential point, and the gate is connected to the third node (15) which is the output terminal of the second level shift circuit (16). P-channel MOS transistor.
次に，この様に構成された内部電源電圧発生回路の動作
について説明する。まず，初期状態において，基準電位
発生回路（８）の第１ノード（７）に なる基準電位が発生する。一方,NチヤンネルMOSトラン
ジスタ（10）が導通状態でありわずかに電流が流れ，第
２ノード（11）が なる第１電位で安定するとともに,PチヤンネルMOSトラ
ンジスタ（13）が導通状態であり，わずかに電流が流
れ，第３ノード（15）が なる第２電位で安定することになる。そして，第１電位
がＮチヤンネルMOSトランジスタ（17）のゲートに印加
され，第２電位がＰチヤンネルMOSトランジスタ（18）
のゲートに印加されるため，両MOSトランジスタ（17）
（18）は５極管領域で動作することになる。その結果,N
チヤンネルMOSトランジスタ（17）により，内部電源出
力端（19）の電位V0は にされ,PチヤンネルMOSトランジスタ（18）により，内
部電源出力端（19）の電位V0は にされ，両MOSトランジスタ（17）（18）による内部電
源端子（９）の電位V0は同じVCCにされるため安定状態
になる。この時，両MOSトランジスタ（17）（18）は導
通状態と非導通状態のぎりぎりの状態となつているた
め，電源電位点（１）から接地電位点への両MOSトラン
ジスタ（17）（18）を介しての電流は零となる。また，
第１レベルシフト回路（12）のＮチヤンネルMOSトラン
ジスタ（10）及び第２レベルシフト回路（16）のＰチヤ
ンネルMOSトランジスタ（13）も導通状態と非導通状態
のぎりぎりの状態となつているため，両MOSトランジス
タ（10）（13）を介して流れる電流も零である。さらに
第１及び第２抵抗（５）（６）の抵抗値を高いものとし
てあるため，電源電位点（１）から接地電位点への第１
及び第２抵抗（５）（６）を介して流れる電流もわずか
となり，消費電流の削減が図れるものである。Next, the operation of the internal power supply voltage generating circuit configured as described above will be described. First, in the initial state, the first node (7) of the reference potential generation circuit (8) Then, a reference potential is generated. On the other hand, the N-channel MOS transistor (10) is in the conductive state, a slight current flows, and the second node (11) Is stable at the first potential, and the P-channel MOS transistor (13) is in the conductive state, a slight current flows, and the third node (15) Will be stable at the second potential. Then, the first potential is applied to the gate of the N-channel MOS transistor (17) and the second potential is applied to the P-channel MOS transistor (18).
Applied to the gate of both MOS transistors (17)
(18) will operate in the pentode region. As a result, N
Due to the channel MOS transistor (17), the potential V 0 of the internal power output terminal (19) is The P-channel MOS transistor (18) controls the potential V 0 of the internal power output terminal (19). Then, the potential V 0 of the internal power supply terminal (9) by both MOS transistors (17) and (18) is set to the same V CC , so that it becomes stable. At this time, since both MOS transistors (17) (18) are in a bare state of conduction and non-conduction, both MOS transistors (17) (18) from the power supply potential point (1) to the ground potential point The current through is zero. Also,
Since the N-channel MOS transistor (10) of the first level shift circuit (12) and the P-channel MOS transistor (13) of the second level shift circuit (16) are also in a bare state of conduction and non-conduction. The current flowing through both MOS transistors (10) (13) is also zero. Further, since the resistance values of the first and second resistors (5) and (6) are high, the first value from the power supply potential point (1) to the ground potential point is increased.
Also, the current flowing through the second resistors (5) and (6) becomes small, and the current consumption can be reduced.
そして，内部電源出力端（19）に負荷が接続され，負荷
の動作により，内部電源端子（19）の電位V0が より高くなると,PチヤンネルMOSトランジスタ（18）の
ドレイン電位が高くなり,PチヤンネルMOSトランジスタ
（18）が導通状態となつて，内部電源出力端（19）の電
位V0を に戻すように働くことになる。この間,NチヤンネルMOS
トランジスタ（17）のドレイン・ソース間電圧は小さく
なるため,NチヤンネルMOSトランジスタ（17）は非導通
状態のままであり，電源電位点（１）から接地電位点へ
両MOSトランジスタ（17）（18）を介して流れる電流は
零である。また，内部電源出力端（19）の電位V0が より低くなると,NチヤンネルMOSトランジスタ（17）の
ソース・ドレイン電圧が大きくなるので,NチヤンネルMO
Sトランジスタ（17）が導通状態となつて，内部電源端
子（19）の電位V0を に戻すように働くことになる。この間,PチヤンネルMOS
トランジスタ（18）のドレイン・ソース間電圧は小さく
なるため,PチヤンネルMOSトランジスタ（18）は非導通
状態のままであり，電源電位点（１）から接地電位点へ
両MOSトランジスタ（17）（18）を介して流れる電流は
零である。この様に，内部電源出力端（９）の電位V0が をずれると,NチヤンネルMOSトランジスタ（17）又はＰ
チヤンネルMOSトランジスタ（18）が直ちに導通状態に
なつて に戻すように働くので，充分低い出力インピーダンスを
得ることができ，しかも両MOSトランジスタ（17）（1
8）を介して電源電位点（１）から接地電位点へ流れる
電流がなく，余分な消費電力の発生がないものである。Then, a load is connected to the internal power supply output terminal (19), and the potential V 0 of the internal power supply terminal (19) is changed by the operation of the load. When it becomes higher, the drain potential of the P channel MOS transistor (18) becomes higher, the P channel MOS transistor (18) becomes conductive, and the potential V 0 of the internal power supply output terminal (19) becomes higher. Will work to return to. During this time, N channel MOS
Since the drain-source voltage of the transistor (17) becomes small, the N-channel MOS transistor (17) remains non-conducting, and both MOS transistors (17) (18) from the power supply potential point (1) to the ground potential point. ), The current flowing through it is zero. In addition, the potential V 0 of the internal power output terminal (19) is When the voltage becomes lower, the source / drain voltage of the N channel MOS transistor (17) increases, so the N channel MO transistor (17) increases.
When the S-transistor (17) becomes conductive, the potential V 0 of the internal power supply terminal (19) is Will work to return to. During this time, P channel MOS
Since the drain-source voltage of the transistor (18) becomes small, the P-channel MOS transistor (18) remains non-conducting, and both MOS transistors (17) (18) from the power supply potential point (1) to the ground potential point. ), The current flowing through it is zero. In this way, the potential V 0 of the internal power output terminal (9) is If deviated, N channel MOS transistor (17) or P
The channel MOS transistor (18) immediately becomes conductive. Since it works so as to restore the output current to a low level, it is possible to obtain a sufficiently low output impedance, and both MOS transistors (17) (1
There is no current flowing from the power supply potential point (1) to the ground potential point via 8), and no extra power consumption occurs.
第２図は，この発明の他の実施例を示したものであり，
第１図に示した実施例のものの基準電位発生回路（８）
を，電源電位点（１）と接地電位点との間に接続された
第１及び第２抵抗（５）（６）と，電源電位点（１）と
接地電位点との間に接続された第３及び第４抵抗（20）
（21）とで構成し，かつ，第１ノード（７）に発生する
電位と第２ノード（22）に発生する電位とが等しくなる
ように，第１〜第４抵抗（５）（６）（20）（21）の抵
抗値を設定してあるものである。そして，第１ノード
（７）が第１レベルシフト回路（12）のＮチヤンネルMO
Sトランジスタ（10）のソースに接続され，第２ノード
（22）が第２レベルシフト回路（16）のＰチヤンネルMO
Sトランジスタ（13）のドレインが接続されるものであ
る。FIG. 2 shows another embodiment of the present invention,
Reference potential generating circuit (8) of the embodiment shown in FIG.
Are connected between the power supply potential point (1) and the ground potential point, and the first and second resistors (5) and (6) connected between the power supply potential point (1) and the ground potential point. Third and fourth resistors (20)
(21), and the first to fourth resistors (5) and (6) so that the potential generated at the first node (7) and the potential generated at the second node (22) become equal. The resistance values of (20) and (21) are set. The first node (7) is the N channel MO of the first level shift circuit (12).
The second node (22) is connected to the source of the S transistor (10) and the second node (22) is connected to the P channel MO of the second level shift circuit (16).
The drain of the S transistor (13) is connected.
この様に構成された内部電源電圧発生回路も第１図に示
した実施例と同様な効果を奏するものである。The internal power supply voltage generating circuit configured as described above also has the same effect as that of the embodiment shown in FIG.
なお，上記実施例においては，基準電位発生回路（８）
からの基準電位を，第１及び第２抵抗（５）（６）の抵
抗値を同じにして としたが，これに限られるものではなく，任意な値の基
準電位に設定できるものである。つまり，第１の抵抗
（５）の抵抗値をR1,第２抵抗（６）の抵抗値をR2とす
れば，基準電圧は となるものである。この時，内部電源出力端（19）の電
位も になるものである。In the above embodiment, the reference potential generating circuit (8)
The reference potential from the same resistance value of the first and second resistors (5) and (6) However, the present invention is not limited to this, and the reference potential can be set to an arbitrary value. That is, if the resistance value of the first resistor (5) is R 1 and the resistance value of the second resistor (6) is R 2 , the reference voltage is It will be. At this time, the potential of the internal power output terminal (19) is also It will be.
この発明は以上に述べたように，基準電位発生回路から
の基準電位よりＮチヤンネルMOSトランジスタの閾値電
圧分高い第１電位を出力する第１レベルシフト回路と，
上記基準電位よりＰチヤンネルMOSトランジスタの閾値
電圧分低い第２電位を出力する第２レベルシフト回路
と，第１レベルシフト回路からの第１電位がゲートに印
加されるＮチヤンネルMOSトランジスタと，第２レベル
シフト回路からの第２電位がゲートに印加されるＰチヤ
ンネルMOSトランジスタとを備え,NチヤンネルMOSトラン
ジスタとＰチヤンネルMOSトランジスタとの接続点を内
部電源出力端としたので，低消費電力化が図れ，かつ出
力インピーダンスを低くできるという効果を有するもの
である。As described above, the present invention provides the first level shift circuit for outputting the first potential higher than the reference potential from the reference potential generation circuit by the threshold voltage of the N channel MOS transistor,
A second level shift circuit that outputs a second potential lower than the reference potential by the threshold voltage of the P channel MOS transistor, an N channel MOS transistor to which the first potential from the first level shift circuit is applied to the gate, and a second It has a P-channel MOS transistor to which the second potential from the level shift circuit is applied to its gate, and the connection point between the N-channel MOS transistor and the P-channel MOS transistor is used as the internal power supply output terminal, thus achieving low power consumption. In addition, the output impedance can be lowered.
第１図はこの発明の一実施例を示す回路図，第２図はこ
の発明の他の実施例を示す回路図，第３図は従来の内部
電源電圧発生回路を示す回路図である。 図において（１）は電源電位点，（５）は第１抵抗，
（６）は第２抵抗，（８）は基準電位発生回路，（12）
は第１レベルシフト回路，（16）は第２レベルシフト回
路，（17）はＮチヤンネルMOSトランジスタ，（18）は
ＰチヤンネルMOSトランジスタ，（19）は内部電源出力
端である。 なお，各図中同一符号は同一又は相当部分を示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional internal power supply voltage generating circuit. In the figure, (1) is the power supply potential point, (5) is the first resistance,
(6) is a second resistor, (8) is a reference potential generating circuit, (12)
Is a first level shift circuit, (16) is a second level shift circuit, (17) is an N channel MOS transistor, (18) is a P channel MOS transistor, and (19) is an internal power supply output terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (4)
てこの電源電位より低い基準電位を発生する基準電位発
生回路，この基準電位発生回路の出力端と上記電源電位
点との間に接続され，上記基準電位よりＮチヤンネルMO
Sトランジスタの閾値電圧分だけ高い第１電位を出力す
る第１レベルシフト回路，上記基準電位発生回路の出力
端と上記接地電位点との間に接続され、上記基準電位よ
りＰチヤンネルMOSトランジスタの閾値電圧分だけ低い
第２電位を出力する第２レベルシフト回路，上記電源電
位点と内部電源出力端との間に接続され，ゲートが上記
第１レベルシフト回路の出力端に接続されて第１電位が
印加されるＮチヤンネルMOSトランジスタ，上記接地電
位点と内部電源出力端との間に接続され，ゲートが上記
第２レベルシフト回路の出力端に接続されて第２電位が
印加されるＰチヤンネルMOSトランジスタを備えた半導
体集積回路の内部電源電圧発生回路。1. A reference potential generating circuit connected between a power source potential point and a ground potential point to generate a reference potential lower than the power source potential, and between an output end of the reference potential generating circuit and the power source potential point. It is connected to the N channel MO from the above reference potential.
A first level shift circuit that outputs a first potential that is higher than the threshold voltage of the S transistor, is connected between the output terminal of the reference potential generation circuit and the ground potential point, and has a threshold value of the P channel MOS transistor that is higher than the reference potential. A second level shift circuit that outputs a second potential lower by a voltage, connected between the power supply potential point and the internal power supply output end, and has a gate connected to the output end of the first level shift circuit to form a first potential N-channel MOS transistor to which is applied, a P-channel MOS transistor which is connected between the ground potential point and the output terminal of the internal power supply, and whose gate is connected to the output terminal of the second level shift circuit to which the second potential is applied. An internal power supply voltage generation circuit of a semiconductor integrated circuit including a transistor.
位点との間に直列接続された高抵抗の第１及び第２の抵
抗からなり，第１抵抗と第２抵抗との接続点に基準電位
が現われるものであることを特徴とする特許請求の範囲
第１項記載の半導体集積回路の内部電源電圧発生回路。2. The reference potential generating circuit comprises high resistance first and second resistances connected in series between a power supply potential point and a ground potential point, and a connection point between the first resistance and the second resistance. 2. The internal power supply voltage generation circuit for a semiconductor integrated circuit according to claim 1, wherein a reference potential appears at.
点との間に直列接続された高抵抗の第１及び第２の抵抗
と，電源電位点と接地電位点との間に直列接続された高
抵抗の第３及び第４の抵抗とからなり，第１抵抗と第２
抵抗との接続点及び第３抵抗と第４抵抗との接続点に同
じ電位の基準電位が現われ，第１抵抗と第２抵抗との接
続点に第１レベルシフト回路が接続され，第３抵抗と第
４抵抗との接続点に第２レベルシフト回路が接続される
ものであることを特徴とする特許請求の範囲第１項記載
の半導体集積回路の内部電源電圧発生回路。3. A reference potential generating circuit, wherein high resistance first and second resistors are connected in series between a power supply potential point and a ground potential point, and a series connection between a power supply potential point and a ground potential point. A high resistance third and a fourth resistance, and the first resistance and the second resistance
The reference potential of the same potential appears at the connection point between the resistance and the connection point between the third resistance and the fourth resistance, and the first level shift circuit is connected at the connection point between the first resistance and the second resistance. 2. The internal power supply voltage generation circuit for a semiconductor integrated circuit according to claim 1, wherein a second level shift circuit is connected to a connection point between the second resistor and the fourth resistor.
端と電源電位点との間に接続された抵抗と，この回路の
出力端と基準電位発生回路の出力端との間に接続され，
ゲートがこの回路の出力端に接続されたＮチヤンネルMO
Sトランジスタとからなるものであり、第２レベルシフ
ト回路は，この回路の出力端と接地電位点との間に接続
とれた抵抗と，この回路の出力端と基準発生回路の出力
端との間に接続され，ゲートがこの回路の出力端に接続
されたＰチヤンネルMOSトランジスタとからなるもので
あることを特徴とする特許請求の範囲第１項ないし第３
項のいずれかに記載の半導体集積回路の内部電源電圧発
生回路。4. The first level shift circuit is connected between a resistor connected between the output terminal of this circuit and a power supply potential point, and between the output terminal of this circuit and the output terminal of the reference potential generating circuit. ，
N channel MO whose gate is connected to the output of this circuit
The second level shift circuit comprises an S-transistor and a resistor connected between the output terminal of this circuit and the ground potential point, and between the output terminal of this circuit and the output terminal of the reference generation circuit. 4. A P-channel MOS transistor having a gate connected to the output terminal of this circuit, and a gate connected to the output terminal of the circuit.
13. An internal power supply voltage generation circuit for a semiconductor integrated circuit according to any one of items.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098519A JPH0680796B2 (en) | 1985-05-07 | 1985-05-07 | Internal power supply voltage generation circuit for semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098519A JPH0680796B2 (en) | 1985-05-07 | 1985-05-07 | Internal power supply voltage generation circuit for semiconductor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61255048A JPS61255048A (en) | 1986-11-12 |
| JPH0680796B2 true JPH0680796B2 (en) | 1994-10-12 |
Family
ID=14221898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60098519A Expired - Lifetime JPH0680796B2 (en) | 1985-05-07 | 1985-05-07 | Internal power supply voltage generation circuit for semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680796B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2780674B2 (en) * | 1995-06-20 | 1998-07-30 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51149777A (en) * | 1975-06-12 | 1976-12-22 | Seiko Epson Corp | Electronic circuit |
-
1985
- 1985-05-07 JP JP60098519A patent/JPH0680796B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61255048A (en) | 1986-11-12 |
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|---|---|---|---|
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Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
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