JPH0680807B2 - Gate array LSI device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array LSI device, and more particularly to a memory circuit having a built-in memory circuit and clipping the input terminal and the like of the memory circuit to a predetermined power supply voltage. The present invention relates to an LSI device capable of changing the circuit capacity and circuit configuration.

(Prior Art) A gate array LSI device is an integrated circuit in which basic cells such as basic gate circuits are arranged in an array and wiring between the basic cells is designed by computer processing according to a logic circuit specified by a customer. It is a device.

Conventionally, such a gate array LSI device is provided with a memory circuit block configured by a dedicated circuit pattern different from the basic cell in addition to the logic circuit block configured by the basic cell, and the logic circuit is configured by using the memory circuit. It was possible to integrate the circuit that operates into an LSI.

However, in such a conventional gate array LSI device, the capacity and the circuit configuration of the memory circuit are fixedly set, and an arbitrary bit and word configuration, an arbitrary control circuit, and a read / write operation of multiple ports. Since it is impossible to realize arbitrary circuit configurations and functions such as, there is a disadvantage that the degree of freedom in logic design of the gate array device is considerably limited.

(Problems to be Solved by the Invention) In view of the above-mentioned problems in the conventional type, the present invention provides a gate array LSI device having a built-in memory circuit so that an input terminal or the like of the memory circuit portion can be clipped to a predetermined voltage. Based on this concept, the memory array capacity and circuit configuration can be set as desired.
The purpose is to improve the degree of freedom in the logic design of the device.

(Means for Solving the Problems) According to the present invention, a basic cell row including a pair of P-channel transistors and N-channel transistors arranged in parallel, in which a plurality of basic cells each having the same element pattern are arranged, A memory configured with a logic block having a pair of high-potential-side and low-potential-side power supply lines fixedly arranged so as to vertically cross the basic cell column, and a memory-specific circuit pattern different from that of the basic cell A block and a wiring drawn from a diffusion region of the P-channel transistor or the N-channel transistor in the basic cell, to which the high-potential-side power supply line or the low-potential-side power supply line is connected, The memory block is connected to an address input of a part of the memory block via a wiring region for interconnecting the memory block. A gate array LSI device is provided which operates as a memory having a capacity smaller than its maximum capacity.

(Operation) According to the present invention, by using the above-described configuration, the input terminal such as the address buffer of the memory circuit can be easily clipped to the power supply voltage in the gate array LSI device including the memory circuit. Therefore, it is possible to realize various functions such as free setting of the storage capacity of the memory circuit, control method, etc. or read / write operation of a plurality of ports. That is, various circuit configurations and functions can be easily changed and set in the memory circuit built in the gate array LSI device, so that the degree of freedom in logic design can be greatly improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a layout of each circuit on a semiconductor chip of a gate array LSI device according to one embodiment of the present invention.
In the figure, 1 and 2 are random access memories,
Memory circuits 3 and 4 such as a read-only memory are basic cell columns provided in the input circuit sections of the memory circuits 1 and 2, respectively, and these elements constitute a memory block. Reference numeral 5 is a basic cell, and these basic cells 5 are arranged in a matrix to form a logic block. An input / output buffer 6 is arranged around these memory blocks and logic blocks.

Further, 7,8,9,10,11,12 are power lines arranged on the respective basic cells, and the power lines 7,10,12 are, for example, 0, respectively.
Power supply V _SS of V is supplied, and power supply lines 8, 9 and 11 are each 5 V
It supplies the power supply V _DD . Also, the power lines 7,8,11,
12 is composed of, for example, the first layer of aluminum wiring,
The power supply lines 9 and 10 are composed of a second layer aluminum wiring formed on the first layer aluminum wiring. And
Circuits such as the basic cell 5 are formed below the first layer aluminum wiring.

In the above-mentioned configuration, the wiring between each basic cell in the logic block and between the basic cell and the memory block is determined by the automatic wiring process based on the logic circuit diagram presented by the customer or the like, and has a desired configuration. A gate array LSI device is manufactured. In this case, the input terminal of each memory circuit in the memory block is clipped to a predetermined logic level to realize a memory having an arbitrary number of bits, words, or an arbitrary control circuit, or two independent memory circuits. It is possible to arbitrarily change the memory configuration such as implementation of the memory circuit. For example, a memory having a desired number of words or bits can be configured by clipping a part of input terminals of an address buffer provided in a memory block in advance to logic "0" or "1". In the present invention, two methods are used to clip the input terminals of the memory block.

One of them is a method of clipping the input terminal of a desired basic cell in the basic cell rows 3 and 4 provided in the input part of the memory circuit to a predetermined potential.

The other one is a method in which some basic cells in the logic block are so-called stack gates and the output of the stack gates is connected to a desired input terminal of the memory block as shown in FIG. The stack gate is
This is a basic cell that outputs a predetermined potential by connecting the output terminal of the basic cell to a power supply line or the like. In addition,
In this case, as shown in FIG. 2, the basic cell rows 3 and 4 such as the input section of each memory circuit are omitted and the outputs of the stack gates 13 and 14 are directly connected to the dedicated pattern of each memory circuit. Good.

FIG. 3 shows details near the memory block of the gate array LSI device shown in FIG. In the figure, the memory circuit 1
Is a memory cell array 15, a sense amplifier 16, a write amplifier 17, a word address register 18, and a word decoder 1.
9 and a control circuit 20. Further, a basic cell column 3 for an input circuit is provided on, for example, one side of the memory circuit 1, and between the memory circuit 1 and the input / output buffer 6 and between the basic cells 5 of the logic block. Wiring area
21 are provided.

In FIG. 3, each signal circuit of the memory circuit 1 is connected to another circuit, for example, the basic cell 5 in the logic block or the input / output buffer 6 via the basic cell included in the basic cell column 3. Various signals are input to and output from the memory circuit 1 through the wirings thus connected. For example, an address signal is input to the word address register 18 as indicated by an arrow A in the figure, write data is input to the write amplifier 17 as indicated by an arrow B, and the sense amplifier 16 is input as indicated by an arrow C. Read data is output. A control signal such as a clock signal and a write enable signal is input to the control circuit 20 including a clock buffer and various control signal circuits, as indicated by an arrow D.

In the memory circuit as described above, the memory cell array 15
For example, it is assumed that a memory cell of 64 words and 10 bits is prepared in advance. In this case, the word address is 6
The number of bits, write amplifiers 17 and sense amplifiers 16 is 10, respectively. When such a memory circuit is used with 32 words and 8 bits, for example, it is necessary to set the word address to 5 bits and the number of write amplifiers 17 and sense amplifiers 16 to 8, respectively. Therefore, as indicated by the hatched lines in FIG. 3, one of the basic cells of the input circuit connected to the word address register 18 and each of the input terminals of the two basic cells connected to the two write amplifiers are connected to, for example, a logic "0". Clip to. Alternatively, regardless of the basic cell of the memory circuit 1, a part of the basic cell in the logic block is used as a stack gate, and the output of the stack gate is connected to a predetermined input terminal of the memory circuit 1 so that the memory capacity as described above is increased. It is also possible to make changes. In this case, the basic cell column 3 of the memory circuit 1 can be omitted as described above.

FIG. 4 (a) is a plan view showing the configuration of each of the basic cells described above, and FIG. 4 (b) is a sectional view taken along line IV-IV in FIG. 4 (a). In these figures, the range of the width L is a region forming one basic cell, and the P channel transistor part and the N channel transistor part are included in this region. In the P-channel transistor section, P ⁺ -type diffusion layers 23, 24, 25 are formed on the N-type semiconductor substrate 22.
Is formed. 26 and
Reference numeral 27 denotes a gate metal layer that constitutes a gate electrode, respectively, and these gate metal layers are integrated with the gate electrode of the N-channel transistor section. Also 28 and 29
Are N ⁺ type basic contact regions connected to the substrate 22, respectively. The N-channel transistor portion has P ⁺ type diffusion layers 31, 32 and 33 formed on the P type well 30 and P ⁺ type substrate contact regions 34 and 35.

In such a basic cell, power supply lines 36 and 37 are arranged across the P-channel transistor section and the N-channel transistor section, respectively. The power supply line 36 supplies a power supply V _{DD of,} for example, 5V, and the power supply line 37 is For example, 0V power supply V
Supply _SS . The power supply line 36 is connected to the N ⁺ type substrate contact regions 28 and 29 and the P ⁺ type diffusion layer 24 via contact holes 38, 39 and 40, respectively. Further, the power supply line 37 is connected to the P ⁺ type substrate contacts 41 and 42 and the N ⁺ type diffusion layer 32.
And contact holes 41, 42 and 43, respectively. Therefore, in the P-channel transistor section, the source, that is, the P ⁺ type diffusion layer 24 is connected to the power source V _DD.
Two P-channel transistors connected to each other are formed, and in the N-channel transistor part, two transistors whose source, that is, the N ⁺ type diffusion layer 32 is connected to the power supply V _SS are formed. The P ⁺ type diffusion layers 23 and 25 are respectively the N ⁺ type diffusion layers 31 and 33 and the aluminum wirings 44 and
A CM formed by a P-channel transistor and an N-channel transistor having a common gate electrode in one basic cell because they are connected with each other.
Two sets of IS inverters will be included.

Further, as shown in FIG. 4A, the gate metal layer 26 is connected to the N ⁺ type substrate contact 28 by the aluminum wiring 46, for example, and the substrate contact 28 is connected to the power supply line 36. The input terminals of the inverter with the common gate metal layer 26 are clipped to the power supply V _DD . Further, since the gate metal layer 27 is connected to the P ⁺ type substrate contact 35 by the aluminum wiring 47 in the N-channel transistor part, the input terminal of the inverter having the gate metal layer 27 as a common gate electrode is clipped to the power supply V _SS . Has been done. By such a method, the input terminal of the basic cell can be accurately clipped to the predetermined potential with the shortest wiring. Even when the input terminal of the memory circuit or the like is clipped to a predetermined potential, the input terminal of the basic cell provided in the input section of the memory circuit can be clipped by such a method.

Further, when such a basic cell is used as a stack gate, as shown in FIG. 5, the power supply line V _DD or V _SS and the output terminal are connected on the grid in the basic cell. That is, as shown in the figure, the contact hole A is formed between the power supply line V _DD or V _SS formed by the first layer wiring and the output terminal formed by the second layer wiring indicated by the dotted line.
Or connect by B. By connecting the output terminal of such a stack gate to the input terminal or the like of the memory circuit, the input terminal can be clipped to a predetermined potential.

FIG. 6 shows one row of wirings of the basic cell row provided in the input part of the memory circuit shown in FIGS. 1 and 3. In the figure, the ranges of L ₁ , L ₂ , L _3, etc. respectively correspond to the range of L shown in FIG. 4A, that is, the area of one basic cell. The gate metal layer in each basic cell is shown by a single line, which is different from the case of FIG. 4 (a). Then, the basic cell in the part of L ₁ is used as a CMOS inverter, and the basic cell in the range of L ₂ has an input terminal of the power supply V _DD.
Is clipped, the basic cell of the range of L ₃ is input power
Clipped to V _SS .

FIG. 7 shows a circuit 1 of the input section of the memory circuit in FIG.
A circuit around a word address register as a column is shown.
In the circuit shown in the figure, an inverter serving as an input buffer
An address register portion 49, which is constituted by a basic cell as shown in FIG.
Are formed by a dedicated pattern of the memory circuit.
With such a configuration, the input terminal of the inverter 48 can be clipped to the predetermined potential by the method described above. In addition,
In FIG. 7, the address register portion is a flip-flop circuit 50, 51, transfer gates 52, 53, and each inverter 5
It is composed of 4,55,56 etc.

As described above, according to the present invention, in a gate array LSI device having a memory circuit, desired input terminals of the memory circuit can be accurately clipped to a predetermined potential by automatic wiring processing. Since the memory configuration can be freely changed by wiring, the degree of freedom in logic design can be greatly improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are plan views showing the arrangement of each circuit on a semiconductor chip of a gate array LSI device according to an embodiment of the present invention, and FIG. 3 is the device of FIG. 4 is an enlarged view showing details of a memory circuit portion in FIG. 4, FIG. 4 (a) is a plan view showing an example of a basic cell used in each gate array LSI device of FIGS. 1 to 3, and FIG. 4B is a sectional view taken along the line IV-IV in FIG. 4A, FIG. 5 is a plan view showing the structure of the stack gate, and FIG. 6 is provided at the input part of the memory circuit in the device of FIG. And FIG. 7 is a block circuit diagram showing a circuit configuration near an address register used in a memory circuit in the device of FIG. 1,2: Memory circuit, 3,4: Basic cell row, 5: Basic cell, 6: Input / output buffer, 7,8,9,10,11,12,36,37: Power line, 13,14: Stack Gate, 15: memory cell array, 16: sense amplifier, 17: write amplifier, 18: word address register,
19: word address decoder, 20: control circuit, 21: wiring region, 22: N type semiconductor substrate, 23, 24, 25: P ⁺ type diffusion layer, 26, 27:
Gate metal layer, 28, 29: N ⁺ type substrate contact region, 30: P type well, 31, 32, 33: N ⁺ type diffusion layer, 34, 35: P ⁺ type substrate contact region, 38, 39, 40, 41,42,43: Contact hole, 44,4
5,46,47: Aluminum wiring, 48,54,55,56: Inverter, 49: Address register block, 50,51: Flip-flop, 52,53: Transfer gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoaki Tanabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP-A-58-210638 (JP, A) JP-A-59-55519 (JP, A) JP-A-59-24492 (JP, A)

Claims (1)

[Claims] 1. A juxtaposed P-channel transistor and N.
A basic cell row including a pair of channel transistors, in which a plurality of basic cells each having the same element pattern are arranged,
A logic block having a pair of high-potential-side and low-potential-side power supply lines that are fixedly arranged so as to vertically cross the basic cell row; and a memory configured with a memory-specific circuit pattern different from that of the basic cell. And a wiring drawn from a diffusion region of the P-channel transistor or the N-channel transistor in the basic cell, to which the high-potential-side power supply line or the low-potential-side power supply line is connected, The memory block operates as a memory having a capacity smaller than its maximum capacity by being connected to a part of the address inputs of the memory block via a wiring region for interconnecting the memory blocks. Gate array LSI device.