JPH0681026B2 - Capacitive load drive circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-based capacitive load drive circuit, and more particularly to a capacitive load drive circuit with a low voltage consumption and a fast response.

[Conventional technology]

The conventional capacitive load drive circuit is a linear IC by Yojiro Yokoi.
As described in Practical Circuit Manual, Radio Technology Co., Ltd., 1980, page 105, SEPP (single end push-pull) is used after the differential amplifier to perform power amplification, and the SEPP output is negatively fed back to the differential amplifier. I was connected to the voltage follower. However, sufficient consideration was not given to the circuit scale, dynamic range, and power consumption.

[Problems to be solved by the invention]

In the above-mentioned prior art, since SEPP is used, the rising and falling speeds of the output are fast, but a level shifter is required between the bases of the two complementary transistors in order to fill the on-voltage of the complementary transistors in the output stage. Furthermore, it is necessary to insert a resistor between the output emitters to prevent shoot-through current. Therefore, there is a problem that the circuit scale and power consumption increase.
Also, if the level shifter is not inserted, there is no problem of shoot-through current, but if the gain of the differential amplifier is not sufficiently increased, the output error will be large and not only will the design conditions become strict, but the on-state voltage of the differential amplifier will increase. It is necessary to widen the dynamic range, which increases power consumption. Furthermore, there is a problem that a very large amount of current flows when the output changes, and the output is affected through the power supply line.

The present invention provides a capacitive load drive circuit suitable for driving a capacitive load such as a liquid crystal display device which has low power consumption, a fast rise and fall speed, and a small peak current when an output changes. With the goal.

[Means for solving problems]

The purpose of the above is to short-circuit and eliminate the resistance between the level shifter between the inputs of the two transistors forming the SEPP and the output, and instead to insert a low current source in parallel with the output, and to collect the collector of at least one of the transistors forming the SEPP. It is achieved by inserting a current limiting circuit between the positive side and the negative side power source.

[Action]

Since the level shifter between the inputs of the two transistors of SEPP is removed, one of the transistors is always cut off, and there is no concern that a through current will flow. Therefore, a through-current limiting resistor between the outputs is not required, and the circuit scale and power consumption can be reduced.

Further, since the level shifter between the inputs is removed and a low current source is inserted between the output terminal and the positive or negative power source, normally only one transistor works as an emitter follower and the other is cut off. Then, the other transistor is turned on only when the input signal is large and the emitter follower changes to the cutoff direction, thereby promoting the charging and discharging of the load capacitance. Then, when charging and discharging of the load capacity progresses, it cuts off again. In this state, the two transistors of SEPP are both cut off, and the output has an error with respect to the input.

After that, the charge and discharge of the load capacity is continued only by the current source of the emitter follower, and finally the output error is corrected.

Here, the output error at the time when the two transistors of SEPP are both cut off is determined by the sum of the on-voltage of both transistors and the gain of the differential amplifier, and is usually a small value. Does not take long. In addition, when one of the SEPP transistors is turned on, charge and discharge are rapidly promoted. Since the load voltage is finally given by the emitter follower, the dynamic range of the differential amplifier does not have to include the ON voltage of the two transistors of SEPP, and it is possible to reduce the power supply voltage and power consumption because it is the minimum necessary. be able to.

A current limiting circuit can be provided between the collector of at least one of the transistors forming the SEPP and the power source on the positive side or the negative side to prevent an adverse effect due to the peak current when the output changes.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention.
This is applied to the output buffer amplifier for liquid crystal display device composed of OSFET. In the figure, 2 is a differential amplifier,
SEPP is composed of NMOSFETs and PMOSFETs 3 and 5, respectively. Reference numeral 8 is a load capacity, that is, the capacity of the drain bus. Reference numerals 40 and 41 are NMOSFETs and constant voltage sources, respectively, both of which constitute a constant current source. Also, NMOSFET 70 and constant voltage source 71 and PMOSFET 60 and voltage source
Each 61 also constitutes a current limiting circuit. The output of the differential amplifier is input to the two MOSFETs 3 and 5 that constitute SEPP, and SEPP
The output of is completely negatively fed back to the differential amplifier 2 to form a voltage follower. Here, if the ON voltage of NMOSFET 3 and PMOSFET 5 (gate-source voltage at which drain current starts to flow) is Vth _N (gate voltage for source) and Vth _P (source voltage for gate), in order to prevent shoot-through current, Must satisfy the following equation.

Vth _N + Vth _P ＞ 0 This output buffer amplifier is NM when there is no change in input.
Since the minute constant current source composed of the OSFET 40 and the voltage source 41 draws out the electric charge from the load and lowers its potential, the PMOSFET 5 is cut off after a sufficient time regardless of the input voltage. The output error is very small because it is a minute constant current source composed of NMOSFET 3, NMOSFET 40 and voltage source 41 and functions as a source follower circuit. When the input signal V _IN rises from this state, the NMOSFET 3 as a source follower suddenly injects charges into the load capacitance 8 and tries to suddenly raise the output. However, since the drain of the NMOSFET 3 is connected to the current limit composed of the PMOSFET 60 and the constant voltage source 61, the peak current is suppressed. Especially when the number of outputs is large and all outputs may change all at once like a liquid crystal driver, it is important to suppress the peak current. The rise time tr of the output buffer amplifier is the voltage change amount ΔV,
The load capacitance 8 (C _L ), the current I _LP of the current limiting circuit composed of the PMOSFET 60 and the constant voltage source 61, is determined by the following equation.

Next, regarding the falling characteristics, the input voltage V
_{When IN} falls, the NMOSFET 3 is first cut off, and when the change in the input voltage is large, the PMOSFET 5 is subsequently turned on. At this time, a current limiting circuit including an NMOSFET 41 and a constant voltage source 71 is connected to the drain of the PMOSFET 5, and the peak current is suppressed here as well.
The micro-current source consisting of always draws electric charge from the load capacitance 8. Therefore, when the PMOSFET 5 is in the ON state, the small constant current source composed of the NMOSFET 40 and the constant voltage source 41 and the PMO
The electric charge is extracted from the load capacitance 8 in both SFET5.

FIG. 2 is a graph showing the falling characteristic of the output in FIG. 1, showing the response of the output voltage V _OUT when the input voltage V _IN changes stepwise from V ₁ to V ₂ . .

In the figure, the time t from 0 to tf ₁ is a period in which extraction is performed by the sum of the currents of the two current sources. Usually, a constant current source comprising a NMOSFET40 constant voltage source 41. is for flowing a minute current I _B to compensate for the load of the leakage current due to leakage resistance 200 and 201 in FIG fall time tf
_{It can be said that 1} is determined by the current I _LN of the constant current source which is almost composed of the NMOSFET 70 and the constant voltage source 71. At this time, assuming that the gain of the differential amplifier 2 is A, tf ₁ is given by the following equation.

However, if the minimum output voltage of the differential amplifier 2 is Vdoff and the minimum output voltage of the voltage follower is Vmin, then Vth _P + Vdoff <Vmin must be satisfied.

When the output voltage V _OUT drops to V _C , PMOSFET 5 cuts off. For a while after PMOSFET5 is cut off, NMOSFET3
Is also in the cut-off state, and only the current source composed of the NMOSFET 40 and the constant voltage source 41 is enough to extract the electric charge from the load capacitance 8. Then, it continues until the load voltage becomes equal to the input voltage, and at the time when the load voltage becomes equal to the input voltage, the NMOSFET 3 shifts to the ON state and enters the steady state. As described above, since the current I _{B of the} current source composed of the NMOSFET 40 and the constant voltage source 41 is small, it is necessary to bring V _C as close as possible to V ₂ . However, if you get too close,
Through current flows due to process variations.

Also, the total fall time tf until it reaches the steady state
Is given by

Considering the power consumption here, the only current that does not directly contribute to driving the load is the output leakage compensation current I _B at rising, and I _B is a very small current, so the overall power consumption is the minimum required. Can be suppressed to Further, in the steady state, since only the MOSFET 3 works as a source follower in the ON state, the dynamic range of the differential amplifier 2 is sufficient for the output, and the power supply voltage can be reduced to reduce the power consumption.

Since the NMOFET 3 and the PMOSFET 5 do not turn on at the same time, there is no through current, and a current limiting circuit can be connected to each drain to quickly drive the load capacitance 8 while suppressing the peak current.

FIG. 3 is a block diagram showing the entire structure of an embodiment in which the present invention is applied to a liquid crystal display device. The part 1 corresponds to the output buffer amplifier of FIG. 1, 101 is a horizontal scanning shift register, and ST
H and CPH are start pulse and shift clock, respectively. 1
Reference numerals 02 and 103 respectively denote an analog switch and a hold capacitor, which form a sample and hold circuit, and sequentially sample and hold a video signal at the output of the horizontal scanning shift register. An analog switch 104 transmits the signal to the output buffer amplifier 1 by closing the switch after the sample hold for one horizontal scanning period is completed. Therefore, the input of the output buffer amplifier 1 is a DC signal which changes stepwise. The output of the output buffer amplifier is connected to the drain bus Dr of the TFT liquid crystal panel 106 to charge / discharge the capacitor 8. The drain bus Dr is connected to the drain of the TFT 107 provided for each pixel, and when a voltage is applied through the gate bus G ₂ by the vertical scanning shift register, the potential on the drain bus is applied to each liquid crystal cell 108. . In this way, the TFT liquid crystal panel 106 is driven.

Note that CPV and STV are the shift clock and start pulse of the vertical scanning shift register, respectively, and HS is the control signal of the analog switch 104.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The schematic structure is the same as that of the embodiment shown in FIG.
The difference is that the current limiting circuit connected to the drain of OEFET5 is shared by several circuits.

In the liquid crystal display device as shown in FIG. 3, the horizontal scanning circuit has as many outputs as the number of horizontal display pixels, and an output buffer amplifier is required for each of them. In addition, the output buffer amplifier, and especially the current of the final stage amplifier, changes greatly, so in Fig. 4, the main power source of the final stage amplifier is separated from the others, and multiple outputs are grouped together into separate power sources through the current limiting circuit. Connected.
The power source for current limiting is shown by 62 and 72. This type is an effective method especially when it is integrated into an IC, and prevents the interference by separating the power supply from other circuits, and can easily control the output rise and fall times and the peak current from the outside.

FIG. 5 is a circuit diagram showing a specific example of the current limiting circuit of FIG. 4, in which (a) corresponds to the current limiting circuit 62 of FIG. 4 and (6) corresponds to the current limiting circuit 72.

In FIGS. 5A and 5B, 621 and 721 are transistors, and 622 to 624 and 722 to 724 are resistors, which are configured by using bipolar transistors and resistors.

Since the operation of the figure is self-explanatory, its explanation is omitted.

Further, in addition to the one using the transistor as described above,
A configuration in which the power source is simply connected via a resistor is also possible.

FIG. 6 is a constitutional view showing a third embodiment of the present invention. The schematic constitution is similar to that of the embodiment shown in FIG. 3, but a bipolar transistor is used as a transistor instead of a CMOSFET, and a load capacitance 8 The difference is that the current source inserted in parallel with is not a current extraction type but a current injection type.
Depending on the characteristics of the transistor, better results can be obtained in this way.

Since the operation of the figure is almost the same as that of the above-mentioned embodiment, the description thereof will be omitted.

The embodiment of the present invention has been described above. However, also in the case of the circuit configurations shown in FIGS. 1 and 4, a constant current source is inserted between the output terminal and the positive side power source, and the PMOSFET 5 is used as a source follower. Good.

Further, although the capacitive load drive circuit of the present invention has been described above as an output buffer amplifier for a liquid crystal display device, the present invention is not limited to this, and can be applied to a DC buffer amplifier that takes various capacitive loads. It is clear that

〔The invention's effect〕

As described above, according to the present invention, the current required for driving other than the load is suppressed, and the dynamic range of the differential amplifier can be suppressed to the necessary minimum. Since it suppresses the peak current and averages it, the CR type rise and fall characteristics are changed to linear rise and fall characteristics, and both rapid output change and prevention of interference with other circuits due to peak current are compatible. Therefore, it is possible to provide a capacitive load drive circuit having an excellent function, excluding the above-mentioned drawbacks of the related art.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, FIG. 2 is a graph showing the rising and falling characteristics of the output for explaining the operation of the configuration shown in FIG. 1, and FIG. 4 is an overall configuration diagram applied to a display device, FIG. 4 is a configuration diagram showing a second embodiment of the present invention, FIG. 5 is a concrete circuit diagram of a current limiting circuit in the embodiment shown in FIG. 4, and FIG. It is a block diagram which shows the 3rd Example of invention. 1 ... Output buffer amplifier, 2 ... Differential amplifier, 3 ...
NMOSFET, 5 ... PMOSFET, 8 ... Load capacitance, 60 ... PMOS
FET, 70 …… NMOSFET, 62 …… Current source for current limiting, 72 ……
Current source for current limiting.

Claims (2)

[Claims] 1. A SEPP is connected to the output of a differential amplifier, and the SEPP is connected to the SEPP.
In a capacitive load drive circuit using a negative feedback type voltage follower in which the output of the above is fed back to the inverting input of the differential amplifier, the two bipolar transistors (or FETs) constituting the SEPP have the sum of the on-voltages of the two bipolar transistors. Is greater than 0 and is directly connected to each base (or gate), and
A current limiting circuit is provided between at least one of the collector (or drain) and the power source, and a constant current source is provided between the output terminal of the SEPP and the positive or negative power source. Sex load drive circuit. 2. The capacitive load drive circuit according to claim 1, wherein the current limiting circuit is provided between a collector (or drain) of a bipolar transistor (or FET) forming the SEPP and a power supply. The capacitive load drive circuit is characterized in that a plurality of output buffer amplifiers are used in common.