JPH0681276B2 - Image memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device used for real-time processing of moving images.

2. Description of the Related Art When performing image processing such as enlargement of a part of the screen in real time on a moving image signal of a television etc. given as a series of field images, the input moving image signal is once written to the field memory and It is general to read data in a necessary area and perform processing such as interpolation and interpolation. FIG. 4 shows the configuration of an image processing apparatus using a conventional image memory device of this system.

In FIG. 4, 101 is a video signal input, 102 and 110 are selectors for switching signals by a field switching signal given from 111, 103 and 104 are field memories, and 105 is 10
A memory write control circuit for generating a write address of the field memory from the synchronization signal given from 6, 107
Is a memory read control circuit that generates a read address of the field memory in accordance with the read start / end addresses given from 108 and 109. Reference numeral 112 denotes an interpolation circuit that interpolates and interpolates a signal of a partial area of the screen read from the field memory and outputs the signal to 113 as a signal of one screen.

The operation of the image processing apparatus using the conventional image memory device configured as described above will be described.

FIG. 5 is a diagram showing a relationship between an image and an address. A frame is an image of one field, and a hatched portion in the figure is an area which is read from the field memory and enlarged. Therefore, the start address read from the field memory corresponds to the upper left point of the shaded portion, and the end address also corresponds to the lower right point of the shaded portion.

FIG. 6 is a graph showing an address signal generated by the memory write / read control circuit and corresponding to FIG. In the figure, the solid line is the write address and the alternate long and short dash line is the read address.

The selectors 102 and 110 switch the field memories 103 and 104 for writing and reading for each field by the field switching signal 111.

As shown by the solid line in FIG. 6A, the memory write control circuit 105 generates a write address so as to write the video signal in each valid period of each field into the field memory. Further, the memory read control circuit 107 generates a read address for reading between the read start address 108 and the read end address 109 in each field, as indicated by the dashed line in FIG. Therefore, the address signals given to the field memories 103 and 104 are as shown in FIGS. The interpolation circuit 112 expands the signal of the area read from the field memory 103 or 104 into a video signal of one screen by inserting a scanning line, and outputs it to the output terminal 113.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, as described above, in the conventional configuration in which two field memories are provided for writing and reading, the memory capacity is too large and the cost and power consumption are large, so that the cost is low, the size is small and the port is portable. It had a problem that it was difficult to make it.

Further, even when a dual port type field memory that can access reading and writing independently in parallel is used, these two field memories cannot be reduced to one field. As shown in FIG. 6A, when the write address overtakes the read address, the read image is 1 until the read image is overtaken.
The image before the field becomes the image of the field after being overtaken, and the image is switched in the middle of the image of one field, which causes a problem in image quality.

In view of the above point, the present invention has an object to provide an image memory device capable of processing such as real-time expansion of a moving image in a memory for one field.

Means for Solving the Problems To achieve the above object, the present invention provides a field memory having an image storage capacity of one field or more, and an arbitrary signal of a first field signal stored in the field memory. The memory read control unit for reading the area and the write start address of the second field following the first field are determined so as to be after the address next to the read end address of the area read by the memory read control unit, A memory write control unit for writing the video signal of the second field in the field memory in a ring shape, starting from the write start address, is provided.

Operation With the above configuration, the input video signal is used as a field memory in the form of a ring memory (memory controlled so that the upper limit address and the lower limit address of the memory are apparently continuous) from the write start address given by the memory write control unit. Write in. By the end of the vertical blanking period, the start address and end address of an arbitrary area to be read in the next field are determined, and the write start address is determined after the address next to the read end address. The memory read control unit reads an arbitrary area from the field memory corresponding to the read address.
The memory write control unit writes the video signal of the new field in a ring memory form from the write start address in parallel with the read. By repeating these steps, the video signal of the read area and the video signal of the next field to be newly written do not overlap, and
It is possible to realize the same function as the conventional image memory device with the memory for the field.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an image memory device and an image processing device using the same in a first embodiment of the present invention.

In FIG. 1, reference numeral 1 is a video signal input, which is input to an input port of a dual port type field memory 2. Three
Is a memory write control circuit, which generates a write address corresponding to the video signal input 1 from the synchronization signal given to 4 and the read end relative address given to 7, and gives it to the field memory 2. Further, the write start address of the field is given to the memory read control circuit 5. Reference numeral 5 denotes a memory read control circuit which, based on the read start relative address given to 6, the read end relative address 7 and the synchronization signal 4, reads a read address corresponding to the data in the end area (described later) shown in FIG. It is generated and given to the field memory 2. Reference numeral 8 denotes an interpolation circuit, which interpolates / interpolates a partial area of the image read from the field memory 2 to enlarge the image on one screen, and outputs the image output terminal 9
Output to.

The operation of the image pickup apparatus having the above-described structure according to this embodiment will be described with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing a relationship between a video signal for one field written in the field memory 2 and a region which is also read out. In the figure, the shaded area is the readout area. The upper left of the read area is the read start address, which is obtained by adding the read start relative address 6 to the write start address of the previous field obtained from the memory write control circuit 3. Similarly, the read end address at the lower right of the shaded area is obtained by adding the read end relative address 7 to the write start address of the previous field.
These processes are performed by the memory read control circuit 5. Then, in order to read in the next field, the write start address for the next field, which is written at the same time as the reading of the field, is determined by the memory write control circuit 3 so as not to overlap the read area and close to the read end address. It Here, when the capacity of the field memory 2 is only one field, the range from the address next to the read end address to the start address of the scan line next to the read end scan line (the capacity of the field memory 2 has a margin). In some cases, the write start address may be determined at any address within the range including the margin).

FIG. 3 is a graph showing the write / read addresses generated as described above. Fig. 3 (a)
Is a diagram showing addresses when the same position on the screen is read in n, n + 1 fields. The write start address of each field is represented by a white circle, and the read address is represented by a black circle. Here, the read start address of the n field is obtained by adding the read start relative address to the write start address of the (n-1) field as described above. Then, similarly, from the read end address obtained by adding the read end addresses, n
The write start address (white circle) of the field is determined as described above. Furthermore, in the (n + 1) field,
Based on the write start address of the n field, the read start address is obtained by adding the read start relative address, and the read end address is also obtained by adding the read end relative address. The write start address of the (n + 1) th field is determined based on the read end address thus obtained.

Further, when the write (read) address reaches the upper limit address of the field memory, the control is performed so as to continue writing (read) from the lower limit address of the field memory.

FIG. 3B shows addresses when the vertical position of the read area is different between the n field and the (n + 1) field. Also in this case, similarly, the read start relative address / read end relative address of the field is added to the read end address of the previous field, and the write start address is obtained from the obtained read end address of the field. (However, the write start address must be determined before the writing of the field starts. That is, these operations must be completed before the valid period of the field starts.) By repeating the operation, the video signal input 1 is written in the field memory 2, and at the same time, the area designated by the read head address 6 and the read end relative address 7 is read from the field memory 2. This output is enlarged by the interpolation circuit 8 as a signal for one screen as in the conventional example, and the enlarged video signal is output to the output terminal 9.

Moreover, referring to FIGS. 3A and 3B, since the write address does not overtake the read address, the read image data are all signals of the previous field.

As described above, the image processing device using the image memory device of this embodiment can realize exactly the same function as that of the conventional example with one field memory which is half of the conventional one.

In the above embodiment, the case where the field memory 2 is composed of a dual port type memory has been described. However, by using a normal 1 port memory, the write address and the read address are alternately given to perform the write and read operations. It may be divided.

Further, in the above embodiment, for simplification of description, the case where the reading area is limited only in the vertical direction has been described, but in the case where the reading area is also limited in the horizontal direction (for example, only the central portion of the image is read). Divides the address given to the field memory 2 into a vertical address and a horizontal address,
The same effect can be obtained by adding the above control only to the vertical address.

EFFECTS OF THE INVENTION According to the present invention, even in real-time processing such as writing a moving image in a memory and enlarging a predetermined portion, the video signal in the area to be read and the video signal in the next field to be newly written do not overlap each other. The same function can be realized in one field, which is half the conventional memory. Therefore, the capacity of the image memory can be halved, and the effects of downsizing, low power consumption and low cost of the device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus using an image memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing the relationship between image signals and addresses in the same embodiment, and FIG. 3 is a graph showing the relationship between write addresses and read addresses in the same embodiment. FIG. 4 is a block diagram of an image processing apparatus using a conventional image memory device, FIG. 5 is a relationship diagram between image signals and addresses in the conventional example, and FIG. 6 is a relationship between write address and read address in the conventional example. It is a graph which shows. 2 ... Field memory, 3 ... Memory write control circuit, 5 ... Memory read control circuit.

Claims (7)

[Claims] 1. A field memory having an image storage capacity of one field or more, a memory read control unit for reading an arbitrary area of a signal of a first field stored in the field memory, and the first memory. The write start address of the second field following the field is determined to be after the address next to the read end address of the area read by the memory read control unit, and the video signal of the second field is set to the write start address. An image memory device, comprising: a memory write controller that writes in a ring shape in the field memory. 2. The image memory device according to claim 1, wherein the field memory is a memory having independent ports for writing and reading. 3. The image memory device according to claim 1, wherein the memory read control unit determines a read start address and a read end address during the vertical blanking period. 4. The image memory device according to claim 1, wherein the memory write control unit determines the write start address during the vertical blanking period. 5. The memory write control unit determines the write area range of the field memory to an area substantially equal to the input video signal in one field period.
The image memory device described. 6. The image memory device according to claim 1, wherein the memory read control unit determines the read area range of the field memory within the write area range of the previous field. 7. The memory write control unit determines the write start address of the second field between the read end address and the write start address of the first field which is captured in a ring shape after the read end address. 1. The image memory device according to 1.