JPH0681530B2 - Servo circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape recorder, a VTR, or the like having a speed servo system for keeping the speed of a motor of a rotary drive system constant.

Background Art and Its Problems In tape recorders and VTRs, a speed servo circuit is generally used to stabilize the running speed of a tape as a recording medium or to keep the rotational speed of a rotary head constant.

FIG. 1 shows an example of a speed servo circuit of a tape recorder, which is a case where a capstan motor (1) is controlled. That is, in the case of this example, the signal FG of the frequency corresponding to the rotation speed of the motor from the frequency generator (2) provided coaxially with the rotation shaft of the capstan motor (1) is the speed servo circuit (3).
Is supplied to the speed servo circuit (3), and an error voltage corresponding to the difference between the value when the number of rotations of the motor is a predetermined value and the number of rotations of the motor at that time is obtained, and this is obtained through the operational amplifier (4). Supplied to the drive amplifier (5),
The motor (1) is controlled by the voltage from the drive amplifier (5) so that the motor (1) rotates at a constant rotation speed.

In this case, the motor (1) requires a certain operating voltage. Now, the circuit power supply voltage is ± 10V, the motor operating voltage is 3V
Then, the speed error fluctuates ± 10V around 0V. Then, the speed error becomes 0V in the state of normal motor rotation, and 3V is added as the bias voltage 3V to obtain the motor supply voltage. This bias voltage is generally set by a bias voltage supply circuit (6) as shown in FIG. 1, and this predetermined bias voltage Vm is mixed with a speed error in an operational amplifier (4) and supplied to the motor (1). It has become so.

FIG. 2 shows an example of the case where this servo circuit is digitally configured. The frequency signal FG (FIG. 3A) from the frequency generator (2) is supplied to the digital delay circuit (11), From this, a signal FD (FIG. 3B) in which the falling edge of the signal FG is delayed by a predetermined time is obtained, and this is supplied to the digital trapepe (12). In this digital trapeze (12), as shown in analog form in FIG.
A digital signal of a trapezoidal wave signal whose voltage gradually rises from the time when the FD falls is obtained, and this is supplied to the latch circuit (13). The digital trapepe (12) is composed of, for example, a counter. That is, the counter is preset by the falling edge of the signal FD, the clock is counted from the preset value, and the counter value is latched at the rising edge of the signal FG in the latch circuit (13). The output of this latch circuit (13) is D / A.
The converter (14) converts the analog signal back into an analog signal, which is supplied to the mix amplifier (15). Mix amplifier (1
The bias voltage Vm as described above is supplied from the bias voltage supply circuit (6) to 5), and the voltage obtained by adding both is supplied to the motor (1) to form a speed servo loop.

In this case, as described above, in the normal motor rotation, the latch circuit (13) latches an intermediate value between the minimum value and the maximum value of the digital value from the digital trapepe (12), that is, D / As for the analog voltage after A conversion, 0V is latched and servo is applied (Fig. 3C).
reference).

However, in such a servo circuit, the operating voltage of the motor changes due to variations in motor manufacturing and load torque. Now, assuming that the drive voltage of the motor is different from the bias voltage Vm by ΔV, the bias voltage must be Vm + ΔV accordingly.
Therefore, it is necessary to make the bias voltage supply circuit (6) variable and adjust it according to the variation of the motor.

Further, in the VTR and the like, in the servo circuit of FIG. 1, a phase servo circuit is further provided before the operational amplifier (4) as a mixing circuit, and the phase servo error voltage is added in addition to the speed servo error voltage and the bias voltage. Then, it is supplied to the drive amplifier (5). However, the phase servo system does not lock the phase unless the motor rotation is controlled within an appropriate frequency range by the speed servo. Therefore, when the operating voltage of the motor changes, unless the bias voltage is supplied from the bias voltage supply circuit (6) following the change, the motor cannot be controlled by the speed servo to the rotational speed at which the phase servo locks. Therefore, there is a risk that phase lock will not be applied. Therefore, also for that purpose, it is necessary to make the bias supply circuit (6) variable and perform the adjustment.

Further, if the operating point of the motor varies in the servo system as described above, a steady speed error occurs because the DC gain of the speed servo is finite. That is, wow and flutter occur even in a steady state. This occurs because the speed servo does not lock at the point where the error voltage is 0V, but tries to lock at a point that deviates from 0V due to the bias voltage fluctuation. Therefore, in order to eliminate this error, it has conventionally been necessary to adjust the bias voltage.

Conventionally, the adjustment of the bias voltage is performed for each individual motor by using, for example, a semi-fixed potentiometer, but the adjustment is very troublesome and must be performed for each machine. From tape recorders and VTRs
This markedly hindered the mass production of.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a servo circuit capable of automatically adjusting the bias voltage by following the variation of the operating voltage of the motor due to variations in the motor and torque load. It is the one we are trying to provide.

SUMMARY OF THE INVENTION According to the present invention, a digital delay means for delaying a frequency signal from a frequency signal generating means for obtaining a frequency signal according to a rotation speed of a motor, and a delay frequency signal from the digital delay means are counted to rotate a motor. The measuring means for measuring the period of the frequency signal according to the number, the latch means for latching the measured output from this measuring means, the latch output from this latch means and the reference value are compared, and depending on the comparison result, By having a comparison means for controlling the delay amount of the digital delay means and a conversion means for converting the latch output from the latch means into an analog signal and supplying this analog signal to the motor, it is possible to always change the bias voltage of the motor. It is designed to be able to follow.

Embodiment FIG. 4 is a block diagram of an example of the present invention, and the portions corresponding to those of the example of FIG.

In this example, a digital signal corresponding to the speed servo error voltage latched in the latch circuit (13) is supplied to the comparison circuit (17). Here, the output of the latch circuit (13) latches the output of the digital trape (12) at the rising edge of the signal FG, that is, the count value of the counter, which corresponds to the cycle of the frequency signal FG. ing.

On the other hand, the reference signal REF corresponding to the count value of the digital trapepe (12) when it is the frequency signal FG at the target rotation speed of the motor (1) is supplied to the comparison circuit (17) through the terminal (20). It

The output of the comparison circuit (17) is supplied to the digital variable delay circuit (21) provided between the digital delay circuit (11) and the digital trapepe (12) through the digital processing circuit (18 '). Then, in the digital variable delay circuit (21), the signal FD from the digital delay circuit (11)
The falling position of is variable.

That is, the signal FG (Fig. 5A) is the digital delay circuit (1
In 1), it is delayed to be the signal FD (Fig. B),
In this variable delay circuit (21), the digital processing circuit (1
The falling position is changed by the signal from 8 '). When the output FD of the digital delay circuit (11) is directly supplied to the digital trapepe (12) and latched, the speed servo system operates so as to lock at the point where the speed servo error is 0, as shown in FIG. 5C. However, the processing circuit (1
When delayed by the output of 8 '), the output of the digital delay circuit (11) is advanced as shown in Fig. 5D, so that the latch output of the output of the digital trapepe (12) is higher than 0V. Therefore, control is performed so that the voltage of the difference between this 0 V and this latch output is exactly the bias voltage of the motor (see FIG. 5E).

That is, in this example, the motor operating voltage is superimposed as the data of the latch circuit (13). Then, the adjustment of the operating voltage is performed in the digital variable circuit (21) through the comparison circuit (17) and the digital processing circuit (18 ').

Therefore, the motor (1) is always controlled to have a constant speed, and at the same time, the bias voltage is automatically set. Even if the operating voltage of the motor (1) fluctuates, the bias voltage is always automatically adjusted by the system of the comparison circuit (17) to the digital variable delay circuit (21). Therefore, it is not necessary to adjust the bias voltage of the motor as in the conventional case, and the steady speed error as in the conventional case does not occur.

FIG. 6 shows an example of a concrete embodiment of the example of FIG.

In the figure, (31) is a terminal to which the frequency signal FG from the frequency generator (2) is supplied, and the waveform is shaped by the amplifier (32) and the D flip-flop circuit (33) to obtain the signal F.
G '.

That is, the D flip-flop circuit (33) is supplied with a clock pulse CK having a frequency sufficiently higher than that of the signal FG from the clock terminal (34), and the signal FG 'is synchronized with the clock pulse CK and the frequency signal FG. A signal delayed by one clock is obtained (Fig. 7A).

Further, the signal FG 'is supplied to the D flip-flop circuit (35) and further delayed by one clock CK, and its output and the signal FG' are NAND gate (36).
Then, the NAND gate (36) provides a signal FP having a pulse width of one clock (FIG. 7B).

Also, the output FP of this NAND gate (36) is the counter (3
It is supplied to the clear terminal of 7) and this counter (3
The clock signal CK is supplied to (7) and this counter (3
From 7), a pulse CA (FIG. 7C) which rises when a predetermined time has elapsed from the rise of the signal FP is obtained. Further, the output of this counter (37) is supplied to the counter (38), from which the pulse CA is output from the rising edge of the signal FP.
Pulse QD rising in 1/2 pulse width period (Fig. 7D)
Is obtained.

The pulse QD is supplied to the latch circuits (74) (75) (76) described later as the latch pulse.

Further, (40), (41), and (42) are counters as digital trapezes, and the clock terminal has a clock CK.
However, the pulse CA is supplied to the load terminal. Therefore, the counters (40) (41) (42) are preset to the count value loaded by the pulse CA and supplied to the preset terminal, and the count value is incremented from the preset value.

Latch circuits (43) (44) and (45) for latching the count values of the counters (40) to (42) are provided at the subsequent stage of the counters (40) (41) and (42). The latch circuits (43) (44) (45) can be latched during the pulse width period of the signal FP, and the counter (40) is generated by the clock CK.
The count values of (41) and (42) are latched. Not all 12 bits of this latch output are used, but in this example, the lower 8 bits are used for servo. Therefore, only the outputs of the latch circuits (43) and (44) are used.

The data selectors (46) and (47) in the latter stages of the latch circuits (43) and (44) are also taken into consideration when the motor is started, and the signals obtained from the data selectors (46) and (47) are D / The analog voltage is converted into an analog voltage by the A converter (48) and is taken out as a speed error voltage through the amplifier (49).

When the signals supplied to the G terminals of the selectors (46) and (47) are at the high level, the outputs obtained at the output terminals (1Y) to (4Y) are all at the low level regardless of the input. When the G terminal is at the low level and the S terminal is at the low level, the output is from the input terminals (1A) to
It is obtained by selecting the data supplied to (4A), and if the S terminal is at high level, it will be output as an input terminal (1B) to (4B)
It is designed so that you can select and obtain the data that is supplied to you.

The output of the selectors (46) (47) starts the motor, stops the speed accuracy, and so on.

That is, (50) is a control switch for controlling the start and stop of the motor (1), for example, when the play button is pressed, this switch (50) is connected to the upper contact in the figure and the state of the control signal CONT is set. Accordingly, the output P _ON of the circuit (52) in the latter stage of the D flip-flop circuits (51) (52) connected in series is supplied to the clock terminal of the D flip-flop circuit (53) and the pulse FP The circuit (53) is cleared by the output of the circuit (55) at the latter stage of the two flip-flop circuits (54) (55) whose (Fig. 8B) is supplied to the clock terminal, and the circuit (5
From 3), the start pulse STAP that becomes high level during the period from the rising of the output P _{ON to} the arrival of two pulses FP.
(FIG. 8C) is obtained.

Then, the output P _ON is inverted in polarity and supplied to the OR gate (56) and is also supplied to the AND gate (57) as it is, and the start pulse STAP is inverted in polarity to the AND gate (58) and the counter (42). Carry pulse DCA (FIG. 7E) is supplied. This AND gate (5
The output of 8) goes through the AND gate (59) and the OR gate (5
6) Supplied to.

Therefore, when the play button is turned on to drive the motor, the output P _ON goes high and the pulse STAP goes high, so that the output of the OR gate (56) goes low. On the other hand, at startup, the output of the AND gate (57) is at the low level because the output of the D flip-flop circuit (61), which will be described later, is at the low level, so that the inputs (1A) to (Four
The 8-bit all "1" signal supplied to A) is obtained, and this is converted into an analog voltage by the D / A converter (48) and obtained as a servo error voltage, so that the motor rapidly starts.

When the stop button is pressed and the output P _ON goes to low level, the G terminals of the selectors (46) (47) go to high level, and the outputs of the selectors (46) (47) all become "0", and the motor The supplied servo error will be a negative voltage and the brake will be applied to stop the motor.

Next, the servo operation in the steady state will be described.

NAND gate (60) and D flip-flop circuit (61)
Is for detecting whether the signal FG is close to the value when the motor speed is correct, that is, whether the motor speed is within the speed servo pull-in range. The output of the NAND gate (60). RNGE (FIG. 7F) becomes low level during the period including the pulse FG when the period of the signal FG is substantially correct. In the D flip-flop circuit (61), the output of the NAND gate is sampled in the period of the pulse FP to obtain the inverted output. Therefore, when the pulse FP exists in the low level period of the output RNGE, the D flip-flop circuit (6
The output DS of 1) is always high level.

On the other hand, since the G terminal is low level, the selector (46)
The latch output of the latch circuits (43) and (44) supplied to the input terminals (1B) to (4B) is obtained from (47), which is the D / A.
Supplied to the converter (48). That is, speed servo is applied so that the rotation speed of the motor becomes a constant value.

Next, when the motor speed decreases or increases and the pulse FP falls outside the low level period of the output RNGE, the output DS of the D flip-flop circuit (61) is always low level, and therefore, The output of the AND gate (57), and thus the S terminal, becomes low level. Then, when the motor rotation speed is slow and the period of the signal FG is longer than a predetermined value, a carry pulse that becomes a high level is obtained from the counter (42), so that the output of the AND gate (58) is at a low level, so that the G terminal Low level, selector (46)
From (47), high level signals supplied to the input terminals (1A) to (4A) are obtained, and the number of rotations of the motor is increased. On the other hand, when the motor rotation speed is high and the cycle of the signal FG is shorter than the desired value, the carry pulse cannot be obtained from the counter (42), so the AND gates (58) and (6
Since the output of 2) becomes high level, and the G terminal becomes high level, the outputs of the selectors (46) and (47) all become "0", and the rotation of the motor is reduced.

The inverted output of the output of the counter (42) is sampled in the D flip-flop circuit (63) during the period of the pulse FP, and its output and the output of the D flip-flop circuit (61) are ANDed by the AND gate (64). And its output is obtained via the AND gate (65). This AND gate (6
The output of 5) has the speed servo in the lock range,
Indicates that the phase servo is within the lock range and that the phase servo can be locked. Therefore, when the phase servo is also used, the phase servo circuit is activated when this output becomes high level. However, when the additional loop of the present invention described below is used, the phase servo circuit does not work, and the output of the AND gate (65) is set to low level by turning on the switch (66). On the contrary, when the phase servo circuit is activated, the system of the additional loop described below is disconnected.

Arithmetic circuits (71) to (73), latch circuits (74) to (76),
The selectors (77) to (79) form a digital variable delay circuit.

That is, the outputs of the selectors (77) to (79) are preset inputs of the counters (40) to (42), and by changing the outputs obtained from the selectors (77) to (79),
Variable delay operation is performed. In this case, the selector (77) ~
The output of (79) is supplied to the arithmetic circuits (71) to (73) and the arithmetic operation of "+1" or "-1" is performed, and the arithmetic output is latched by the latch circuits (74) to (76). The preset values of the counters (40) to (42) can be changed by obtaining the latch output from the selectors (77) to (79).

Further, the arithmetic circuits (81) (82) (83) form a subtraction circuit, and one of the input terminals has a latch circuit (43)-
The output of (45) is supplied, and the outputs of the selectors (77) to (79) are supplied to the other input terminals. Selector (7
The outputs of 7) to (79) are preset values of the counters (40) to (42), and the outputs of the latch circuits (43) to (45) are of the counters (40) to (42) at the time of the pulse FP. Since they are count values, the difference between them is equal to the count value of the clock CK for one cycle of the signal FG.

8 bits of the output of the difference between the two are compared (8
Supplied to 4) and (85). These two comparison circuits (8
4) and (85) do not use a constant value as the reference signal REF, but use a reference signal having a predetermined allowable width as the reference signal REF. The value set by the setting circuit (86) for setting the value is supplied, and the lower limit value set by the setting circuit (87) is supplied to the comparison circuit (85). Then, in the comparison circuits (84) and (85), signals of the output values from the arithmetic circuits (81) to (83) and the set upper and lower limit values are compared, and the arithmetic circuits (81) to (83). The signal UD _{1 that} changes the state when the output of is larger than the lower limit and when it is smaller than
4) and the signal UD ₁ from the comparison circuit (84) controls whether the arithmetic circuits (71) (72) (73) subtract or add.

Further, an AND circuit (88) is provided for detecting when the outputs of the arithmetic circuits (81) to (83) are just between the upper limit value and the lower limit value, and the output of this AND circuit (88) is the OR gate (89). ) Is supplied to the enable terminals of the latch circuits (74), (75) and (76) through the latch circuits (74) to (76).
Is designed not to latch the outputs of the arithmetic circuits (71) to (73) when the outputs of the arithmetic circuits (81) to (83) are just between the upper limit value and the lower limit value.

The above circuit operates while being controlled by the following control signals.

That is, as described above, in the state where the power switch is turned on, the counter (91) is cleared by the signal P _{ON which} goes high when the play button is pressed, for example. A signal FP is supplied as a clock to the counter (91), and for example, every time 16 signal FPs are counted, a carry pulse is obtained from this, and this is supplied to the D terminal of the D flip-flop circuit (92). The high-level signal being sampled is sampled to obtain a high-level signal MODY (FIG. 9A). The length of the predetermined period from the rising of the signal P _{ON to} the rising of the signal MODY is set to be long enough for the speed servo to rise and be pulled into the lock range.

This signal MODY is supplied to the S terminals of the data selectors (77) to (79), and when it is at the low level, the input terminal (1A)
This data selector (7
Obtained from 7) to (79), and at that value the counter (40) to (42)
Preset. Then, when the signal MODY becomes high level, the signals from the latch circuits (74) to (76) are obtained from the selectors (77) to (79). That is, for a predetermined period after the play button is pressed, the data selectors (77) to (79) set the appropriate initial value to the counter (40).
~ (42) is supplied to the preset terminals, and the counters (40) to (42) are loaded by the signal CA (Fig. 7C) whose rising edge is delayed by a predetermined time from the pulse FP from the counter (37). , The count value supplied to the preset terminal at the time of its rising is preset, the clock CK is counted from the value, and the count value is incremented. Then, as described above, the count value is latched by the latch circuit (43).
It is latched by the pulse FP with a phase leading from the pulse CA at (45).

Next, after a predetermined time has elapsed from the rising of the signal P _ON , the signal M
When ODY rises, the outputs of the latch circuits (74) to (76) are obtained from the selectors (77) to (79).
At this time, the inverted pulse LE becomes low level every time the carry pulse of the counter (91) is obtained, so that the output pulse Q _D of the counter (38) falls at the low level period of this pulse LE. The outputs of the arithmetic circuits (71) to (73) are latched in the latch circuits (74) to (76).

In this case, the outputs of the selectors (77) to (79) are supplied to the arithmetic circuits (71) to (73) and the output UD of the comparison circuit (84).
_{According to 1} , the count values are incremented by "1" or decremented by "1" in the arithmetic circuits (71)-(73).
That is, when the outputs of the arithmetic circuits (81) to (83) are smaller than the lower limit value, it means that the cycle of the signal FG is short, and therefore the arithmetic circuits (71) to (73) increase by "1". Since the operation is performed and the output of the comparison circuit (85) becomes low level, it is latched at (74) to (76) by the pulse Q _D during the low level period of the pulse LE, which is selected by the selectors (77) to (79). To the preset value. Then, the counter (4
Since 0) to (42) start counting, the rising position of the ramp wave in the case of analog voltage is delayed, and the values of the latch circuits (43) to (45) become smaller, which causes the motor rotation speed to decrease. Will go down. Then, the arithmetic circuit (8
Until the output of 1) to (83) becomes larger than the lower limit,
The preset values of the counters (40) to (42) increase by "1". Then, when the output of the arithmetic circuits (81) to (83) becomes larger than the lower limit value but smaller than the upper limit value,
The FG cycle is within the allowable value, and the motor rotates at a constant speed. And at this time, the comparison circuit (84) (85)
Outputs UD ₁ and UD ₂ go high and the AND gate (8
Since the output of 8) becomes high level, the latch circuit (74)
~ (76) is retained at the previous value.

Further, when the output of the arithmetic circuits (81) to (83) becomes larger than the upper limit value, the output UD ₁ of the comparison circuit (84) is at a low level, and the arithmetic circuits (71) to (73) each output "1". Is subtracted. Then, the output of the AND gate (88) becomes low level, and the subtraction result is latched by the latch circuits (74) to (76) by the pulse Q _D during the low level period of the pulse LE. Therefore, the outputs of the selectors (77) to (79), that is, the preset values of the counters (40) to (42), become smaller, and the trape rises faster, which in turn increases the latched count value and increases the servo error. The voltage goes up. In this case, as shown in FIG. 9, after the power is turned on, the play button is first pressed to drive the motor (hereinafter referred to as motor ON), and after the signal P _ON becomes high level, the switch is turned on. The signal MODY remains high level even if the motor is turned on and off repeatedly with (50). However, the carry of the counter (91) becomes low level when the motor is turned off (when the stop button is pressed),
The signal LE becomes high level and the latch circuits (74) to (76)
Is disabled. Then, the motor is turned on next time, and when the above-mentioned predetermined period elapses from the time when the signal P _ON rises, the carry pulse which becomes the high level is obtained from the counter (91), and therefore the signal LE becomes the low level during the pulse width period, The latch circuits (74) to (76) can be latched by the latch pulse Q _D. Latch circuit (7
The latch enable states of 4) to (76) are shown in FIG. 9B.

When the motor is turned off, the latch circuit (7
4) to (76) retain the data immediately before that, so the next time the motor is turned on, the counter (40) will be set to the previous value.
~ (42) will be preset. Therefore,
The speed servo will soon be retracted.

Thus, the counters (40) to (42) are
The bias voltage of the motor is determined by the additional loop including the circuits (71) to (89) by changing the motor rotation speed to a predetermined value.

Further, even if the operating point voltage of the motor fluctuates, the bias voltage is automatically determined to follow this.

As described above, in the present invention, the bias voltage of the motor is not set and supplied by the bias setting circuit, but the signal serving as the servo reference other than the speed servo system has a predetermined value. Since a loop is added and the bias voltage of the motor is supplied by this loop, the bias voltage can be set automatically.

Therefore, the labor of adjusting the bias voltage by using the semi-fixed potentiometer as in the conventional case can be omitted, and the mass productivity is improved.

Further, since the additional loop of the present invention makes the period of the signal serving as the servo reference always equal to the period when the motor speed is correct, wow and flutter in the low range is greatly improved, and the steady speed deviation is increased. Becomes almost 0.

If an additional loop is provided in the circuit having the speed servo and the phase servo, the following effects can be obtained.

That is, when the phase servo is applied, it is necessary to first set the motor rotation speed within a certain range only by the speed servo. However, according to the present invention, even if the motor operating point varies due to the additional loop, the range where the phase can be locked is surely achieved. Since it can be pulled in, the phase is locked.

[Brief description of drawings]

1 and 2 are views showing an example of a conventional speed servo circuit, FIG. 3 is a time chart for explaining the same, FIG. 4 is a block diagram of an example of the present invention, and FIG. 5 is FIG. 6 is a time chart for explaining the above, FIG. 6 is a diagram showing an example of a concrete configuration of FIG. 4, and FIGS. 7 to 9 are time charts for explaining the same. (1) is a motor, (2) is a frequency generator, (11) is a digital delay circuit, (12) is a digital trape, (13) is a latch circuit, and (17) is a reference signal and a signal for obtaining a speed servo error. A comparison circuit for obtaining the output of the difference between the two by comparing the difference between the cycles, (18 ') is a digital processing circuit, and (21) is a digital variable delay circuit.

Claims (1)

[Claims] 1. A digital delay means for delaying a frequency signal from a frequency signal generating means for obtaining a frequency signal according to the rotation speed of the motor, and a delay frequency signal from the digital delay means is counted to count the number of revolutions of the motor. Measuring means for measuring the cycle of the frequency signal, latch means for latching the measurement output from this measuring means, and the latch output from this latch means and the reference value are compared,
Comprising a comparison means for controlling the delay amount of the digital delay means according to the comparison result, and a conversion means for converting the latch output from the latch means into an analog signal and supplying the analog signal to the motor. Characteristic servo circuit.