JPH0682132B2 - Waveform storage - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital waveform storage device used in a measuring device such as a recorder, a digital oscilloscope, a waveform analysis device.

2. Description of the Related Art Conventionally, as shown in FIG.
A sample clock generator 1, an analog / digital converter 2, a data latch 3, a digital comparator 4, a control logic 5, an operation mode register 6, a recording clock generator 7, an address counter 8 and a memory 9 (Japanese Patent Publication No. Sho). 58-4
See 7661). Reference numeral 10 surrounded by a broken line is a digital peak detector including a data latch 3, a digital comparator 4, data buses 11 and 12, and a control signal 13.

The analog signal is input from the analog input terminal 14 to the analog / digital converter 2, and the sample clock generator 1
Is converted into n-bit digital data in the cycle of the sample pulse generated by and is output to the data latch 3. This digital data is compared with the two previously captured digital data recorded in the two latches in the data latch 3 and the two comparators in the digital comparator 4. The two pieces of digital data captured last time are the maximum value and the minimum value, and when the digital data newly output from the analog / digital converter 2 is larger than the maximum value already recorded or smaller than the minimum value, The digital comparators 4 each inform the control logic 5 that a new value has been detected. This causes the control logic 5 to strobe the latch to be updated and record the new maximum or minimum value in the data latch 3. This operation is repeated in the cycle of the sample pulse, and the recorded content in the data latch 3 is updated each time a new maximum or minimum value is detected. Recording clock generator 7
Is generated by the clock pulse generated by the address counter 8
Is updated and the maximum and minimum values recorded in the data latch 3 are recorded in the memory 9 at the memory address indicated by the address counter 8. At the same time, the control logic is also updated, and two latches in the data latch 3 are reset to newly start detection of the maximum value and the minimum value.

FIG. 4 shows the operation timing in the conventional device, showing the recording data when the peak is not detected by the sample clock, the analog signal, and the recording clock, and the recording data of the maximum value and the minimum value when the peak detection is performed. There is.

As described above, also in the conventional waveform storage device, the maximum value and the minimum value can be detected and stored by converting the analog signal into a digital signal.

However, in the above conventional waveform storage device, since the digital peak detector 10 must operate at the same sample clock speed as the analog / digital converter 2, when the sample clock is high speed, Digital peak detector 10
Had the problem of becoming expensive.

The present invention solves such a conventional problem. Even when the sample clock is high-speed, a low-speed and inexpensive digital peak detector is used to detect the digital peak at the same speed as the sample clock. It is an object of the present invention to provide an excellent waveform storage device that can realize equivalent resolution.

Means for Solving the Problems In order to achieve the above object, the present invention distributes n (n is a natural number) digital signals obtained by analog-to-digital conversion of analog signals with a sample clock, and outputs each digital data from a distributor. Is compared by a multi-step size comparator, and the maximum and minimum values are detected from among the maximum and minimum values that are sequentially output from each size comparator, and the analog / digital converted digital data is sequentially The maximum value and the minimum value are detected from a plurality of output data stored in the memory.

Action The present invention has the following effects due to the above configuration. That is, when the maximum value and the minimum value are detected from n integer multiples of data, the data analog / digital converted by the sample clock is distributed to a plurality of magnitude comparators,
In the tournament method, the maximum and minimum values are calculated from the n pieces of data before digital peak detection is performed. Therefore, if each size comparator and digital peak detector operate at the speed of 1 / n of the sample clock. Good. Also,
When the maximum and minimum values are detected from data other than integer multiples of n, the digital peak is detected after the analog / digital converted data is stored in the memory. It suffices if the detector operates. Therefore, there is an effect that the digital peak can be detected with a low-speed and inexpensive circuit configuration, which has the same resolution as that when the digital peak is detected at the same speed as the sample clock.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, reference numeral 21 is an analog input terminal, which is connected to the analog / digital converter 23. 22 is a sample clock generator, and the sample clock output from this is the analog / digital converter 23 and the control logic 24.
Entered in. The output of the analog / digital converter 23 is
It is input to the 4-phase distributor 25, and the four pieces of data are input to the two magnitude comparators 26 and 27 and A of the data selector 28. The distributor 25 distributes and converts the serial digital data sequentially output from the analog / digital converter 23 into n pieces of parallel digital data and outputs them. The output data of the large and small comparators 26 and 27 is the other two large and small comparators 29 and 29.
It is input to 30 and compared in magnitude, and then input to digital peak detectors 31 and 32. The large and small comparators 26 and 27, together with the other comparators 29 and 30, constitute a multi-stage (two stages in this embodiment) large and small comparator. First, the large and small comparators 26 and 27 corresponding to the first stage. Then, the four pieces of data output from the distributor are grouped into two pieces and compared in magnitude. Next, the large values obtained by the large and small comparators 26 and 27 are input to the large and small comparator 29 corresponding to the second stage, while the large and small comparators are input.
The small values obtained by 26 and 27 are input to the size comparator 30 corresponding to the second stage, so that the four data output from the distributor 25 are transferred to the large values after the second stage. , Are configured to be grouped into smaller values and compared in magnitude. The output data from the digital peak detectors 31 and 32 is input to B of the data selector 28. The output of the data selector 28 is input as the data of the memory 33. On the other hand, the output of the address counter 34 is
Entered as the address of. The data read from the memory 33 is input to A of the data selector 35 and the digital peak detector 36, and the output of the digital peak detector 36 is input to B of the data selector 35. The output of the data selector 35 is input to the display unit 37. Distributor 25, size comparators 26, 27, 29, 30 and digital peak detectors 31, 32
Are controlled by control logic 24. The digital peak detector 36 is controlled by the read controller 38. The address counter 34 is controlled by the control logic 24 and the read controller 38.

Next, the operation of the above embodiment will be described. In the above-described embodiment, the analog signal input from the analog input terminal 21 is converted into an instantaneous value of the analog signal at a period T determined by the output of the sample clock generator 22 in the analog / digital converter 23 and is converted into K-bit digital data. Convert to. In the distributor 25, when four pieces of the K-bit digital data are input, these four pieces of digital data are simultaneously sent to the magnitude comparators 26 and 27 and the A of the data selector 28.
Output to. In the meantime, the next K-bit digital data is input to the distributor 25, and when four pieces of data are input, four pieces of digital data are simultaneously output as in the previous case. That is, 4 pieces of digital data from the distributor 25 have a period of 4T.
Is output at the speed of. The size comparators 26 and 27 are each 2
Of the input digital data, large digital data is output to the size comparator 29, and small digital data is output to the size comparator 30. Further, the size comparator 29 inputs the large digital data of the two inputs to the digital peak detector 31, and the size comparator 30 outputs the small digital data of the two inputs to the digital peak detector 32. In the digital peak detector 31, m pieces of data are sequentially input at each peak detection cycle, the maximum value is detected from the data, and it is output to B of the data selector 28. Similarly digital peak detector
At 32, the minimum value is detected and output to B of the data selector 28. In this way, the data output to B of the data selector 28 is such that the number of digital data input to the distributor 25 in each peak detection cycle is an integer m times the number of data 4 simultaneously output from the distributor 25. Is the maximum and minimum value of.

FIG. 2 shows the relationship between the peak detection period and the number of data input to the distributor 25 within the period when the sample clock period T is 5 nsec. As is clear from this figure, when the peak detection period is 20 nsec or 100 nsec or more, the number of digital data input to the distributor 25 for each peak detection period is an integral multiple of 4. At this time, the data selector 28
The data input to the B is output to the memory 33, and the memory 33
Writes these data to the address determined by the output of the address counter 34 controlled by the control logic 24. After the necessary data is taken into the memory 33, the data is read from the address determined by the output of the address counter 34 controlled by the read controller 38, and is output to the display unit 37 through the A input of the data selector 35.

When the peak detection period is 5nsec, 10nsec, 50nsec, the number of digital data input to the distributor 25 for each peak detection period is not an integral multiple of 4. At this time, the A input data of the data selector 28 is written in the memory 33.
After the necessary data is loaded into the memory 33, the data read from the memory 33 is input to the digital peak detector 36 controlled by the read controller 38. The digital peak detector 36 detects the maximum value and the minimum value from the number of data shown in FIG. 2, and outputs the maximum value and the minimum value to the display section 37 through the B input of the data selector 35.

As described above, according to the above-described embodiment, since the output data of the analog-digital converter 23 is distributed to four by the distributor 25, when the peak detection period is 20 n sec and 100 n sec or more, the sample period is 5 n sec. There is an effect that an inexpensive circuit for obtaining the maximum value and the minimum value can be constructed with a cycle of 4 times 20 nsec. Further, since the digital peak detector 36 only needs to operate at the same speed as the reading of the memory at most, it can be configured by a low speed and inexpensive circuit.

EFFECTS OF THE INVENTION As is apparent from the above embodiment, the present invention inputs a plurality of sequentially captured n digital data to a distributor and detects a maximum value and a minimum value from the n digital data. Since the comparator and the means for detecting the maximum value and the minimum value among the plurality of maximum values and the minimum values sequentially output from the magnitude comparator are provided, the maximum value can be selected from the digital data of n integer multiples. To detect the value and the minimum value, the operating speed is 1 / n of the sample clock, and a low-speed and inexpensive circuit configuration can be achieved. Further, the maximum value and the minimum value are detected from the digital data other than an integral multiple of n by storing the sequentially captured data in the memory and detecting the maximum value and the minimum value when reading from the memory. In order to achieve this, it is possible to realize an excellent waveform storage device that has the same resolution as that when digital peak detection is performed at the same speed as the sample clock, by using the circuit configuration that is at the same speed as the reading of the memory and is therefore slow and inexpensive. .

[Brief description of drawings]

FIG. 1 is a block diagram of a data capturing section in a waveform storage device showing an embodiment of the present invention, FIG. 2 is a diagram showing a relationship between a peak detection period and the number of data in an embodiment of the present invention, and FIG. FIG. 4 is a block diagram of a data capturing section in a conventional waveform storage device, and FIG. 4 is an operation timing chart in the conventional device. 21 ... Analog input terminal, 22 ... Sample clock generator,
23 ... Analog / digital converter, 24 ... Control logic, 25
… Distributor, 26,27,29,30… Size comparator, 28… Data selector, 31,32… Digital peak detector, 33… Memory, 34
... Address counter, 35 ... Data selector, 36 ... Digital peak detector, 37 ... Display unit, 38 ... Read controller.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-56-54366 (JP, A) JP-A-54-126442 (JP, A) JP-A-58-106637 (JP, A) JP-A-59- 148880 (JP, A) JP 63-304318 (JP, A) JP 2-155032 (JP, A) JP 58-47661 (JP, B2)

Claims (1)

[Claims] 1. An analog / digital converter for sampling an analog signal with a sample clock to convert it into a digital signal, and serial digital data sequentially output from the analog / digital converter into n parallel digital data. And the n pieces of data output from the distributor are grouped into two at the first stage and compared in magnitude, and at the second stage and thereafter, large values obtained in the previous stage are compared. , A multi-level magnitude comparator that obtains a large value and a small value by grouping them into small values and comparing the magnitude, and a large value and a small value that are sequentially output from this multi-step magnitude comparator. Waveform storage device including means for detecting maximum and minimum values, and memory for storing the maximum and minimum values output from the means for detecting maximum and minimum values