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JPH068240B2 - Thin film manufacturing method - Google Patents
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JPH068240B2 - Thin film manufacturing method - Google Patents

Thin film manufacturing method

Info

Publication number
JPH068240B2
JPH068240B2 JP33245288A JP33245288A JPH068240B2 JP H068240 B2 JPH068240 B2 JP H068240B2 JP 33245288 A JP33245288 A JP 33245288A JP 33245288 A JP33245288 A JP 33245288A JP H068240 B2 JPH068240 B2 JP H068240B2
Authority
JP
Japan
Prior art keywords
substrate
thin film
ions
ion source
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP33245288A
Other languages
Japanese (ja)
Other versions
JPH02180793A (en
Inventor
文彦 大谷
真 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP33245288A priority Critical patent/JPH068240B2/en
Publication of JPH02180793A publication Critical patent/JPH02180793A/en
Publication of JPH068240B2 publication Critical patent/JPH068240B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は、基板上にGaAs等の薄膜を形成する方法に
関する。
The present invention relates to a method for forming a thin film of GaAs or the like on a substrate.

<従来の技術> イオンビーム蒸着法で、GaAs基板上にGaAs薄膜
を形成する場合の製造手順を、以下に説明する。
<Prior Art> A manufacturing procedure for forming a GaAs thin film on a GaAs substrate by an ion beam evaporation method will be described below.

GaAs基板を真空槽内に入れ、まずGaAs基板を80
0〜900℃で10時間加熱して基板表面のサーマルクリーニ
ングを行なう。これは、前処理工程において、基板表面
に形成された酸化膜あるいは吸着した汚染物質を取り除
くために行われ、そしてこのクリーニングが終了した
後、基板表面にGaおよびAsそれぞれのイオンを所定
エネルギに加速して照射することによって、その基板表
面上にGaAs薄膜を成長させる。
Place the GaAs substrate in the vacuum chamber and first place the GaAs substrate at 80
Thermally clean the substrate surface by heating at 0-900 ° C for 10 hours. This is performed to remove the oxide film formed on the substrate surface or the adsorbed contaminants in the pretreatment step, and after the cleaning is completed, the Ga and As ions are accelerated to a predetermined energy on the substrate surface. Then, irradiation is performed to grow a GaAs thin film on the surface of the substrate.

また、Si基板上にGaAs薄膜をエピタキシャル成長
させる場合には、従来、MBE法による2段階成長法等
が採用されている。その製造手順を、以下に説明する。
Further, in the case of epitaxially growing a GaAs thin film on a Si substrate, a two-step growth method based on the MBE method has been conventionally used. The manufacturing procedure will be described below.

まず、先の手順と同様に、Si基板を800〜900℃で1時
間程度加熱してサーマルクリーニングを施し、次いで、
基板の温度を400℃程度に設定し、この状態で基盤表面
にGaおよびAsそれぞれの分子線を照射して、アモル
ファスもしくはある程度結晶化したバッファ層を積層し
た後、基板の温度を500〜700℃に設定し、この状態で基
板表面にGaおよびAsそれぞれの分子線を照射して、
バッファ層上にGaAs薄膜をエピタキシャル成長させ
る。
First, similar to the above procedure, the Si substrate is heated at 800 to 900 ° C. for about 1 hour to perform thermal cleaning, and then,
The temperature of the substrate is set to about 400 ° C, and the surface of the substrate is irradiated with molecular beams of Ga and As in this state to deposit an amorphous or crystallized buffer layer to some extent, and then the substrate temperature is set to 500 to 700 ° C. , And in this state, the surface of the substrate is irradiated with molecular beams of Ga and As respectively,
A GaAs thin film is epitaxially grown on the buffer layer.

<発明が解決しようとする課題> ところで、上述の従来の手順によれば、いずれも、薄膜
製造過程において基板の温度を変化させるため、基板に
そり、転位の成長等の劣化が生じる虞れがあった。
<Problems to be Solved by the Invention> By the way, according to the above-mentioned conventional procedure, since the temperature of the substrate is changed in the thin film manufacturing process, there is a possibility that the substrate is warped and deterioration such as dislocation growth occurs. there were.

本発明の目的は、基板の劣化等を招くことなく、所望の
薄膜を製造することのできる方法を提供することにあ
る。
An object of the present invention is to provide a method capable of producing a desired thin film without causing deterioration of a substrate.

<課題を解決するための手段> 本発明の薄膜製造方法は、一種もしくは複数種の蒸着材
料を真空雰囲中で加熱することにより蒸発させ、その蒸
発粒子それぞれを、イオン化し、所定強さの電場で加速
して基板表面に照射することによって、その基板表面上
に薄膜を形成する方法において、薄膜を形成すべき基板
表面に、真空雰囲中で薄膜を形成する蒸着材料のうち少
なくとも一種の材料の蒸発粒子のイオンを、成膜時とは
異なる強さの電場で加速して照射した後、成膜を行なう
ことを特徴としている。
<Means for Solving the Problems> In the thin film manufacturing method of the present invention, one or more kinds of vapor deposition materials are heated to evaporate in a vacuum atmosphere, and each of the vaporized particles is ionized to have a predetermined strength. In a method of forming a thin film on a substrate surface by irradiating the substrate surface by accelerating with an electric field, at least one of vapor deposition materials for forming a thin film on a substrate surface on which a thin film is to be formed in a vacuum atmosphere. The feature of the present invention is that the film formation is performed after the ions of evaporated particles of the material are accelerated and irradiated with an electric field having a strength different from that during film formation.

<作用> 一般に、基板表面に数kV程度の加速電圧で加速したイ
オンを照射すると、その基板の表面層はイオンによって
スパッタリングされることが知られている。従って、蒸
発粒子イオンの加速電場の強さ、つまり加速電圧を数k
V程度に設定すれば、基板の温度に関係なく、基板表面
上の酸化膜等を蒸発粒子イオンによるスパッタクリーニ
ングにより除去することが可能になる。
<Operation> It is generally known that when a substrate surface is irradiated with ions accelerated by an acceleration voltage of about several kV, the surface layer of the substrate is sputtered by the ions. Therefore, the strength of the accelerating electric field of evaporated particle ions, that is, the accelerating voltage is several k
When set to about V, the oxide film and the like on the surface of the substrate can be removed by sputter cleaning with evaporated particle ions regardless of the temperature of the substrate.

また、ある一定温度の基板においては、薄膜がエピタキ
シャル成長するか否かは、蒸発粒子が基板に衝突すると
きのエネルギの大きさに左右されることが知られてい
る。すなわち、衝突時のエネルギが小さいと、得られる
膜はアモルファスとなる。従って、加速電圧を、エピタ
キシャル薄膜を成長させるのに適した値よりも低い値に
設定すれば、基板の温度を変化させることなく、基板表
面上にアモルファスもしくはある程度結晶化した層を積
層することが可能になる。
Further, it is known that, on a substrate at a certain temperature, whether or not a thin film is epitaxially grown depends on the amount of energy when vaporized particles collide with the substrate. That is, when the energy at the time of collision is small, the obtained film becomes amorphous. Therefore, if the accelerating voltage is set to a value lower than a value suitable for growing an epitaxial thin film, an amorphous or partially crystallized layer can be stacked on the substrate surface without changing the temperature of the substrate. It will be possible.

<実施例> 本発明の実施例を、以下、図面に基づいて説明する。<Examples> Examples of the present invention will be described below with reference to the drawings.

図面は、本発明方法の実施に使用する薄膜製造装置の概
略構成図である。
The drawing is a schematic diagram of a thin film manufacturing apparatus used for carrying out the method of the present invention.

真空槽(図示せず)内に二つのイオン源Gaイオン源1お
よびAsイオン源2が配設されている。
Two ion sources Ga ion source 1 and As ion source 2 are arranged in a vacuum chamber (not shown).

その各イオン源1,2はそれぞれ蒸気発生部11,21
およびイオン化部12,22によって構成されており、
その各出力イオンは、ともに同一の基板Sに到達するよ
う構成されている。
The ion sources 1 and 2 are steam generators 11 and 21, respectively.
And the ionization units 12 and 22,
Each of the output ions is configured to reach the same substrate S.

各イオン源1および2の上方には、それぞれ加速電極1
3および23が配設されている。各加速電極13,23
と基板Sとの間には、それぞれシャッタ14および24
が配設されており、この各シャッタ14,24の操作に
より各イオン源1,2からのイオンの基板Sへの進行を
選択的に遮断できるようになっている。
Above each of the ion sources 1 and 2 is an accelerating electrode 1 respectively.
3 and 23 are provided. Each acceleration electrode 13, 23
And the substrate S between the shutters 14 and 24, respectively.
Is provided, and the operation of the shutters 14 and 24 can selectively block the progress of ions from the ion sources 1 and 2 to the substrate S.

蒸気発生部11,21は、蒸着材料GaまたはAsを収
容したるつぼと、その側方周辺を囲ってなる加熱用フィ
ラメント等を備え、るつぼを加熱用フィラメントにより
加熱することによって内部の蒸着材料を蒸気化するよう
構成されている。
The vapor generating units 11 and 21 are provided with a crucible containing the vapor deposition material Ga or As and a heating filament surrounding the lateral periphery thereof, and vaporize the vapor deposition material inside by heating the crucible with the heating filament. It is configured to change.

イオン化部12,22はイオン化フィラメントおよびグ
リッド等を備え、イオン化フィラメントが発生する熱電
子をグリッドにより蒸気発生部11,21からの蒸気へ
と引き止せ衝突させることによって、その蒸気を陽イオ
ン化するよう構成されている。
The ionization units 12 and 22 include an ionization filament and a grid, and are configured to positively ionize the vapor by causing the thermoelectrons generated by the ionization filament to stop and collide with the vapor from the vapor generation units 11 and 21 by the grid. Has been done.

基板Sおよび加速電極13,23は接地電位に置かれて
いる。また、各加速電極13,23と各イオン源1,2
との間には、それぞれ可変直流電源15および25が設
けられており、イオン源1,2が正電位になるよう、両
者間にそれぞれ任意の大きさの電位差を付与することが
できる。そして、この電位差によって形成される電場に
よって、イオン化部12,22において陽イオン化され
た蒸気は、それぞれ加速されて基板S表面に衝突する。
The substrate S and the acceleration electrodes 13 and 23 are placed at the ground potential. In addition, each acceleration electrode 13, 23 and each ion source 1, 2
Variable DC power supplies 15 and 25 are provided between the two, respectively, and an arbitrary potential difference can be applied between the ion sources 1 and 2 so that they have a positive potential. Then, by the electric field formed by this potential difference, the vapors that have been positively ionized in the ionization units 12 and 22 are accelerated and collide with the surface of the substrate S.

なお、基板Sは、例えば加熱器および熱電対等を備えた
ホルダ(図示せず)によって、真空槽内の所定位置に保持
されるとともに、所定温度、例えば500〜700℃程度の温
度に維持される。
The substrate S is held at a predetermined position in the vacuum chamber by a holder (not shown) equipped with, for example, a heater and a thermocouple, and is maintained at a predetermined temperature, for example, about 500 to 700 ° C. .

以上説明した装置を使用して、GaAs基板上にGaA
s薄膜を形成する場合の手順を説明する。
Using the device described above, GaA is formed on a GaAs substrate.
The procedure for forming a thin film will be described.

まず、基板Sの温度を500〜700℃程度の成膜に適した温
度に保ち、かつ、Gaイオン源1およびAsイオン源2
をともに駆動した状態で、Asイオン源2側のシャッタ
24だけを開き、基板S表面に加速されたAsイオンを
照射する。このときのAsイオンの加速電圧は数kV程
度とする。これにより、基板Sの表面はAsイオンによ
ってスパッタされ、数分間のAsイオン照射で基板Sの
表面層は100Å程度エッチングされる。このエッチング
により、基板Sの表面には、原子層レベルの平滑な面が
現れ、前工程において基板S表面に付着した酸化膜等は
充分に洗浄されたことになる。
First, the temperature of the substrate S is kept at a temperature suitable for film formation at about 500 to 700 ° C., and the Ga ion source 1 and the As ion source 2 are used.
In the state where both are driven, only the shutter 24 on the As ion source 2 side is opened, and the surface of the substrate S is irradiated with accelerated As ions. The acceleration voltage of As ions at this time is about several kV. As a result, the surface of the substrate S is sputtered with As ions, and the surface layer of the substrate S is etched by about 100Å by irradiation with As ions for several minutes. By this etching, a smooth surface at the atomic layer level appears on the surface of the substrate S, and the oxide film and the like attached to the surface of the substrate S in the previous step are sufficiently cleaned.

以上の洗浄工程が終了した後、各イオン源1,2の加速
電圧を、それぞれ通常の成膜時の所定値に設定し、さら
にGaイオン源1側のシャッタ14を開いて、基板S表
面にGaおよびAsイオンを加速して照射し、基板S表
面上にGaAs薄膜を形成する。
After the above cleaning process is completed, the acceleration voltage of each of the ion sources 1 and 2 is set to a predetermined value during normal film formation, and the shutter 14 on the Ga ion source 1 side is opened to expose the surface of the substrate S. Ga and As ions are accelerated and irradiated to form a GaAs thin film on the surface of the substrate S.

ここで、成膜時のGaおよびAsイオンの加速電圧は、
各イオンが基板表面をマイグレートしたり、また、基板
表面の一部をスパッタし得る程度のエネルギになるよう
に、適宜に設定する。なお、成膜時におけるAsイオン
の基板への衝突エネルギは、当然のことながら基板エッ
チング時のエネルギよりも小さく、従って、成膜時のA
sイオンの加速電圧は、基板洗浄時の加速電圧よりも低
い値になる。
Here, the acceleration voltage of Ga and As ions during film formation is
The energy is set appropriately so that each ion migrates to the surface of the substrate or has such energy that it can sputter a part of the surface of the substrate. The energy of collision of As ions with the substrate during film formation is naturally smaller than the energy during substrate etching.
The acceleration voltage of s ions has a value lower than the acceleration voltage at the time of cleaning the substrate.

次に、先の実施例と同じ装置を使用して、Si基板上に
GaAs薄膜をエピタキシャル成長させる場合の手順を
説明する。
Next, a procedure for epitaxially growing a GaAs thin film on a Si substrate using the same apparatus as that of the previous embodiment will be described.

まず、基板Sを500〜700℃程度の成膜に適した温度に保
ち、かつ、Gaイオン源1およびAsイオン源2をとも
に駆動した状態で、先の手順と同様に、Asイオン源2
側のシャッタ24だけを開き、基板S表面に数kVの加
速電圧で加速されたAsイオンを照射して、基板S表面
の洗浄を行なう。
First, while keeping the substrate S at a temperature suitable for film formation at about 500 to 700 ° C. and driving both the Ga ion source 1 and the As ion source 2, the As ion source 2 is subjected to the same procedure as described above.
Only the side shutter 24 is opened, the surface of the substrate S is irradiated with As ions accelerated by an acceleration voltage of several kV, and the surface of the substrate S is cleaned.

次いで、Gaイオン源1およびAsイオン源2の加速電
圧を、それぞれ1kV以下に設定し、さらにGaイオン
源1側のシャッタ14を開いて、基板S表面にGaおよ
びAsイオンを照射する。このときの各イオンの基板S
への衝突エネルギは小さく、基板S表面上には、アモル
ファスもしくはある程度結晶化した層、つまりGaAs
バッファ層が積層されることになる。
Next, the acceleration voltages of the Ga ion source 1 and the As ion source 2 are set to 1 kV or less, respectively, and the shutter 14 on the Ga ion source 1 side is opened to irradiate the surface of the substrate S with Ga and As ions. Substrate S of each ion at this time
The collision energy is small, and the surface of the substrate S is amorphous or crystallized to some extent, that is, GaAs.
A buffer layer will be laminated.

次いで、Gaイオン源1およびAsイオン源2の加速電
圧を、それぞれ、先のバッファ層を積層した際の加速電
圧よりも高い値、つまり、GaAs薄膜をエピタキシャ
ル成長させるのに適した値に設定し、この状態で、基板
S表面にGaおよびAsイオンを照射することによっ
て、基板S表面上のバッファ層上にGaAs薄膜をエピ
タキシャル成長させる。
Then, the acceleration voltage of the Ga ion source 1 and the As ion source 2 is set to a value higher than the acceleration voltage at the time of stacking the buffer layer, that is, a value suitable for epitaxially growing a GaAs thin film, In this state, the surface of the substrate S is irradiated with Ga and As ions to epitaxially grow a GaAs thin film on the buffer layer on the surface of the substrate S.

なお、この手順においても、GaAs薄膜をエピタキシ
ャル成長させる際のAsイオンの加速電圧は、基板洗浄
時の加速電圧よりも低い値になることは言うまでもな
い。
In this procedure as well, it goes without saying that the accelerating voltage of As ions when epitaxially growing the GaAs thin film is lower than the accelerating voltage at the time of cleaning the substrate.

以上はGaAs薄膜形成に本発明を適用した例について
説明したが、本発明は、例えばSi薄膜等、他の材料の
薄膜形成にも適用可能である。
An example in which the present invention is applied to the formation of a GaAs thin film has been described above, but the present invention can also be applied to the formation of a thin film of another material such as a Si thin film.

<発明の効果> 以上説明したように、本発明によれば、基板表面に、真
空雰囲中で薄膜を形成する材料の蒸発粒子イオンを、成
膜時よりも強い電場もしくは弱い電場で加速して照射し
た後、成膜を行なうので、基板の温度を変化させること
なく、基板表面に付着した酸化物等の除去、バッファ層
の積層等を行なうことができ、これにより、基板の品質
を劣化させることなく所望の薄膜を形成することが可能
になる。
<Effects of the Invention> As described above, according to the present invention, evaporated particle ions of a material forming a thin film on a substrate surface in a vacuum atmosphere are accelerated by a stronger electric field or a weaker electric field than during film formation. After the irradiation, the film is formed, so that the oxide etc. adhering to the substrate surface can be removed and the buffer layer can be laminated without changing the substrate temperature, which deteriorates the quality of the substrate. It is possible to form a desired thin film without performing the above.

さらに、基板温度を高温、例えば700℃以上に保つ必要
がなく、基板ホルダ等における基板の加熱容量を従来に
比して軽減できるという効果もある。
Further, it is not necessary to keep the substrate temperature at a high temperature, for example, 700 ° C. or higher, and the heating capacity of the substrate in the substrate holder or the like can be reduced as compared with the conventional case.

【図面の簡単な説明】[Brief description of drawings]

図面は、本発明方法の実施に使用する装置の概略構成図
である。 1・・・Gaイオン源 2・・・Asイオン源 11,21・・・蒸気発生部 12,22・・・イオン化部 13,23・・・加速電極 S・・・基板。
The drawing is a schematic configuration diagram of an apparatus used for carrying out the method of the present invention. 1 ... Ga ion source 2 ... As ion source 11,21 ... Steam generation part 12,22 ... Ionization part 13,23 ... Accelerating electrode S ... Substrate.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一種もしくは複数種の蒸着材料を、真空雰
囲中で加熱することにより蒸発させ、その蒸発粒子それ
ぞれを、イオン化し、所定強さの電場で加速して基板表
面に照射することによって、その基板表面上に薄膜を形
成する方法において、薄膜を形成すべき基板表面に、真
空雰囲中で上記蒸着材料のうち少なくとも一種の材料の
蒸発粒子のイオンを、成膜時とは異なる強さの電場で加
速して照射した後、成膜を行なうことを特徴とする、薄
膜製造方法。
1. A method of evaporating one or a plurality of kinds of vapor deposition materials by heating in a vacuum atmosphere, ionizing each of the vaporized particles, accelerating the vaporized particles with an electric field of a predetermined strength, and irradiating the substrate surface. According to the method for forming a thin film on the surface of a substrate, ions of evaporated particles of at least one of the above vapor deposition materials are different from those at the time of film formation on the surface of the substrate on which the thin film is to be formed. A method for producing a thin film, which comprises accelerating and irradiating with a strong electric field and then performing film formation.
JP33245288A 1988-12-28 1988-12-28 Thin film manufacturing method Expired - Lifetime JPH068240B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33245288A JPH068240B2 (en) 1988-12-28 1988-12-28 Thin film manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33245288A JPH068240B2 (en) 1988-12-28 1988-12-28 Thin film manufacturing method

Publications (2)

Publication Number Publication Date
JPH02180793A JPH02180793A (en) 1990-07-13
JPH068240B2 true JPH068240B2 (en) 1994-02-02

Family

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Country Status (1)

Country Link
JP (1) JPH068240B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3023649U (en) * 1995-10-09 1996-04-23 槌谷印刷株式会社 Direct mail envelope
JP3035141U (en) * 1996-08-27 1997-03-11 株式会社東京セロレーベル Envelope

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3023649U (en) * 1995-10-09 1996-04-23 槌谷印刷株式会社 Direct mail envelope
JP3035141U (en) * 1996-08-27 1997-03-11 株式会社東京セロレーベル Envelope

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JPH02180793A (en) 1990-07-13

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