JPH0682628B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to the formation of a fine pattern on a semiconductor substrate in the technical field of LSI and the like, and more particularly to a method for forming electrodes.

(Prior Art) In recent years, semiconductor technology has entered the era of VLSI, and the dimensions of elements, wirings, and the like have been further miniaturized in order to achieve high integration in a small area.

Ohmic electrodes in such a semiconductor device (hereinafter,
(Referred to simply as “electrode”) is, for example, as shown in FIG.
Although the opening 3 is selectively provided in the insulating film 2 on one main surface of the substrate 1 and the Al alloy wiring 4 is vapor-deposited on the opening 3 to form an electrode,
With the miniaturization of integrated devices, Al in the opening 3
Problems such as step coverage (step coverage) of the alloy wiring 4, disconnection, and increase in contact resistance have occurred.

In order to improve this, as shown in FIGS. 3 (a) to 3 (c), first, a polycrystalline Si film 5 having good step coverage is deposited at 615 ° C. by a low pressure CVD method, as shown in FIGS.
After this is doped with impurities to form a conductor (FIG. 3 (a)), it is etched back to fill the opening 3 with the polycrystalline Si film 5 and flatten it as shown in FIG. 3 (b). It has been proposed to provide the Al alloy wiring 4 as shown in FIG.

(Problems to be Solved by the Invention) However, when the Si substrate 1 mounted on a boat is put into a low pressure CVD apparatus to form the polycrystalline Si film 5, the Si substrate is exposed to high temperature air. The surface of 1 oxidizes, 20 to 100
About Å oxide film grows. Therefore, the contact resistance between the Si substrate 1 and the polycrystalline Si film 5 may be higher than in the conventional case or may be completely out of contact with the contact resistance, resulting in a decrease in manufacturing yield. Note that, in general, the Si substrate below the above-mentioned opening of the integrated circuit has a high impurity concentration and is easily oxidized. Therefore, it is difficult to avoid the problem of electrode contact described above.

The present invention solves the above-mentioned conventional drawbacks of the semiconductor device, that is, the increase or failure of the electrode contact resistance due to the oxide film growth of the opening provided in the Si substrate, and the low resistance contact of the electrode and the Al alloy wiring. It is an object of the present invention to provide a method for manufacturing a semiconductor device with improved step coverage.

(Means for Solving Problems) In order to achieve the above object, conventionally, in order to achieve good step coverage, pinhole-free, etc., an opening portion selectively provided in an insulating film on a Si substrate, While the polycrystalline Si film was deposited at a high temperature of 600 ° C. or higher where the Si substrate is easily oxidized, the present invention first forms the first polycrystalline Si film thin at a relatively low temperature of 500 ° C. or lower. Then, at a high temperature of 600 ° C. or higher, deposition is performed by a two-step operation of forming a thick second polycrystalline Si film so as to substantially fill the opening.

(Operation) According to the present invention, the first polycrystal deposited at a relatively low temperature
Although the Si film is somewhat inferior in crystal uniformity or characteristics such as pinholes, the growth of the oxide film on the Si substrate can be sufficiently prevented, and the second polycrystalline Si film deposited thickly is
Since it has characteristics such as good step coverage and pinhole-free property, it is possible to form an electrode wiring having good contact coverage without worrying about contact resistance.

(Examples) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing a manufacturing process of an embodiment of the present invention. First, as shown in FIG. 1 (a), the present invention is performed on a Si substrate 6 having a specific resistance of 8 to 12 Ω · cm, a conductivity type of P type and a (100) plane by a low pressure CVD method to form a phosphosilicate glass. Insulating film 7
Glass flow of PH _{3 at} a temperature of 1000 ℃, deposited to a thickness of 0.8 μm
Perform averaging heat treatment for 30 minutes. Next, a resist pattern is formed by a photo process and dry etching is performed to form an opening 8 in the phosphosilicate glass insulating film 7 to expose the surface of the Si substrate 6. This opening 8
In addition, by decomposing SiH ₄ at a relatively low temperature of 450 ℃, polycrystalline Si
The film 9 is formed to a thickness of 300Å. In this case, the thickness of the polycrystalline Si film 9 may be any thickness required to prevent the surface of the Si substrate 6 from being oxidized. Further, the formation temperature of the polycrystalline Si film 9 is preferably 500 ° C. or lower.

Next, as shown in FIG. 1 (b), the polycrystalline Si film 9 is formed on the polycrystalline Si film 9 by a low pressure CVD method in SiH ₄ gas at a temperature of 615 ° C.
A film 10 is deposited to a thickness of 0.4 to 0.8 μm so as to fill the opening 8 and is doped with an impurity of phosphorus (P) at a temperature of 950 ° C. in a POCl ₃ atmosphere. It should be noted that the growth temperature of polycrystalline Si by the above-mentioned CVD method is required to be 600 ° C. or higher, considering that the sheet resistance of the polycrystalline Si film 10 is 25 Ω / port. Further, the doping of the impurity (P) may be performed in PH ₃ gas, or may be performed by an ion implantation method. In the case of using the ion implantation method, it is preferable that the dose is 2 × 10 ¹⁶ cm ^-2 , the impurity ions are P ⁺ , and the accelerating voltage is about 100 KeV. In the case of ion implantation, the etching rate of the polycrystalline Si film 10 is rapidly increased due to implantation damage.
Annealing treatment in N ₂ gas at ℃ for 10 minutes is required.

Next, a photoresist having a thickness of 1.2 μm is formed on the polycrystalline Si film 10.
To flatten the surface, and after baking, etch back by dry etching in SF ₆ / CCl ₄ gas under the condition that the etching ratio of the polycrystalline Si film 10 to the photoresist is 1: 1, As shown in FIG. 1C, the polycrystalline Si films 9 and 10 in the opening 8 are left.

Next, as shown in FIG. 1D, Al-Si is used as the electrode wiring 11.
After the alloy is deposited by sputtering to a thickness of 1.0 μm, Al wiring is selectively formed by photoetching.
Firing is performed in a mixed atmosphere of H ₂ and N ₂ for 5 minutes to complete the electrode forming step of the semiconductor device of the present invention.

As described above, the feature of the present invention is that the first polycrystalline Si film 9 is thinly deposited on the exposed surface of the semiconductor substrate in the opening and the surface of the insulating layer at the growth temperature of 500 ° C. or lower, and then the The second polycrystalline Si film 10 is thickly deposited at a growth temperature of 600 ° C. or higher to form an electrode portion so as to substantially fill the opening, and a conventional example not having the constitution of this feature. According to the present invention, the opening 8 having a size of 1.5 μm × 1.5 μm is 400
As a result of comparing the contact states of the electrodes formed individually, the contact resistance per opening 8 of the present invention is 25 to 30 Ωcm ^-2.
This is the same value as in the case of the conventional metal wiring in which the opening 8 is not filled with the polycrystalline Si film. Therefore, the present invention aims to improve the step coverage of the opening while maintaining good contact characteristics. Become.

(Effects of the Invention) As is apparent from the above description, the present invention provides a first polycrystalline Si film formed at a temperature of 500 ° C. or lower in the opening of the electrode contact portion and having a temperature of 600 ° C. or higher. The second polycrystalline Si film formed at a temperature is buried and an Al wiring is formed on the second polycrystalline Si film, which improves the conventional problems of step coverage of an opening, disconnection, and increase of contact resistance due to pattern miniaturization. ,
Therefore, it can greatly contribute to the miniaturization of the device pattern (1.5 μm, less than the rule).

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a manufacturing process of an embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing process of a conventional example, and FIG. 3 is a sectional view of another conventional example. Is. 6 ... Si substrate, 7 ... insulating film, 8 ... opening, 9 ...
(First) polycrystalline Si film (forming temperature of 500 ° C or less), 10 ...
(Second) Polycrystalline Si film (forming temperature 600 ℃ or higher), 11 ……
Electrode wiring.

Claims (1)

[Claims] 1. An opening is selectively formed at a desired position of an insulating layer formed on one main surface of a semiconductor substrate, and the surface of the insulating layer including the surface of the semiconductor substrate exposed at the opening has a thickness of 50.
A step of thinly forming the first polycrystalline silicon film at a deposition temperature of 0 ° C. or lower, and a low pressure CVD at a temperature of 600 ° C. or higher so as to substantially fill the opening on the first polycrystalline silicon film.
A step of depositing a second polycrystalline silicon film by a method and doping impurities, and applying a photoresist on the second polycrystalline silicon film, and then forming the photoresist and the second polycrystalline silicon film. Etching back under the condition that the dry etching ratio is 1: 1 and leaving the first and second polycrystalline silicon films only in the opening with the opening being substantially filled; And a step of forming a metal wiring connected to the substantially buried second polycrystalline silicon film.