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JPH0682692B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0682692B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0682692B2
JPH0682692B2 JP3696487A JP3696487A JPH0682692B2 JP H0682692 B2 JPH0682692 B2 JP H0682692B2 JP 3696487 A JP3696487 A JP 3696487A JP 3696487 A JP3696487 A JP 3696487A JP H0682692 B2 JPH0682692 B2 JP H0682692B2
Authority
JP
Japan
Prior art keywords
conductor layer
insulating substrate
back surface
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3696487A
Other languages
Japanese (ja)
Other versions
JPS63204663A (en
Inventor
雅夫 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3696487A priority Critical patent/JPH0682692B2/en
Publication of JPS63204663A publication Critical patent/JPS63204663A/en
Publication of JPH0682692B2 publication Critical patent/JPH0682692B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明の半導体装置の製造方法に関し、特に絶縁性基板
上に形成された半導体素子の少なくとも一つの電極を貫
通孔を介して裏面に引き出した半導体装置の製造方法に
関するものである。
TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device of the present invention, and in particular, at least one electrode of a semiconductor element formed on an insulating substrate is drawn out to the back surface through a through hole. The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

絶縁性基板上に形成された半導体素子、例えばGaAsの電
界効果トランジスタ(以降FETと称す)では、絶縁性基
板の熱抵抗を下げるためにその厚さを、例えば20〜30μ
m程度と薄くし、しかも高周波におけるソース・インダ
クタンスを減少させるために、ソース電極直下の絶縁性
基板に貫通孔を開け、裏面の導体層と接続してソース電
極を裏面から引出す構造を用いている。
In a semiconductor element formed on an insulating substrate, for example, a GaAs field effect transistor (hereinafter referred to as FET), its thickness is, for example, 20 to 30 μm in order to reduce the thermal resistance of the insulating substrate.
In order to reduce the thickness to about m and to reduce the source inductance at high frequencies, a structure is used in which a through hole is opened in the insulating substrate immediately below the source electrode and the source electrode is pulled out from the back side by connecting to the conductor layer on the back side. .

第3図(a)〜(e)は従来の半導体装置の製造方法の
第1の例を説明するための工程順に示した半導体チップ
の断面図である。
3 (a) to 3 (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first example of a conventional method for manufacturing a semiconductor device.

この例は、先ず、第3図(a)に示すように、厚さ400
μmの絶縁性基板1a表面の能動層2上にソース3,ゲート
4及びドレイン5を形成した後絶縁性基板1a表面を絶縁
膜6で覆い、絶縁性基板1bの裏面を研磨して厚さを100
μm程度の厚さにした後、その表面をホトレジスト膜9
によって石英板10に貼付ける。
In this example, first, as shown in FIG.
After forming the source 3, the gate 4 and the drain 5 on the active layer 2 on the surface of the insulating substrate 1a of μm, the surface of the insulating substrate 1a is covered with the insulating film 6, and the back surface of the insulating substrate 1b is polished to reduce the thickness. 100
After having a thickness of about μm, the surface of the photoresist film 9
Affix to the quartz plate 10 by.

次に、第3図(b)に示すように、絶縁性基板1bの裏面
を化学蝕刻法等によりエッチングして、20〜30μm程度
の厚さの絶縁性基板1にする。
Next, as shown in FIG. 3 (b), the back surface of the insulating substrate 1b is etched by chemical etching or the like to form the insulating substrate 1 having a thickness of about 20 to 30 μm.

次に、第3図(c)に示すように、ホトリソグラフィ法
等により絶縁性基板1に選択的に貫通孔A′及びスクラ
イブ溝B′を形成する。
Next, as shown in FIG. 3C, a through hole A ′ and a scribe groove B ′ are selectively formed in the insulating substrate 1 by a photolithography method or the like.

次に、第3図(d)に示すように、メッキ用の導体層1
2′を絶縁性基板1裏面に形成した後、スクライブ溝の
部分にホトレジスト膜13を形成し更にメッキによりAu等
からなる導体層14′を形成する。
Next, as shown in FIG. 3 (d), the conductor layer 1 for plating
After forming 2'on the back surface of the insulating substrate 1, a photoresist film 13 is formed in the scribe groove portion, and a conductor layer 14 'made of Au or the like is formed by plating.

最後に、ホトレジスト膜13を除去した後スクライブ線の
部分で半導体チップに分割し、更にホトレジスト膜9を
除去して石英板10から半導体チップを剥すことにより、
第3図(c)に示すようなFETを含む半導体装置ができ
る。
Finally, after removing the photoresist film 13, the semiconductor chip is divided at the scribe line, and the photoresist film 9 is further removed to peel the semiconductor chip from the quartz plate 10.
A semiconductor device including a FET as shown in FIG. 3 (c) can be obtained.

第4図は従来の半導体装置の製造方法の第2の例を説明
するための半導体チップの断面図である。
FIG. 4 is a sectional view of a semiconductor chip for explaining a second example of the conventional method for manufacturing a semiconductor device.

この例は、第1の例における第3図(b)に示したよう
に絶縁性基板1に貫通孔A′及びスクライブ溝B′を形
成した後、第4図に示すように、メッキ用の導体層12′
を形成し、先ず、貫通孔A′の部分を開孔したホトレジ
スト膜13′で裏面を覆ってから貫通孔A′の部分にメッ
キによりAu等からなる導体層を形成し、次にホトレジス
ト膜13′を除去して再びスクライブ溝の部分を除き裏面
にAu等のメッキによる導体層を形成することによってメ
ッキによる裏面の導体層14′をつくる。この第2の例
は、先ず貫通孔の部分のみにメッキによる導体層を形成
し、次に裏面全体に再びメッキによる導体層を形成する
という2段階により裏面の導体層14′を形成するので、
貫通孔が狭くなってもその部分にも均一にメッキによる
導体層14′ができる。
In this example, as shown in FIG. 3 (b) in the first example, after forming the through hole A ′ and the scribe groove B ′ in the insulating substrate 1, as shown in FIG. Conductor layer 12 '
First, the back surface is covered with a photoresist film 13 'in which the through holes A'are opened, and then a conductor layer made of Au or the like is formed on the through holes A'by plating, and then the photoresist film 13' is formed. ′ Is removed and the scribe groove portion is removed again to form a conductor layer by plating with Au or the like on the back surface to form a conductor layer 14 ′ on the back surface by plating. In this second example, the conductor layer 14 'on the back surface is formed by the two steps of first forming the conductor layer by plating only on the through-hole portion and then again forming the conductor layer by plating on the entire back surface.
Even if the through hole is narrowed, a conductor layer 14 'can be uniformly plated on that portion.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、絶縁性基板表面に形
成した所定のパターンの第1の導体層の上に開孔部を備
えた絶縁膜を前記絶縁性基板表面上に形成する工程、前
記絶縁膜上に前記開孔部を通して第1の導体層と接続し
た第2の導体層を形成する工程、前記絶縁性基板に裏面
から前記第1の導体層に至る貫通孔を形成する工程及び
該貫通孔を充填する第3の導体層をメッキにより形成す
る工程を含み、前記第1の導体層に接続されかつ前記絶
縁性基板裏面に至る引出し用の第3の導体層を形成して
成る。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film having openings on a surface of the insulating substrate, the insulating film having openings on a first conductor layer having a predetermined pattern formed on the surface of the insulating substrate. Forming a second conductor layer connected to the first conductor layer through the opening on the insulating film, forming a through hole from the back surface to the first conductor layer in the insulating substrate, and The method includes a step of forming a third conductor layer that fills the through hole by plating, and forms a third conductor layer that is connected to the first conductor layer and extends to the back surface of the insulating substrate.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(g)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図である。
1A to 1G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

この実施例は、先ず、第1図(a)に示すように、厚さ
400μmの絶縁性基板1a表面の能動層2上にソース3,ゲ
ート4及びドレインを形成した後、ソース3上に開孔部
を有する絶縁膜6及びポリイミド膜7を順次形成する。
In this embodiment, first, as shown in FIG.
After the source 3, the gate 4 and the drain are formed on the active layer 2 on the surface of the insulating substrate 1a having a thickness of 400 μm, the insulating film 6 having the openings and the polyimide film 7 are sequentially formed on the source 3.

次に、第1図(b)に示すように、厚さが2000Å程度の
Ti層からなりかつ開孔部を通じてソース3と接続された
導体層8をポリイミド層7上に形成した後、ホトレジス
ト膜9を介して石英板10に絶縁性基板1aの表面を貼付け
る。
Next, as shown in Fig. 1 (b), the thickness is about 2000Å
After forming the conductor layer 8 made of a Ti layer and connected to the source 3 through the opening on the polyimide layer 7, the surface of the insulating substrate 1a is attached to the quartz plate 10 via the photoresist film 9.

次に、第1図(c)に示すように、裏面を研磨すること
により厚さが約30μmになった絶縁性基板1にソース3
に達する貫通孔A及び半導体チップに分割するためのス
クライブ溝Bを形成する。
Next, as shown in FIG. 1 (c), the source 3 is formed on the insulating substrate 1 whose thickness is about 30 μm by polishing the back surface.
A through hole A reaching up to and a scribe groove B for dividing into semiconductor chips are formed.

次に、第1図(d)に示すように、メッキにより貫通孔
をAuからなりかつソース3と接続した導体層11で充填す
る。
Next, as shown in FIG. 1D, the through hole is filled with a conductor layer 11 made of Au and connected to the source 3 by plating.

次に、第1図(e)に示すように、絶縁性基板1裏面に
導体層11を介してソース3と接続した厚さ500ÅのTi層
と厚さ2000ÅのAu層からなるメッキ用の導体層12を形成
し、スクライブ溝の部分にホトレジスト膜13を形成した
後、Auメッキにより厚さ50μmの導体層14を形成する。
Next, as shown in FIG. 1 (e), a conductor for plating consisting of a Ti layer having a thickness of 500Å and an Au layer having a thickness of 2000Å connected to the source 3 via the conductor layer 11 on the back surface of the insulating substrate 1. After forming the layer 12 and forming the photoresist film 13 in the scribe groove portion, the conductor layer 14 having a thickness of 50 μm is formed by Au plating.

次に、第1図(f)に示すように、スクライブ溝部分の
ホトレジスト膜13を除去した後、スクライブ線の部分で
半導体チップに分割し、更にホトレジスト膜9を溶解除
去することにより石英板10から半導体チップを分離す
る。
Next, as shown in FIG. 1 (f), after removing the photoresist film 13 in the scribe groove portion, it is divided into semiconductor chips at the scribe line portion, and the photoresist film 9 is dissolved and removed to dissolve the quartz plate 10. The semiconductor chip is separated from.

最後に、Ti層からなる導体層8を弗酸−硫酸系のエッチ
ング液で除去した後、更にヒドラジン水溶液でポリイミ
ド膜を取り除けば、第1図(g)に示すGaAsFETを含む
半導体装置ができる。
Finally, the conductor layer 8 made of a Ti layer is removed with a hydrofluoric acid-sulfuric acid-based etching solution, and then the polyimide film is removed with an aqueous solution of hydrazine to obtain a semiconductor device including a GaAs FET shown in FIG. 1 (g).

第2図は本発明の第2の実施例を説明するための半導体
チップの断面図である。
FIG. 2 is a sectional view of a semiconductor chip for explaining the second embodiment of the present invention.

この第2の実施例は、第2図に示すように、絶縁膜6の
上にポリイミド膜7を形成せずに直接厚さが2000Å程度
のTi層からなる導体層8を形成した後、ホトレジスト膜
9によって石英板10に絶縁性基板1aの表面を貼付ける。
In the second embodiment, as shown in FIG. 2, a polyimide layer 7 is not formed on the insulating film 6 and a conductor layer 8 made of a Ti layer having a thickness of about 2000Å is directly formed on the insulating film 6 and then a photoresist is formed. The surface of the insulating substrate 1a is attached to the quartz plate 10 by the film 9.

以降、第1の実施例と同様の工程により、第1図(g)
に示すGaAsFETを含む半導体装置ができる。
Thereafter, the same steps as those in the first embodiment are carried out, and the process shown in FIG.
A semiconductor device including the GaAs FET shown in can be obtained.

ただし、この第2の実施例では、ポリイミド膜7が無い
ので、Ti層からなる導体層8を弗酸−硫酸系エッチング
液で除去するときに、下の絶縁膜6表面も若干エッチン
グされるが、ポリイミド膜7を形成する工程が不要とな
り製造工程が第1の実施例よりも短縮される。
However, since the polyimide film 7 is not provided in the second embodiment, the surface of the insulating film 6 below is also slightly etched when the conductor layer 8 made of the Ti layer is removed with a hydrofluoric acid-sulfuric acid based etching solution. Since the step of forming the polyimide film 7 is unnecessary, the manufacturing process is shortened as compared with the first embodiment.

又、本発明の実施例では、ソース3と接続した導体層8
としてTi層を用いているが、勿論導電性ガラスのような
透明な導体層を用いても良い。
In the embodiment of the present invention, the conductor layer 8 connected to the source 3 is also used.
Although a Ti layer is used as the above, of course, a transparent conductor layer such as conductive glass may be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明では、絶縁性基板裏面から表
面に至る貫通孔を埋込む姿態の導体層を形成し、絶縁性
基板の裏面、特に貫通孔の部分を、平坦にすることによ
り、裏面のメッキ層からなる導体層を均一に形成するこ
とができるという効果がある。
As described above, in the present invention, by forming a conductor layer in a state of filling a through hole from the back surface of the insulating substrate to the front surface, and flattening the back surface of the insulating substrate, particularly the through hole portion, There is an effect that the conductor layer composed of the plated layer can be uniformly formed.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(g)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図、第2図
は本発明の第2の実施例を説明するための半導体チップ
の断面図、第3図(a)〜(e)は従来の半導体装置の
製造方法の第1の例を説明するための工程順に示した半
導体チップの断面図、第4図は従来の半導体装置の製造
方法の第2の例を説明するための半導体チップの断面図
である。 1,1a……絶縁性基板、2……能動層、3……ソース、4
……ゲート、5……ドレイン、6……絶縁膜、7……ポ
リイミド膜、8……導体層、9……ホトレジスト膜、10
……石英板、11,12,12′……導体層、13,13′……ホト
レジスト膜、14,14′……導体層、A,A′……貫通孔、B,
B′……スクライブ溝。
1 (a) to 1 (g) are sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIG. 2 is for explaining the second embodiment of the present invention. 3A to 3E are sectional views of the semiconductor chip shown in the order of steps for explaining the first example of the conventional method for manufacturing a semiconductor device, and FIG. FIG. 9 is a cross-sectional view of a semiconductor chip for explaining a second example of the method for manufacturing the semiconductor device of FIG. 1, 1a ... Insulating substrate, 2 ... Active layer, 3 ... Source, 4
... gate, 5 ... drain, 6 ... insulating film, 7 ... polyimide film, 8 ... conductor layer, 9 ... photoresist film, 10
...... Quartz plate, 11,12,12 '... Conductor layer, 13,13' ... Photoresist film, 14,14 '... Conductor layer, A, A' ... Through hole, B,
B '... scribe groove.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板表面に形成した所定のパターン
の第1の導体層の上に開孔部を備えた絶縁膜を前記絶縁
性基板表面上に形成する工程、前記絶縁膜上に前記開孔
部を通して第1の導体層と接続した第2の導体層を形成
する工程、前記絶縁性基板に裏面から前記第1の導体層
にいたる貫通孔を形成する工程、メッキにより前記貫通
孔に第3の導体層を前記絶縁性基板の裏面とほぼ同一平
面上の高さまで充填して前記第1の導体層から前記絶縁
性基板裏面に到る引き出し用の導体層を形成する工程と
を有することを特徴とする半導体装置の製造方法。
1. A step of forming, on the surface of the insulating substrate, an insulating film having openings on the first conductor layer having a predetermined pattern formed on the surface of the insulating substrate. A step of forming a second conductor layer connected to the first conductor layer through an opening, a step of forming a through hole from the back surface to the first conductor layer in the insulating substrate, and a step of plating the through hole Filling the third conductor layer to a height substantially flush with the back surface of the insulative substrate to form a conductor layer for extraction from the first conductor layer to the back surface of the insulative substrate. A method of manufacturing a semiconductor device, comprising:
JP3696487A 1987-02-19 1987-02-19 Method for manufacturing semiconductor device Expired - Lifetime JPH0682692B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3696487A JPH0682692B2 (en) 1987-02-19 1987-02-19 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3696487A JPH0682692B2 (en) 1987-02-19 1987-02-19 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63204663A JPS63204663A (en) 1988-08-24
JPH0682692B2 true JPH0682692B2 (en) 1994-10-19

Family

ID=12484415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3696487A Expired - Lifetime JPH0682692B2 (en) 1987-02-19 1987-02-19 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0682692B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2715016B2 (en) * 1991-06-14 1998-02-16 株式会社三協精機製作所 Hall element and method of manufacturing hall element
JP2009054659A (en) * 2007-08-24 2009-03-12 Fuji Electric Device Technology Co Ltd Method for manufacturing gallium nitride semiconductor device

Also Published As

Publication number Publication date
JPS63204663A (en) 1988-08-24

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