JPH0682786B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0682786B2 JPH0682786B2 JP63019989A JP1998988A JPH0682786B2 JP H0682786 B2 JPH0682786 B2 JP H0682786B2 JP 63019989 A JP63019989 A JP 63019989A JP 1998988 A JP1998988 A JP 1998988A JP H0682786 B2 JPH0682786 B2 JP H0682786B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- diode
- semiconductor integrated
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
Landscapes
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に電源の共通イ
ンピーダンスによる雑音の回り込みが問題となるアナロ
グ・デジタル混在型の半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a mixed analog / digital semiconductor integrated circuit device in which noise sneak due to a common impedance of a power source poses a problem.
従来、この種の半導体集積回路装置として第２図に示す
ものが用いられている。第２図において、半導体基板１
上で第１の電源電圧が与えられ直接に接続されていない
第１の電源端子２及び第２の電源端子３と、第２の電源
電圧が与えられ直接に接続されていない第３の電源端子
４及び第４の電源端子５がそれぞれアナログ回路ブロッ
ク６と、デジタル回路ブロック７に接続され、アナログ
回路ブロック６と、デジタル回路ブロック７は半導体集
積回路装置内で同一の電源電圧に対して共通インピーダ
ンスをもたないようになっている。Conventionally, the semiconductor integrated circuit device of this type shown in FIG. 2 has been used. In FIG. 2, the semiconductor substrate 1
A first power supply terminal 2 and a second power supply terminal 3 to which the first power supply voltage is applied and are not directly connected, and a third power supply terminal to which the second power supply voltage is applied and are not directly connected The fourth and fourth power supply terminals 5 are respectively connected to the analog circuit block 6 and the digital circuit block 7, and the analog circuit block 6 and the digital circuit block 7 have a common impedance with respect to the same power supply voltage in the semiconductor integrated circuit device. It does not have to.
上述した従来の半導体集積回路装置は、ICパッケージに
アセンブリするときや、パッケージング後プリント基板
上に実装されるまでの間に、静電気等によって同一の電
源電圧を供給し直接接続していない電源端子間に高い電
圧が印加されると、破壊され易いという欠点があった。The above-mentioned conventional semiconductor integrated circuit device supplies the same power supply voltage by static electricity or the like to the power supply terminals that are not directly connected when assembled in an IC package or before being mounted on a printed circuit board after packaging. If a high voltage is applied between them, there is a drawback that they are easily broken.
本発明の目的は前記課題を解決した半導体集積回路装置
を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that solves the above problems.
上記目的を達成するため、本発明に係る同一の電源電圧
を互いに直接接続していない複数の電源端子より供給す
る半導体集積回路装置においては、第１のダイオードの
アノードと第２のダイオードのカソードを接続し、該第
２のダイオードのアノードと該第１のダイオードのカソ
ードを接続した回路を、前記複数の電源端子間に挿入し
接続したものである。In order to achieve the above object, in the semiconductor integrated circuit device which supplies the same power supply voltage according to the present invention from a plurality of power supply terminals which are not directly connected to each other, the anode of the first diode and the cathode of the second diode are A circuit in which the anode of the second diode and the cathode of the first diode are connected to each other is inserted between the plurality of power supply terminals and connected.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の回路図である。第１図にお
いて、半導体基板１上に形成されたアナログ回路ブロッ
ク６に第１の電源電圧を供給する第１の電源端子２と第
２の電源電圧を供給する第３の電源端子４を接続し、デ
ジタル回路ブロック７に、第１の電源電圧を供給する第
２の電源端子３と第２の電源電圧を供給する第４の電源
端子５を接続した構成において、第１のダイオード８の
アノードと第２のダイオード９のカソードを接続し、該
第２のダイオード９のアノードと該第１のダイオード８
のカソードを接続した回路を第１の電源端子２と第２の
電源端子３の間に挿入接続し、第３のダイオード10のア
ノードと第４のダイオード11のカソードを接続し、第４
のダイオード11のアノードと第３のダイオード10のカソ
ードを接続した回路を第３の電源端子４と第４の電源端
子５の間に挿入接続している。FIG. 1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, a first power supply terminal 2 for supplying a first power supply voltage and a third power supply terminal 4 for supplying a second power supply voltage are connected to an analog circuit block 6 formed on a semiconductor substrate 1. In the configuration in which the second power supply terminal 3 for supplying the first power supply voltage and the fourth power supply terminal 5 for supplying the second power supply voltage are connected to the digital circuit block 7, the anode of the first diode 8 and The cathode of the second diode 9 is connected, and the anode of the second diode 9 and the first diode 8 are connected.
The circuit in which the cathode of is connected is inserted and connected between the first power supply terminal 2 and the second power supply terminal 3, and the anode of the third diode 10 and the cathode of the fourth diode 11 are connected,
A circuit in which the anode of the diode 11 and the cathode of the third diode 10 are connected is inserted and connected between the third power supply terminal 4 and the fourth power supply terminal 5.
シリコン系のダイオードでは、アノードとカソード間の
電圧差が順方向で0.7V程度、逆方向で20V程度以上ない
と電流は流れないから、少なくとも0.7V以下の電源雑音
はデジタル回路ブロック７からアナログ回路ブロック６
に回り込むことはない。In a silicon diode, current does not flow unless the voltage difference between the anode and cathode is about 0.7 V in the forward direction and about 20 V or more in the reverse direction. Therefore, at least 0.7 V or less of power supply noise is generated from the digital circuit block 7 to the analog circuit. Block 6
There is no turning around.
以上説明したように本発明は第１のダイオードのアノー
ドと第２のダイオードのカソードを接続し第２のダイオ
ードのアノードと第１のダイオードのカソードを接続し
た回路を、同一の電源電圧を供給し互いに直接接続して
いない電源端子間に挿入接続することによって、同一の
電源電圧を供給し互いに直接接続していない電源端子間
にダイオードの順方向のオン電圧以上の電圧が静電気等
によって印加されても、ダイオードがオンし電荷がダイ
オードを通り放電されるので、半導体集積回路装置の回
路ブロック内で破壊が発生しないという効果がある。As described above, the present invention supplies the same power supply voltage to a circuit in which the anode of the first diode and the cathode of the second diode are connected and the anode of the second diode and the cathode of the first diode are connected. By inserting and connecting between power terminals that are not directly connected to each other, the same power supply voltage is supplied, and a voltage higher than the forward voltage of the diode is applied by static electricity between power terminals that are not directly connected to each other. However, since the diode is turned on and the electric charge is discharged through the diode, there is an effect that no breakdown occurs in the circuit block of the semiconductor integrated circuit device.
第１図は本発明の半導体集積回路装置を示す回路図、第
２図は従来の半導体集積回路装置を示す回路図である。 １……半導体基板、2,3,4,5……電源端子 ６……アナログ回路ブロック ７……デジタル回路ブロック 8,9,10,11……ダイオードFIG. 1 is a circuit diagram showing a semiconductor integrated circuit device of the present invention, and FIG. 2 is a circuit diagram showing a conventional semiconductor integrated circuit device. 1 ... Semiconductor substrate, 2,3,4,5 ... Power supply terminal 6 ... Analog circuit block 7 ... Digital circuit block 8,9,10,11 ... Diode
Claims (1)
い複数の電源端子より供給する半導体集積回路装置にお
いて、第１のダイオードのアノードと第２のダイオード
のカソードを接続し、該第２のダイオードのアノードと
該第１のダイオードのカソードを接続した回路を、前記
複数の電源端子間に挿入し接続したことを特徴とする半
導体集積回路装置。1. In a semiconductor integrated circuit device supplying the same power supply voltage from a plurality of power supply terminals which are not directly connected to each other, an anode of a first diode and a cathode of a second diode are connected to each other, and A semiconductor integrated circuit device, wherein a circuit in which an anode of a diode is connected to a cathode of the first diode is inserted and connected between the plurality of power supply terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63019989A JPH0682786B2 (en) | 1988-01-30 | 1988-01-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63019989A JPH0682786B2 (en) | 1988-01-30 | 1988-01-30 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01196156A JPH01196156A (en) | 1989-08-07 |
| JPH0682786B2 true JPH0682786B2 (en) | 1994-10-19 |
Family
ID=12014584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63019989A Expired - Lifetime JPH0682786B2 (en) | 1988-01-30 | 1988-01-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682786B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007013145A1 (en) * | 2005-07-27 | 2007-02-01 | Renesas Technology Corp. | Semiconductor integrated circuit |
-
1988
- 1988-01-30 JP JP63019989A patent/JPH0682786B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01196156A (en) | 1989-08-07 |
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